This document discusses trends and challenges in VLSI technology. It notes that Moore's law of transistor density doubling every 18 months has continued to drive semiconductor scaling. However, smaller geometries create challenges like increased power consumption and reliability issues. Future progress will require advances in areas like low-power design techniques, fault tolerance, and active power management to balance performance with other constraints as technology scales.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
TYPES OF PLACEMENT,GOOD PLACEMENT VS. BAD PLACEMENT ,ALGORITHMS, ASIC DESIGN FLOW DIAGRAM,DEFINITION OF PLACEMENT,TECHNIQUES USED FOR PLACEMENT,PLACEMENT TRENDS,SOLUTIONS
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Very Large Scale Integration is the technology used now a day everywhere. Diploma as well as degree students can refer this
(For Downloads, send me mail
agarwal.avanish@yahoo.com)
Power gating is the main power reduction techniques for the static power. As long as technology scaling is taking place, static power becomes paramount important factor to the VLSI designs.Therefore Power gating is the recent power reduction technique that is actively in research areas.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
In this project, we compare the working of the four 8- bit multipliers like Wallace tree multiplier, Array multiplier, Baugh-Wooley multiplier and Vedic multiplier by simulating each of them separately. This is a very important criterion because in the fabrication of chips and the high-performance system requires components which are as small as possible.
If you any doubts regarding project.......then to a mail(saikiranpanjala@gmail.com)
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
TYPES OF PLACEMENT,GOOD PLACEMENT VS. BAD PLACEMENT ,ALGORITHMS, ASIC DESIGN FLOW DIAGRAM,DEFINITION OF PLACEMENT,TECHNIQUES USED FOR PLACEMENT,PLACEMENT TRENDS,SOLUTIONS
I made this presentation for you , I hope its useful for you all, and I hate Plagiarism please, I also used some slides here but I mentioned all in the last slide :)
Hope you can get benefits from it
Very Large Scale Integration is the technology used now a day everywhere. Diploma as well as degree students can refer this
(For Downloads, send me mail
agarwal.avanish@yahoo.com)
Power gating is the main power reduction techniques for the static power. As long as technology scaling is taking place, static power becomes paramount important factor to the VLSI designs.Therefore Power gating is the recent power reduction technique that is actively in research areas.
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
I have prepared it to create an understanding of delay modeling in VLSI.
Regards,
Vishal Sharma
Doctoral Research Scholar,
IIT Indore
vishalfzd@gmail.com
DESIGN AND SIMULATION OF DIFFERENT 8-BIT MULTIPLIERS USING VERILOG CODE BY SA...Saikiran Panjala
In this project, we compare the working of the four 8- bit multipliers like Wallace tree multiplier, Array multiplier, Baugh-Wooley multiplier and Vedic multiplier by simulating each of them separately. This is a very important criterion because in the fabrication of chips and the high-performance system requires components which are as small as possible.
If you any doubts regarding project.......then to a mail(saikiranpanjala@gmail.com)
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
The low power has been the main concern for the VLSI industry with the technology scaling in CMOS process from 130 nm to 22nm. The presentation here gives a brief idea about the several low power VLSI techniques being used in VLSI circuits to reduce the power and delay. for any query feel free to visit us at: http://www.siliconmentor.com/
It is a presentation for the Embedded System Basics. It will be very useful for the engineering students who need to know the basics of Embedded System.
Implementation of High Reliable 6T SRAM Cell Designiosrjce
Memory can be formed with the integration of large number of basic storing element called cells.
SRAM cell is one of the basic storing unit of volatile semiconductor memory that stores binary logic '1' or '0' bit.
Modified read and write circuits were proposed in this paper to address incorrect read and write operations in
conventional 6T SRAM cell design available in open literature. Design of a new highly reliable 6T SRAM cell
design is proposed with reliable read, write operations and negative bit line voltage (NBLV). Simulations are
carried out using MENTOR GRAPHICS
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
Low power requirement has become a principal motto in today’s world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progres...IJECEIAES
The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
In today’s modern electronics industries energy or power efficiency is most important feature to increase the speed, portability, reliability, popularity and efficiency of electronic products. Reduction in power consumption or low power requirement for a system adds features of low cost, high speed, more efficiency and reliability. CMOS technology is a popular name in the field of low power systems. In the field of CMOS technology various methods are used to make the systems more power efficient like, use of Sleepy transistors, Stack method in which transistor length or width is increased to get reduction in leakage power, use of pre-computation technique with the use of BDD (Binary Decision Diagram), use of SRAM (Static Random Access Memory) for high speed operations. In this paper we survey low power systems in which various techniques are used to reduce the power consumption in different circuit areas of the system to get more power efficient and cost effective electronic systems.
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2. OVERVIEW
Introduction
Technology Scaling
Challenges in DSM digital design
Design challenges of technology Scaling
Design challenges of low power
Active power management
Leakage power management
Challenges in VLSI circuit reliability
Future direction in microprocessors systems
Conclusion
3. In the last three decades the world of computers and
especially that of microprocessors has been advanced at
exponential rates in both productivity and performance. The
integrated circuit industry has followed a steady path of
constantly shrinking devices geometries and increased
functionality that larger chips provide. The technology that
enabled this exponential growth is a combination of
advancements in process technology, microarchitecture,
architecture and design and development tools.
4. Each new generation has approximately doubled logic circuit density
and increased performance by about 40% .
Moore’s law:
In 1965, Gordon Moore noted that the number of transistors on a chip
doubled every 18 to 24 months.
He made a prediction that semiconductor technology would double its
effectiveness every 18 months
Moore’s law continues to drive the scaling of CMOS technology. The
feature size of the transistor now has been shrunk well into Nano-scale
region.
A large single VLSl chip can contain over one billion transistor.
5. The ever-increasing level of integration has enabled higher
performance and richer feature sets on a single chip.
As the geometry of the transistor is getting smaller and the
number of transistors on a single chip grows exponentially, the
power management for a state-of-the-art VLSI design has become
increasingly important.
To maintain the performance trend of the vlsi system as the
technology scaling continues, many advanced design techniques,
especially in power management, have to be employed in order to
achieve a balanced design to meet platform and end-user needs.
6. INTRODUCTION
During the past 40 years the semiconductor VLSI IC industry has
distinguished itself both by rapid pace of performance improvements
in its products, and by a steady path of constantly shrinking device
geometries and increasing chip size.
The speed and integration density of IC’s have dramatically improved.
Exploitation of a billion transistor capacity of a single VLSI IC
requires new system paradigms and significant improvements to
design productivity.
Structural complexity can be increased by having more productive
design methods and by putting more resources in design work.
7. According to International Technology Roadmap for Semiconductor
(IRTS) projections, the number of transistors per chip and the local
clock frequencies for high-performance microprocessors will continue
to grow exponentially in the next 10 years too.
8. The general trends, that we expect in the next ten years, according to
ITRS projections concerning:
Increasing of transistor count for microprocessors and DRAM
memory elements.
Shrinking of linewidths of IC’s.
Growing chip die sizes and Increasing semiconductor fabrication
process complexity
10. CHALLENGES IN DSM DIGITAL DESIGN
Microscopic Issue Macroscopic Issue
Ultra high speed design Time to market
Interconnect Millions of gates
Noise , Crosstalk High-Level Abstractions
Reliability, Manufacturability Reuse & IP: Portability
Power Dissipation Predictability
Clock distribution Etc…..
11. Exponential growth rates have occurred for other aspects of computer
technology such as clock speed and processor performance.
Shrinking linewidths not only enables more components to fit onto an
IC (typically 2x per linewidth generation) but also lower costs
(typically 30% per linewidth generation).
12. Shrinking linewidths have slowed down the rate of growth in die size to
1.14x per year versus 1.38 to 1.58x per year for transistor counts, and
since the mid-nineties accelerating linewidth shrinks have halted and
even reversed the growth in die sizes.
13. Shrinking linewidths isn’t free. Linewidth shrinks require process
modifications to deal with a variety of issues that come up from
shrinking the devices - leading to increasing complexity in the
processes being used
Design Challenges of Technology Scaling:
Advances in optical lithography have allowed manufacturing of on -
chip structures with increasingly higher resolution.
The area, power, and speed characteristics of transistors with a
planar structure, such as MOS devices, improve with the decrease
(i.e. scaling) in the lateral dimensions of the devices. Therefore, these
technologies are referred as scalable
14. Generally, scalable technology has three main goals:
Reduce gate delay by 30%, resulting in an increase in Operating
frequency of about 43%
Double transistor density and
Reduce energy per transition by about 65%, saving 50% of power, at a
43% increase in frequency
Scaling a technology reduces gate by 30% and the lateral and vertical
dimensions by 30%. Therefore, the area and fringing capacitance, and
consequently the total capacitance, decrease by 30% to 0.7 from nominal
value normalized to 1. Since the dimensions decrease by 30%, the die area
decrease by 50%, and capacitance per unit of area increases by 43%
15. DESIGN CHALLENGES OF LOW POWER
The electronic devices at the heart of such products need to dissipate
low power, in order to conserve battery life and meet packaging
reliability constraints.
Lowering power consumption is important not only for lengthening
battery life in portable systems, but also for improving reliability, and
reducing heat-removal cost in high-performance systems.
Consequently, power consumption is a dramatic problem for all
integrated circuits designed today
Following figure shows the relative impact on power consumption of
each phase of the design process. Essentially higher - level categories
have more effect on power reduction.
16. Low power design in terms of algorithms, architectures, and circuits has
received significant attention and research input over the last decade.
Higher System level Design partitioning, Power down
Impact
Complexity, concurrency, locality,
Algorithm level
Regularity, Data representation
Architecture Voltage Scaling, Parallelism,
level Instruction set, Signal correlation
Transistor sizing, Logical
optimization, Activity driven power
Circuit level down, Low swing logic, Adiabatic
Switching
Process device Threshold Reduction, Multi
level Threshold
17. ACTIVE POWER MANAGEMENT:
Reducing Switching Activities:
For a high-frequency digital design, the clock power often represents a significant
portion of the overall switching power.
The clock signals are driving a large number of sequential elements in a
synchronized system.
The frequency scaling continues to drive up the overall use of the timing elements,
including latches and flip-flops.
One of the most effective ways to reduce the switching power is through clock
gating.
By dividing the chip into different clock domains and gating the clock signals
with block enable signals, it can greatly reduce the overall chip power.
18. Dynamic Voltage swing:
To ensure a chip provide a high-level of performance while not getting
into reliability issues induced by on-die over-heating, an ability to
intelligently scale both voltage and frequency dynamically.
The power and frequency scaling can be managed through either
operating system or can be triggered in flight by many on-die thermal
sensors that are positioned strategically across the die
The on-die thermal sensor is critical in managing the “hot-spots”
where junction temperature could exceed reliability limit if now
controlled.
19. LEAKAGE POWER MANAGEMENT
Sleep transistor:
As transistor geometry gets smaller, the leakage components, including
both sub threshold and gate leakage, have become more and more.
The leakage power can potentially take up a significant portion of the
overall chip power.
One of the most effective techniques in reducing the transistor leakage is
to introduce sleep transistor between normal circuit block and power
supply rails, either or both VCC and VSS.
The sleep transistors can be shut off completely during idle state or
whenever the blocks are not being accessed.
20. When the sleep transistors are turned off, the power supplies at VCC and
or VSS across the function block will be collapsing towards the middle.
As a result, the voltage difference across the transistor gate as well as
source and drain is lowered, which reduces the leakage significantly.
Multiple Power Supplies:
Since each functional block on a chip often requires different supply
voltage in order to achieve optimal power and performance trade off at
local level.
One effective way to minimize the power consumption is to introduce
different power supplies locally.
21. When certain circuit blocks are in idle state, a lower power supply can be
given to keep the leakage power at minimum.
When the circuits are in active state, a higher power supply can be given
to provide optimum performance.
Frequency Scaling:
The figure shows that the
voltage level is decreasing
due to the scaling of the size
of the channel.
22. The average number of gate delays in a clock period is decreasing
because both the new microarchitectures use shorter pipelines for static
gates, and because the advanced circuit techniques reduce the critical
path delays even further. This could be the main reason that the
frequency is doubled in every technology generation.
23. The twofold frequency improvement for each technology generation is
primarily due to the following factors
The reduced number of gates employed in a clock period, what
makes the design more pipelined.
Advanced circuit design techniques that reduce the average gate
delay beyond 30% per generation.
24. CHALLENGES IN VLSI CIRCUIT RELIABILITY
Shrinking geometries, lower power voltages, and higher frequencies
have a negative impact on reliability. Together, they increase the number
of occurrences of intermittent and transient faults.
Faults experienced by semiconductor devices fall into three main
categories: permanent, intermittent, and transient.
Permanent Faults:
Permanent faults reflect irreversible physical changes. The
improvement of semiconductor design and manufacturing techniques has
significantly decreased the rate of occurrence of permanent faults.
25. The Figure shows the evolution of permanent - fault rates for CMOS
microprocessors and static and dynamic memories over the past decade.
The semiconductor industry is widely adopting copper interconnects. This
trend has a positive impact on permanent - faults rate of occurrence, as
copper provides a higher electro migration threshold than aluminium
does.
26. Intermittent Faults
Intermittent faults occur because of unstable or marginal hardware;
they can be activated by environmental changes, like higher or lower
temperature or voltage. Many times intermittent precede the occurrence of
permanent faults.
Transient faults
Transient faults occur because of temporary environmental
conditions. Several phenomena induce transient faults: neutron and alpha
particles; power supply and interconnect noise, electromagnetic
interference, and electrostatic discharge.
27. Higher VLSI integration and lower supply voltages have contributed to
higher occurrence rates for particle - induced transients, also known as
soft errors.
Following plot measured neutron - and alpha - induced soft errors rates
(SERs) for CMOS SRAMs as a function of memory capacity.
28. FAULT AVOIDANCE AND FAULT TOLERANCE
Fault avoidance and fault tolerance are the main approaches used to
increase the reliability of VLSI circuits.
Fault avoidance relies on improved materials, manufacturing processes,
and circuit design. For instance, lower - alpha emission interconnect
and packaging materials contribute to low SERs.
Silicon on insulator is commonly used process solution for lower
circuit sensitivity to particle - induced transients
29. Fault tolerance is implementable at the circuit or system level. It relies on
concurrent error detection, error recovery, error correction codes (CEDs), and
space or time redundancy.
Intermittent and transient faults are expected to represent the main source of
errors experienced by VLSI circuits.
Failure avoidance, based on design technologies and process technologies,
would not fully control intermittent and transient faults.
Fault - tolerant solutions, presently employed in custom – designed systems,
will become widely used in off-the-shelf ICs tomorrow, i.e. in mainstream
commercial applications.
30. The transient errors we will consider the influences of changes in the
supply voltage referred to as power supply noise. Power supply noise
adversely affects circuit operation through the following mechanisms:
a) signal uncertainty
b) on-chip clock jitter
c) noise margin degradation and
d) degradation of gate oxide reliability.
For correct circuit operation the supply levels have to be maintained
within a certain range near the nominal voltage levels.
This range is called the power noise margin.
31. The primary objective in the design of the distribution system is to
supply sufficient current to each transistor on an integrated circuit
while ensuring that the power noise does not exceed the target noise
margins.
As an illustration, the evolution of the average current of high-
performance Intel family of microprocessors is given in Figure.
32. FUTURE DIRECTIONS IN MICROPROCESSOR
SYSTEMS
Deep-submicron technology allows billions of transistors on a single die,
potentially running at gigahertz frequencies.
According to Semiconductor Industry Association projections, the
number of transistor per chip and the local clock frequencies for high
performance microprocessors will continue to grow exponentially in the
near future, as it is illustrated in Figure below.
This ensures that future microprocessors will become even more
complex.
33.
34. CONCLUSION
As technology scales, important new opportunities emerge for VLSI
ICs designers. Understanding technology trends and specific applications is
the main criterion for designing efficient and effective chips. There are
several difficult and exciting challenges facing the design of complex ICs.
To continue its phenomenal historical growth and continue to follow
Moore’s law, the semiconductor industry will require advances on all fronts
– from front-end process and lithography to design innovative high-
performance processor architectures, and SoC solutions. The roadmap’s goal
is to bring experts together in each of these fields to determine what those
challenges are, and potentially how to solve them.