The document discusses design for testability (DFT) techniques. It explains that DFT is important for testing integrated circuits due to unavoidable manufacturing defects. DFT aims to increase testability by making internal nodes more controllable and observable. Common DFT techniques mentioned include adding scan chains, which allow testing at speed by launching test vectors from a shift register. Stuck-at fault and transition fault models are discussed as well as methods for detecting these faults including launch-on-capture and launch-on-shift. Fault equivalence and collapsing techniques are also summarized.

1. Kumar Gavanurmath
Design For Testability

2. Agenda
 Importance of Testing.
 What is Testability.
 What is DFT? Why?
 DFT Technique.
 Manufacturing Defects.
 Fault Modelling.
 Methods To Test Transition Fault.
 Fault Equivalence / collapsing.
 Structured Approach.

3. Importance of Testing
§ According to Moore’s law feature size is decreasing.
 defects are unavoidable.
§ Testing is required to guarantee fault-free chips.
§ Product quality depends on the following parameters,
ü Test cost
ü Test quality
ü Test time
§ DFT – “The game changer”

4. What is Testability?
 The ability to put a design into a known initial state, and then control
and observe internal signal values.
 Circuit without DFFs: Circuit is controllable and observable.
 Circuit with DFFs: Low testability.
 Two basic properties determine the testability of a node:
 Controllability
 The ability to set node to a specific value.
 Observability
 The ability to observe a node’s value.

5. What is DFT?
 DFT refers to hardware design styles, or added hardware that reduces
test generation complexity.
 Philosophy of DFT is Murphy's law:- ”whatever can go wrong, will go
wrong.”
 Motivation:- : Test generation complexity increases exponentially with
the size of the circuit.
 Basically DFT enables the manufacturing test.
 It is a structural technique, which facilitates a design to become testable
after production .

6. Why DFT
 To increase Productivity:
Shorter time-to-market
Reduced design cycle
Reduced cost
 To improve Quality:
Reduced Defects per million (DPM)
Improved quality of test

7. DFT Technique
 Ad-hoc Technique.
Ø As name implies Ad-hoc Technique is a temporary Technique.
Ø Is a strategy to enhance the design testability without making much change
to design style.
Ø Good design practices learnt through experience are used as guidelines for
ad-hoc DFT.
 Structural Technique.
Ø Here it provides more systematic & automatic approach to enhance the
design testability.
Ø Targets manufacturing defects.

8. Manufacturing Defects
 Physical problem in silicon:
q Extra metal-causing shorts.
q Insufficient Doping.
q Contamination causing opens.
q CMOS Stuck-ON.
q CMOS Stuck-OPEN.
q Slow Transistors.

9. Cont...
 Defect: The term defect generally refers to a physical imperfection in
the processed wafer.
 Some defects are observable through the optical or electron
microscope. Others are not visible and can only be detected by
electrical tests.
 Fault: A representation of a “defect” at the abstracted function level is
called a fault.
 Error: A wrong output signal produced by a defective system is called
an error.
 Failure: Repeated occurrence of the same defect indicates the need for
improvements in the manufacturing process or the design of the device.
Procedures for diagnosing defects and finding their causes are known
as failure mode analyses (FMA).

10. Fault Modelling
 Due to defect during manufacturing of integrated circuit, There is need to
model the possible faults that might occur during fabrication process, this is
called fault modelling.
v Stuck-at-fault.
v Transition fault.
§ Stuck-at-fault: From the beginning of the DFT single stuck-at fault model is
the most popular fault model used in practice. This is mainly due to process
variations, imperfection during photolithography and etching, the metal.
B
Y
A

11. Stuck-at-fault example
§ Fault activation
§ Fault propagation
§ Line justification
i
e
D
X
g
j
f
h
D
D
a
b=1
c
d
S-a-0
Figure Sensitization by b=1, Propagation path by e-f-g-h

12. D Algorithm
 Target a specific stuck-at-fault.
 Drive fault site to to opposite value.
 Propagate error to primary outputs.
 Generate patterns for one Stuck-at-fault at a time.
 Involve decision-making at almost every step.

13. Transition Fault Model
§ The transition fault is similar to the stuck-at fault in many respects.
§ The effect of a transition fault at any point P in a circuit is that a rising or a
falling transition at P will not reach an observable output such as a scan
flip-flop or a primary output within the desired time.
A
B
C

14. Methods To Test Transition Fault
 Delay tests require a vector pair to detect a fault.
 Since the patterns must be applied at the rated speed, at-speed
testing is needed.
 For full scan circuits, both the vectors in the scan flip-flops must be
ready for consecutive time frames to ensure atspeed testing.
 Several different methods are used to apply the vectors at-speed.
Transition faults are detected through scan chain. There are two
methods to detect transition faults.
 Skew Load or Launch-From-Shift (LOC).
 Skew Load or Launch-From-Shift (LOS).

15. Cont...
 LOC  LOS

16. Fault Equivalence / collapsing
 The gates behaves the same for any input
SA0 ,SA1 or the output SA0 ,SA1 .
 The fault after collapsing are included in the
fault universe called primary faults, the faults
after collapsing are not included in the fault
universe are called Equivalent fault of primary
faults.
 Fault Coverage = # of Detectable faults
Total no of faults
 Test Coverage = # of Detectable faults
# of Detected faults.

17. Structured Approach
 The structured DFT approach tries to boost the overall testability of a
circuit with a test oriented style methodology.
 This approach is organized and systematic with far more inevitable results.
Scan style, the most widely used structured DFT methodology, tries to
boost testability of a circuit by rising the controllability and observability of
storage elements in an exceedingly sequential style.
 Typically, this is often accomplished by converting the sequential design
into a scan design with 3 modes of operation they are,
 normal mode.
 shift mode.
 capture mode.
 Circuit operations with associated clock cycles conducted in these 3 modes
are referred to as normal operation, shift operation, and capture operation,
respectively.

18. Scan Cell Designs
 There are three types of scan cell designs, they are:
 Muxed-D scan cell.
 Clocked scan cell.
 LSSD scan cell.
 Muxed-D Scan cell:

19. Need for Scan Design
 The need for Scan design in a sequential design can be well understood by
considering a example shown in Figure below.

20. Cont...
 These scan chains are made externally accessible by connecting the scan
input of the first scan cell in a scan chain to a primary input and the output
of the last scan cell in a Scan chain to a primary output.
•
Scan design is currently the most popular structured DFT approach. It is
implemented by Connecting selected storage elements present in the
design into multiple shift registers, called Scan chains

21. Thank You