Functional verification is one of the key bottlenecks in the rapid design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary tools used in logic and functional verification of commercial integrated circuits are simulation (at various levels), emulation at the chip level, and formal verification.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Heterogeneous Systems Architecture: The Next Area of Computing Innovation AMD
Dr. Lisa Su, Senior Vice President and GM, Global Business Units, AMD keynote from ISSCC on Heterogeneous Systems Architecture: The Next Area of Computing Innovation - Case Study, The Holodeck.
Functional verification is one of the key bottlenecks in the rapid design of integrated circuits. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources and total personnel. The three primary tools used in logic and functional verification of commercial integrated circuits are simulation (at various levels), emulation at the chip level, and formal verification.
UVM is a standardized methodology for verifying complex IP and SOC in the semiconductor industry. UVM is an Accellera standard and developed with support from multiple vendors Aldec, Cadence, Mentor, and Synopsys. UVM 1.0 was released on 28 Feb 2011 which is widely accepted by verification Engineer across the world. UVM has evolved and undergone a series of minor releases, which introduced new features.
UVM provides the standard structure for creating test-bench and UVCs. The following features are provided by UVM
• Separation of tests from test bench
• Transaction-level communication (TLM)
• Sequences
• Factory and configuration
• Message reporting
• End-of-test mechanism
• Register layer
Heterogeneous Systems Architecture: The Next Area of Computing Innovation AMD
Dr. Lisa Su, Senior Vice President and GM, Global Business Units, AMD keynote from ISSCC on Heterogeneous Systems Architecture: The Next Area of Computing Innovation - Case Study, The Holodeck.
Overview of the BF609 dual-core Blackfin processor series covering main features including the Pipelined Vision Processor including the hardware and software development tools. By Analog Devices
Why Graphics Is Fast, and What It Can Teach Us About Parallel ProgrammingJonathan Ragan-Kelley
Graphics has been at the forefront of the resurgence in parallel computation. Real-time graphics and games have been the source of many of today’s new programming models and architectures for parallel computation. Modern games are arguably the only successful mainstream application of highly parallel programming in heterogeneous, million-line codebases. But while graphics is thought of as an embarrassingly parallel application, there has been little success in implementing high-performance graphics systems in any single general-purpose parallel programming model, ironically including those which have come from the GPGPU community.
I will talk about key patterns of parallelism and locality used in graphics pipelines and games, and how existing tools and monolithic programming models fail to express these patterns with sufficient efficiency. I will try to synthesize some directions for future programming systems based on this experience, including my current thoughts for how a compile-time continuation passing transform could help formalize patterns emerging in how high performance systems are manually overcoming the limitations of existing GPU programming models.
This talk will be at least as much informal, educational and speculative as it will be about any currently active research.
Slack (or Teams) Automation for Bonterra Impact Management (fka Social Soluti...Jeffrey Haguewood
Sidekick Solutions uses Bonterra Impact Management (fka Social Solutions Apricot) and automation solutions to integrate data for business workflows.
We believe integration and automation are essential to user experience and the promise of efficient work through technology. Automation is the critical ingredient to realizing that full vision. We develop integration products and services for Bonterra Case Management software to support the deployment of automations for a variety of use cases.
This video focuses on the notifications, alerts, and approval requests using Slack for Bonterra Impact Management. The solutions covered in this webinar can also be deployed for Microsoft Teams.
Interested in deploying notification automations for Bonterra Impact Management? Contact us at sales@sidekicksolutionsllc.com to discuss next steps.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
Search and Society: Reimagining Information Access for Radical FuturesBhaskar Mitra
The field of Information retrieval (IR) is currently undergoing a transformative shift, at least partly due to the emerging applications of generative AI to information access. In this talk, we will deliberate on the sociotechnical implications of generative AI for information access. We will argue that there is both a critical necessity and an exciting opportunity for the IR community to re-center our research agendas on societal needs while dismantling the artificial separation between the work on fairness, accountability, transparency, and ethics in IR and the rest of IR research. Instead of adopting a reactionary strategy of trying to mitigate potential social harms from emerging technologies, the community should aim to proactively set the research agenda for the kinds of systems we should build inspired by diverse explicitly stated sociotechnical imaginaries. The sociotechnical imaginaries that underpin the design and development of information access technologies needs to be explicitly articulated, and we need to develop theories of change in context of these diverse perspectives. Our guiding future imaginaries must be informed by other academic fields, such as democratic theory and critical theory, and should be co-developed with social science scholars, legal scholars, civil rights and social justice activists, and artists, among others.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
The Art of the Pitch: WordPress Relationships and Sales
Verification of Graphics ASICs (Part II)
1. How Shaders are Created
Application
API
GPU Driver
Video BIOS
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2. Images
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3. Display Processing
Advanced Gamma and Color Correction
No correction
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4. Display Processing
Advanced Gamma and Color Correction
Avivo Display Engine 10-bit
No correction
gamma and color correction
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5. “Call of Juarez” using DirectX 9
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6. “Call of Juarez” using DirectX 10
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8. Graphics Verification Challenges
Large complex ASICs:
Approaching 1B xtrs; >50 different clocks; > 600 MHZ; >100 top level tiles
Parallel SIMDs, Multiple pipelines; hundreds of threads in flight; >300 ALUs
High BW memory/cache interface; PCI Express; Display Ports
3rd party compliance: DirectX and OpenGL Graphic APIs and Apps
Firmware critical to ASIC function
ASIC validation utilizes firmware release as part of tape out
Firmware debug requires significant amounts of time
Full frames processing requires days/weeks of RTL simulation
Market window small – consumer market is harsh!
Schedule is KING
Need incremental development; hierarchy and reuse prior
Respins are costly; time to market is critical
Christmas, Dads/Grads, or bust!
29 May 30, 2008 AMD: DV Club - Westford MA
10. Top Level Command Processor Vertex Index Fetch
Radeon 2900
Hierarchical Z
Shader Caches
Shader Caches
Setup
Instruction &
Tessellator
Constant
Constant
Rasterizer Unit
Stream Out
Red – Compute
Geometry Vertex
Yellow – Cache Interpolators Assembler Assembler
Unified shader
Ultra-Threaded Dispatch Processor
Shader R/W
Memory Read/Write Cache
L2 Texture Cache
Instr./Const. cache
L1 Texture Cache
Texture Units
Texture Units
Texture Units
Texture Units
Unified texture cache Unified
Compression Shader
Z/Stencil Cache
4 SIMDs Processors
16 Pipelines/SIMD
5 Stream processes
(32bit FP) per pipeline Shader Export
320 ALU ops in parallel
Over 700M transistors Render Back-Ends
Color Cache
31 May 30, 2008 AMD: DV Club - Westford MA
11. Technical Solutions
Layered CODE Methodology
Multiple Layers of Testbenches
Maximize Controllability, Observability, and Debug Efficiency
Reference Model
Tools
Coverage and assertions
Visualization
HW Emulation
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12. Layered CODE Verification
Testbench Capability - Maximize Controllability, Observability, and Debug Efficiency
Level Controllability Observability Debug / Expected
(I/O; pipeline (Checking Fix Bugs
timing; results in I/O; Efficiency found for
sequencing; internal states) efficiency
internal state;
error injection)
Silicon in Lab Low Low days - ZERO
weeks
Chip/System Med: chip I/O Med hours – days Few
Block High: block I/O High minutes- Many
hours
Sub Block Max – closest Max minutes Most
to design;
internal corner
states
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13. Reference Model Methodology
C++ reference model of the DUT
One “block” = one C++ object
Non-synthesizeable => easier to write than RTL
Very fast
– Several orders of magnitude faster than the design
– Used by driver, performance teams
Transaction-level accuracy
Block-block interfaces modeled (see SystemVerilog definition)
Matches design exactly (almost)
Sub-transaction debug taps for added accuracy
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14. Testbenches
Sub-block testbenches : designer boot-strap
Block-level testbenches: constrained-
random Test
Tests written in C++
Test library in C++
Test library
– SCV, other randomization
Threaded transport layer
– Based on SystemC
– C++ to C++
– C++ to verilog
Transport
Two-pass approach
– Ref model, then RTL, then compare
Block
reference
SystemVerilog testbenches also used model OR RTL
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15. Testbenches
Chip/system testbenches
Tests written in C++
Tests debugged on chip reference model
Test
– Collection of block ref models; see prev slide
Test library in C++
– Mimics OpenGL, an industry standard OpenGL-like
test library
OR
Test portability production
Write once, run everywhere driver
– Reference model
– Design
– H/W emulation
– Lab/diags Transport
– Production drivers
Overall TTM improved Chip reference
model OR RTL
– Driver schedule is nontrivial OR emulation
OR real H/W
36 May 30, 2008 AMD: DV Club - Westford MA
16. HW Emulation
Usage:
In-Ckt Emulation of full chip design and running Chip DV and SW stack
Simulates up to 1000X faster than SW (RTL) simulation
Capable of rendering full image frames in minutes/hrs vs days/weeks
Capture/playback scenes of benchmarks and games
Pre Silicon
Verifying chip/system level functionalities and performance, block
interactions, stress
Allows for longer runs of random tests to look for hangs
Prototype and test SW drivers and Diag
Develop Boot Up settings
Post Silicon: BringUp to Production
Debug platform for silicon
Validate ECOs
37 May 30, 2008 AMD: DV Club - Westford MA
17. Coverage and Assertions
Assertions are a Good Thing
White-box testing
Designer impact on DV
Etc.
Functional coverage is a Good Thing
Deep corner cases
API spec does not show all implementation details
Etc.
Bug rates/DV closure improved greatly when func covg was adopted
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18. Visualization
It is graphics, after all
Nice to see pretty pictures
for what you are drawing
Two overlapping textured
triangles, with depth
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19. Visualization
Corruptions become easier to see; recognize patterns
Color
corruption
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20. Summary
AMD + ATI = positioned for success
Graphics business/technology has many challenges
Market window is everything
Techniques mostly leverage standard industry practice, with some twists
Reference-model-based flow
High quality is required
– Rely on coverage, constrained-random, etc.
H/W and S/W are both key to product success
– Seamless integration required
We are growing
Always looking for good people!
Shaw.Yang@amd.com
Gary.Greenstein@amd.com
41 May 30, 2008 AMD: DV Club - Westford MA