1) The document describes empirically derived power models for uncore elements like the Power Bus and memory controllers of IBM's POWER8 server processor. 2) Using a small set of activity markers like read, write, retry and snoop events along with microbenchmarks, the models can predict uncore power with up to 6% error. 3) These abstract power models allow more accurate dynamic power management by the chip compared to using a constant worst-case uncore power, potentially enabling a 5% CPU frequency boost.