This document provides a literature review on design strategies and methodologies for low power VLSI circuits. It discusses the major sources of power dissipation in CMOS circuits as leakage current, short circuit current, and power dissipated during logic transitions. The document also outlines the low power design space, including reducing voltage, physical capacitance, and logic transitions to minimize power. It describes techniques for power minimization such as reducing chip area, advanced interconnect substrates, supply voltage scaling, and better design techniques. Finally, it mentions that CAD methodologies can help reduce power at the system level, logic synthesis level, physical design level, and circuit level.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
Low power requirement has become a principal motto in today’s world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Optimized Design of an Alu Block Using Power Gating TechniqueIJERA Editor
Power is the limiting factor in traditional CMOS scaling and must be dealt with aggressively. With the scaling
of technology and the need for high performance and more functionality, power dissipation becomes a major
bottleneck for a system design. Power gating of functional units has been proved to be an effective technique to
reduce power consumption. This paper describe about to design of an ALU block with sleep mode to reduce the
power consumption of the circuit. Local sleep transistors are used to achieve sleep mode. During sleep mode
one functional unit is working and another functional unit is in idle state. i.e., it disconnects the idle logic
blocks from the power supply. Architecture and functionality of the ALU implemented on FPGA and is tested
using DSCH tool. Power analysis is carried out using MICROWIND tool.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Analysis of Power Dissipation & Low Power VLSI Chip DesignEditor IJMTER
Low power requirement has become a principal motto in today’s world of electronics
industries. Power dissipation has becoming an important consideration as performance and area for
VLSI Chip design. With reducing the chip size, reduced power consumption and power management
on chip are the key challenges due to increased complexity. Low power chip requirement in the
VLSI industry is main considerable field due to the reduction of chip dimension day by day and
environmental factors. For many designs, optimization of power is important as timing due to the
need to reduce package cost and extended battery life. This paper present various techniques to
reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power
Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level
Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors,
Dynamic Threshold MOS, Short Circuit Power Suppression.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Implementation of Area Effective Carry Select AddersKumar Goud
Abstract: In the design of Integrated circuit area occupancy plays a vital role because of increasing the necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in data processing processors for performing fast arithmetic functions. From the structure of the CSLA, the scope is reducing the area of CSLA based on the efficient gate-level modification. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the Regular CSLA is still area-consuming due to the dual Ripple-Carry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than the Regular Linear CSLA and Regular SQRT CSLA respectively. This project was aimed for implementing high performance optimized FPGA architecture. Modelsim 10.0c is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4. Then the implementation is done in Virtex5 FPGA Kit.
Keywords: Field Programmable Gate Array (FPGA), efficient, Carry Select Adder (CSLA), Square-root CSLA (SQRTCSLA).
Comparative Performance Analysis of Low Power Full Adder Design in Different ...ijcisjournal
This paper gives the comparison of performance of full adder design in terms of area, power and delay in
different logic styles. Full adder design achieves low power using the Transmission Gate logic compared to
all other topologies such as Basic CMOS, Pass Transistor and GDI techniques but it make use of more
number of transistors compared to GDI. GDI occupies less area compared to all other logic design styles.
This paper presents the simulated outcome using Tanner tools and also H-Spice tool which shows power
and speed comparison of different full adder designs. All simulations have been performed in 90nm, 45nm
and 22nm scaling parameters using Predictive Technology Models in H-Spice tool.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
The conventional transformer in power infrastructure should be capable of meeting the demand for the load. The conventional transformer is structured and designed to handle high power. Also, the overload capacity of conventional transformers depends on the highest temperature and short-term overload. This paper represents the construction and working of the solid-state transformer which consists of AC to DC and DC to AC conversion which has low overload capability as compared to conventional transformers. Solid-state transformer finding applications in Solar and wind power generation electric vehicle battery management systems because of high-frequency operation, which is not possible in case of conventional transformers also smart transformer, provides flexible control of electric power distribution.
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
With Increase in Portable devices, VLSI chips has to consider about Power usages in VLSI silicon chips. So Power Aware design and verification is so important in Industry. To get basic knowledge on Low Power Design and Verification with UPF basics Go through this Slides.
Sources of Power Dissipation
Dynamic Power Dissipation
Static Power Dissipation
Power Reduction Techniques
Algorithmic Power Minimization
Architectural Power Minimization
Logic and Circuit Level Power Minimization
Control Logic Power Minimization
System Level Power Management.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
The conventional transformer in power infrastructure should be capable of meeting the demand for the load. The conventional transformer is structured and designed to handle high power. Also, the overload capacity of conventional transformers depends on the highest temperature and short-term overload. This paper represents the construction and working of the solid-state transformer which consists of AC to DC and DC to AC conversion which has low overload capability as compared to conventional transformers. Solid-state transformer finding applications in Solar and wind power generation electric vehicle battery management systems because of high-frequency operation, which is not possible in case of conventional transformers also smart transformer, provides flexible control of electric power distribution.
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Adiabatic describe the thermodynamic processes in which there is no energy exchange with the environment, and therefore very less dissipated energy loss. These circuits are low power circuits which use reversible logic to conserve energy. Adiabatic logic works with the concept of switching activities which reduces the power by giving stored energy back to the supply. The main design changes are focused on power clock which plays the vital role in the principle of operation. This has been used because many adiabaticcircuits use a combined power supply and clock, or a power clock (Four Phase).To achieve this, the power supply of adiabatic logic circuits have used time varying voltage charging signal, in contrast to traditional non-adiabatic systems that have generally used constant voltage charging from a fixed-voltage power supply. Thereby the circuit topology and operation of the circuit has been changed so that the source current of CMOS transistor change its direction and goes back to the supply(Recovery) when the power clock falls from VDD to zero. Power efficient blocks can be designed by using adiabatic logic which can be used in combinational and sequential circuits. The simulation of the designs is done using a backend tool called MENTOR GRAPHICS in 130nm technology
A Survey Paper on Leakage Power and Delay in CMOS Circuitsijtsrd
Power consumption is one of the top issues of VLSI circuit design, for which CMOS is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area and thus, designers are required to choose appropriate techniques that satisfy application and product needs. In this paper we study different author’s paper to relate to this problem and try to find out the best solution for future work. Vidhyasagar Chaudhary | Dr. Neetesh Raghuwanshi "A Survey Paper on Leakage Power and Delay in CMOS Circuits" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-5 | Issue-4 , June 2021, URL: https://www.ijtsrd.compapers/ijtsrd43615.pdf Paper URL: https://www.ijtsrd.comengineering/electronics-and-communication-engineering/43615/a-survey-paper-on-leakage-power-and-delay-in-cmos-circuits/vidhyasagar-chaudhary
A verilog based simulation methodology for estimating statistical test for th...ijsrd.com
The low Power estimation is an important aspect in digital VLSI circuit design. The estimation includes a power dissipation of a circuit and hence this to be reduces. The power estimations are specific to a particular component of power. The process of optimization of circuits for low power, user should know the effects of design techniques on each component. There are different power dissipation methods for reduction in power component. In this paper, estimating the power like short circuit and the total power, power reduction technique and the application of different proposed technique has been presented here. Hence, it is necessary to provide the information about the effect on each of these components.
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A Literature Review On Design Strategies And Methodologies Of Low Power VLSI Circuits
1. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
Volume 4, Issue 2, Ver. IV (Mar-Apr. 2014), PP 17-21
e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197
www.iosrjournals.org
www.iosrjournals.org 17 | Page
A Literature Review on Design Strategies and Methodologies of
Low Power VLSI Circuits
Anuj1
, Divya Khanna2
1
(VLSI,Cetpa Infotech pvt. Ltd, Noida, India)
2
(Electronics and communication Department, Amity University,Noida, India)
Abstract: Low power came in to limelight in the current generation of electronic design. Earlier area and
performance and cost were the priority of design engineers overlooking power. However trade off
exist between area, performance and power. Overall performance of the circuit is affected by its
components. Optimization of the design is accomplished by compromising design issues and
components. With the shrinking technology below 90 nm power dissipation and its management has
been critical for designer .Importance for optimization has been drawn from extended battery life and
lowering package cost. This paper presents a literature review upon the strategies and methodologies
in designing low power VLSI circuits.
Keywords: VLSI circuits, Low power management, Low power strategies, power dissipation, Power
optimization.
I. Introduction
Digital circuits simplify transistor operation that allows devices to be conceived as switches. Advent of
Vacuum tube created a huge impact on electronics industry but had certain hindrances like high power and
hundreds of anode voltage. The invention of transistor was a revolutionary step in microelectronics industry
consuming few watts of power. This was the foundation stone for low power devices.The integration of
numerous functions into a single chip and improvement in the performance of the circuits has led to shrinkage
of feature size and resulted in the growth of power per unit area that in turn accompanied a requirement of heat
removal and cooling system. Low power is now a principal them in VLSI domain. Three most important factors
now days to be optimized are area, power and performance. In the past area, reliability, cost and performance
was given utmost importance and power reduction was negligible. Requirement for low power has been
increased with remarkable growth in battery powered, complex functional device like PC, wearable devices,
mobile phones, implantable medical instruments, multimedia portable devices that demand low power
consumption and high speed computation. High power system exacerbates numerous silicon failures due to
operation in high temperature.
Rise in 10o
C temperature component failure rate doubles. Some of the key design issues in the VLSI
industry are thermal and electrical limits determination, impact cost, size, weight, battery size, components, heat
sink and system packaging. Excessive power consumption is circumscribing factor in integrating more transistor
on a single chip. With lesser power dissipation, less amount of heat is produced in the room, lower is the
consumption of electricity and lesser requirement of heat removal equipment and thus impact on global
environment is trimmed helping in saving environment. Low power strategies are application specific. Goal of
micro powered, battery operated gadgets like cell phones, laptops is to increase the battery life, decreasing
weight and cutting off packaging cost. Plastic packaging is used for the circuits with power level of 1-2W. The
goal of battery powered, high performance system alike tablets and laptops is reduction in power dissipation to
half of total power consumption. For high performance, non battery operated devices achievement of reduced
power dissipation with the maintenance of reliability is an objective.
The paper is organized in the following manner. Section II explains major source of power dissipation.
Low power design space has been detailed in the section III. Section IV elaborates power minimization
techniques while section V and section VI explains CAD methodologies and power management strategies
respectively. The paper concludes in section VII.
II. Sources of Power dissipation
Power dissipation is the amount of power that is converted into heat and radiated away from the
electrical system. Measurement of power dissipation is in watts. Three major sources of power dissipation in
CMOS circuit are:
2. A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits
www.iosrjournals.org 18 | Page
i) Leakage current: It happens when input(s) and output(s) are stable i.e. not changing.
ii) Short circuit current: It occurs when N-MOS and P-MOS of a CMOS circuit conduct simultaneously
allowing current to flow directly from source to ground.
iii) Logic transitions: Nodes in a digital CMOS circuits oscillates between two logic levels („0‟ and „1‟) that
in turn charges and discharges the capacitance. This charging and discharging causes the Current to flow
from channel resistances of the transistor and phenomenon of power dissipation comes into the picture.
Leakage current fall under the category of static power dissipation while short circuit current and logic
transitions are categorized under dynamic power dissipation. Leakage current depends on fabrication technology
that includes reverse bias current and subthreshold current in parasitic diodes. The formation of the reverse bias
current takes place between drain, source and bulk region in MOS transistors while subthreshold current arises
from the inversion charge existing at gate voltage below threshold voltage. If feature size is 1 micrometer then a
diode leakage of 1 picoA takes places.
If a dc path is formed between supply rails and ground during input and output transition then short
circuit current takes places. Short circuit current is referred to as crow bar current. For an inverter gate, crow bar
current is proportional to gain of inverter gate, supply voltage cubic power, subthreshold voltage, operating
frequency and as well as on input rise/fall time. During logic transitions capacitive loads are charged and
discharged and thus causes power dissipation. In case of absence of load maximum short circuit current is
observed that decreases as load is increased.
Short circuit power consumption is less than 15% of dynamic power consumption if rise and fall time of input(s)
and output(s) are equivalent. Exploitation of appropriate circuit and device designing techniques can endeavor in
bogging down the short circuit and leakage current. However charging and discharging of load capacitance
dominates power consumption and is given by equation 1:
P = 0.5CVdd
2
E(sw) fclk (1)
Where C is the physical capacitance of the circuit, Vdd is the power supply, fclkis the clock frequency and E(sw)
is the switching activity that describes average number of transitions per 1/ fclk period. Total power is given in
the equation 2 as:
Ptotal = Pdynamic+ Pstatic + Pshortcircuit (2)
III. Low Power Design Space
Low power can be accomplished by reducing one of the following factors:
1. Voltage: One of the best method for reduction of power in the circuits. Voltage and power relationship
is described by following equation
P = V2
R
If V is reduced then power is also reduced. Now consider V as V then a power reduction of one
2
fourth is Observed. Its effect is globally on the circuit. Designers often sacrifice increased physical
capacitance and data activity for reduced voltage. Although this design space have few disadvantages
of lower speed and increased delay as Vdd approaches Vt.
2. Physical capacitance: Dynamic power dissipation is dependent on switching of physical capacitance.
Determination of physical capacitance is arduous task before routing and mapping. Thus with complete
information about placement, routing and mapping precision of estimation of capacitance is high. With
lesser logic, shorter wires and smaller devices capacitance can be curtailed. An important factor while
designing a circuit is interconnects capacitance. Interconnects affect chip area, power dissipation and
delay thus during design processing interconnects shall be estimated. Calculation of interconnect
capacitance is becomes easy after layout designing. Register sharing, extraction of common sub-
functions and information about placement and routing helps in reducing interconnect capacitance.
3. Logic transitions: Logic transitions or switching activity influences dynamic power dissipation. In the
absence of switching activity power dissipation is zero even on a chip having large number of
capacitance. Logic transitions determines switching that has two components namely fclkand E(sw). fclk
estimates the average period of data arrival while E(sw) determines number of transition each arrival
generate.
IV. Power Minimization technique
i) Reducing chip area and capacitances with techniques such as SOI (Silicon on insulator) with partially
or fully depleted wells or by scaling CMOS to submicron device size. It is an efficient technique but
financially too expensive.
3. A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits
www.iosrjournals.org 19 | Page
ii) Advanced interconnect substrates like multi chip module MCM. It is highly efficient technique but cost
heavily.
iii) Supply voltage scaling: It requires new fabrication technique and support circuits such as DC/DC
converters and level converters for operation low voltage environment. It is a cheap technique but handling
of signal to noise ratio is critical.
iv) Better design technique: Investment for the reduction of power by employing a better design technique
is small and has a very high potential.
v) Appropriate power management strategies.
V. CAD Methodologies
System Level
Circuit level design Logic synthesis
Physical design level
Figure1. Different CAD Methodologies
EDA tools bolster power savings during implementation. Four level of abstraction are logic synthesis level,
system level, physical design level and circuit level. This is achieved at above various level of abstraction.
3.1 System level :
At system level design, the hardware modules that are inactive is turned off automatically in order to
husband power. A designer can provide minimum supply voltages to modules and implant them with
level converters. Thus utilization of this technique will cycle back the energy to save power.
3.2 Logic synthesis:
This level of abstraction fits between register transfer level and netlist of gate specification. Various
techniques are employed for the transformation and optimization of RTL description depending upon
input target implementation, delay model and objective functions. After the system level, architectural
implementation and technological choices are made the switched capacitance of logic determines the
power consumption.
3.3 Physical design level:
It fits between netlist gate specification and layout that depends on target design technology, packaging
technology and objective functions. Numerous optimization technologies are used for partition, place,
resize and route gate. Under zero delay model switching activity of gate is constant during layout
optimization therefore to reduce the power decrease the load on high switching activity gate by
appropriate netlist portioning, gate placement, gate and wire resizing.
3.4 Circuit level design:
This utilizes adiabatic switching principle where speed is traded for low power. Other techniques that
are employed are based on self timed circuits and are based on partial transfer of energy stored on a
capacitance to a charge sharing capacitance. DC/DC level converters and energy efficient level
converters are required for circuit level design power reduction.
VI. Power Management strategies
Power management strategies play a key role in lowering the power dissipation in digital circuits. Some of
the strategies that are discussed in this paper for power reduction are multiple threshold voltage, clock
gating, multiple supply voltage, power gating, dynamic voltage scaling and substrate biasing.
6.1 Multiple threshold voltage:
Threshold voltage is an important factor in the reducing of power. This method assist in reducing both
dynamic and leakage power. Using different threshold voltage according to the mode of operation the goal is
4. A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits
www.iosrjournals.org 20 | Page
easily achieved. For leakage power reduction implantation of high threshold voltage is useful. During active
mode of operation low threshold voltage is employed for accomplishing low power with high performance. As
threshold voltage increases, subthreshold current starts coming down with an increase in propagation delay of
the gate. Thus leading to little penalties on speed and area. This is a very useful strategy for reduction of
glitches power.
6.2 Multiple supply voltage:
In this technology lower supply voltages and high supply voltage are implanted according to the modes
of operation. Non critical path are employed with low supply voltage and higher supply voltage is used for
critical paths. Higher supply voltage with critical path helps in attaining performance while lower supply voltage
in non critical path helps in accomplishing lower power dissipation. Each tier in a chip is parted into many grids.
In these grids higher and lower voltages are fabricated depending upon operational mode. Multiple supply
voltage is used in digital signal processors. It helps in achieving latency constraints in critical path. Some of the
disadvantages with it are isolation requirement, little increment in the area and difficulty in testing.
6.3 Power gating:
In power gating methodology a sleep transistor is introduced between actual ground and virtual ground
when device is turned off in sleep mode in order to cut off leakage path. This technique cut short leakage power
without impacting performance. Two types of power gating techniques are fine graining and coarse graining.
Design architecture is more than clock gating technique. The disadvantage of this strategy is increased area and
delay. Better power efficiency is an advantage of this technique.
6.4 Body biasing:
Body biasing decreases power dissipation by enhancing threshold voltage of individual transistor
thereby curtailing leakage current. Two most commonly used techniques are Swapped body biasing (SBB) and
dynamic threshold voltage MOS biasing scheme. In SBB propagation delay is short. This technique tends to
propose slight penalty on delay and area. RFID, biomedical devices and sensor networks are some example
where body biasing is employed.
6.5 Dynamic voltage and frequency scaling:
Most commonly used power management strategy. In this technique clock frequency is reduced
causing a reduction in supply voltage. It has the ability to reduce power consumption of CMOS IC like modern
computers and laptops.
P= cfv2
+ Pstatic (3)
Voltage required depends upon the frequency at which it is clocked and thus if frequency is trimmed then
voltage can be reduced. By this technique 34% of power is saved. The reduction in frequency increases speed,
thus a biggest advantage of this technique. It also offers high performance. It is employed for microprocessors,
multimedia interface system and battery powered electronic devices.
6.6 Clock gating:
This technique reduces clock signal resulting in switching power reduction of flip flop. As feature size
had shrink clock frequency of IC has increased thus power consumption takes place. Power dissipation is
highest due to clock net as it has higher switching activity. In clock gating technique clock is stopped in parts of
the circuits. Clock gating occupies large chip area. Some clock gating techniques are AND gate. NOR gate,
Latched AND and latched NOR clock gating.
Table 1. Showing comparison between various power management techniques
S.no Power Management techniques
Power reduction technique Power saving Delay
Penalty
Area
1 Multiple Threshold voltage Medium Little Medium
2 Multiple supply voltage High Medium Medium
3 Power gating High Small Little
4 Body biasing Medium Small Little
5 Dynamic voltage and frequency scaling High Small Medium
6 Clock gating High Medium Large
5. A Literature Review on Design Strategies and Methodologies of Low Power VLSI Circuits
www.iosrjournals.org 21 | Page
VII. Conclusion
In this paper various strategies and methodologies for reduction in power has been discussed. This
paper has successfully reviewed the CAD methods for power optimization keeping pace with area, delay and
performance. This works elaborated the need for low power VLSI circuits and suggested various design
techniques currently in practice in microelectronics industry. This paper will help the designers to understand
the basics of low power. The major design issues were briefly explained and presented for better clarity to
anyone looking to grasp good knowledge about the subject.
Acknowledgment
First author Anuj expresses deep sense of gratitude towards his late grandparents for the shower of
blessings. He would take this opportunity to kind heartedly thanks his Mother and Father Mrs Neeta and Mr
Avinash Chander for their continuous encouragement and help. Further he is thankful to his Sister Swati
Misra and brother- in-law Ashish Misra for being such a great support to him. Without these people
accomplishment of this paper would have been a dream.
Second author Divya Khanna extends gratitude to her grandmother, Smt. Sarla Khanna, Father, Shri
Ramesh Khanna, Mother Mrs. Vandana Khanna and brother Amit Khanna who never ceased in helping
until the paper was structured.
References
Journal Papers:
[1] Zamin Ali Khana ,S. M. AqilBurneyb, , Jawed Naseemc, KashifRizwand, “Optimization of Power Consumption in VLSI Circuit”
IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 2, March 2011
[2] KanikaKaur, Arti Noor, “STRATEGIES & METHODOLOGIES FOR LOW POWER VLSI DESIGNS: A REVIEW” ,International
Journal of Advances in Engineering & Technology, May 2011.
[3] Dr. Neelam R, Prakash, Akash, “Clock Gating for Dynamic Power Reduction in Synchronous Circuits” ,International Journal of
Engineering Trends and Technology (IJETT) – Volume4Issue5- May 2013.
[4] BagadiMadhavi, G Kanchana, VenkateshSeerapu, “Low Power and Area Efficient Design of VLSI Circuits” ,International Journal
of Scientific and Research Publications, Volume 3, Issue 4, April 2013
[5] Sherif A. Tawfik and VolkanKursun,“Low Power and High Speed Multi Threshold Voltage Interface Circuits”,IEEE
TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
[6] Shih-An Yu Pei-Yu Huang Yu-Min Lee, “A Multiple Supply Voltage Based Power Reduction Method in 3-D Ics Considering
Process Variations and Thermal Effects”
[7] Velicheti Swetha1, S Rajeswari, “Design and Power Optimization of MT- CMOS circuits using Power Gating Techniques”,
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering (An ISO 3297: 2007
Certified Organization) Vol. 2, Issue 8, August 2013
[8] JabulaniNyathi, Brent Bero and Ryan McKinlay, “A Tunable Body Biasing Scheme for Ultra-Low Power and High Speed CMOS
Designs”
[9] Manoj Kumar 1, Sandeep K. Arya 2, and Sujata Pandey , “Low power CMOS full adder design with body biasing approach”,
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Books:
[11] Kaushik Roy, Sharat C. Prasad, “Low power CMOS VLSI circuit design” (Wiley India pvt. Ltd., 2013)
Authors Profile
Anuj received degree of B.Tech(Electronics and communication) from Maharishi Dayanand
University in the year 2013. He is enthusiastic to work in the field of VLSI. His area of interest
includes digital system design using CAD tools and Low power VLSI domain in addition to
analog and mixed signal circuit design. He is also interested in Circuit design in presence of
device variability and design of adaptive VLSI circuits.
Divya Khanna received degree of B.Tech(Electronics and communication) from Uttar Pradesh
technical university in 2012.Currently she is pursuing M.Tech from Amity University, Noida,
India. Her interest areas are Electronic Design Automation (EDA) of digital and analog circuits,
as well as VLSI design. Apart from that low power, reliability, testing, simulation, design for
manufacturability, hardware/software co-design, application specific integrated circuits (ASICs),
and System-on-Silicon (SOC) areas also attracts her.