The document discusses intellectual property (IP) cores and embedded systems-II course content. Section A introduces IP cores and real-time operating systems (RTOS). Section B covers RTOS services like threads, scheduling, and communication. The course also includes ARM and AVR microcontrollers. Examples of IP cores provided are SDRAM controllers, UARTs, LCD controllers, and Nios II processors. Interfaces like Avalon are used to connect IP cores in a system on chip design.

1. Embedded Systems-II – IP Cores
Prof. Anish Goel

2. Contents of ES-II course
Section A
 Introduction to Intellectual Property (IP) Circuits or Cores,
Core examples. Peripherals interfacing with IP Cores. Core
based SOC design. Concept and Fundamentals of RTOS
essential features, ROS Kernel Function, RTOS examples Lynox,
QNX, Neutrino,VRTX, Vx Works.
Section B
 OS services. Operating Modes. Threads, Context Switching
overheads, Scalability, Embedding with application code.Task
Scheduling, Interrupt handling, Inter task communication.
Comparison and application of various RTOS.
2 IP Cores Prof. Anish Goel

3. Elective Courses offered in this Semester…
 Low power VSLI design.
 Video lectures, Seminar’s and Discussion on power reduction
techniques, Short channel effects and SRAM design.
 Advanced Computer Architecture.
 Embedded Systems –II
 Everything in the course, ARM Microcontroller, AVR
microcontroller and NIOS-2 and softcores.
3 IP Cores Prof. Anish Goel

4. IP CORES
 An IP (intellectual property) core is a block of logic or
data that is implemented in a field programmable gate
array ( FPGA ) or application-specific integrated circuit (
ASIC ) for a product.
 Universal Asynchronous Receiver/Transmitter ( UART s),
central processing units ( CPU s), Ethernet controllers,
and PCI interfaces are all examples of IP cores
 IP cores fall into one of three categories: hard cores , firm
cores , or soft cores
4 IP Cores Prof. Anish Goel

5. IP CORE OVERVIEW
Types of IP Cores and main deliverables
 Soft IP Cores
synthesisable VHDL or Verilog (54 % of IPs)
 Firm IP Cores
netlist after synthesis in the target technology (20
% of IPs)
 Hard IP Cores
layout of the block on chip (GDSII, CIF) (26 % of
IPs)
5 IP Cores Prof. Anish Goel

6. Types of IP Cores…
6 IP Cores Prof. Anish Goel

7. Flexibility and performance
7 IP Cores Prof. Anish Goel

8. System IP
8 IP Cores Prof. Anish Goel

9. Altera IP Cores
 Embedded Peripherals IP
 ■ SDRAM Controller Core
 ■ CompactFlash Core
 ■ Common Flash Interface Controller Core
 ■ EPCS Serial Flash Controller Core
 ■ JTAG UART Core
 ■ UART Core
 ■ SPI Core
 ■ Optrex 16207 LCD Controller Core
 ■ PIO Core
 ■ Avalon-ST Serial Peripheral Interface Core
 ■ PCI Lite Core
 ■ Cyclone III Remote Update Controller Core
 ■ MDIO Core
9 IP Cores Prof. Anish Goel

10. SDRAM Controller Interface Block
Diagram
10 IP Cores Prof. Anish Goel

11. SDRAM interface
 The SDRAM controller core provides Memory-Mapped
interface to off-chip SDRAM.
 The SDRAM controller allows designers to create
custom systems in an Altera device that connect easily to
SDRAM chips.
 The SDRAM controller supports standard SDRAM.
 The SDRAM controller connects to one or more
SDRAM chips, and handles all SDRAM protocol
requirements.
 The core can access SDRAM subsystems with various
data widths (8, 16, 32, or 64 bits), various memory sizes,
and multiple chip selects
11 IP Cores Prof. Anish Goel

12. Example Configurations
Single 128-Mbit SDRAM Chip with 32-Bit Data
12 IP Cores Prof. Anish Goel

13. Example Configurations
Two 64-MBit SDRAM Chips Each with 16-Bit Data
13 IP Cores Prof. Anish Goel

14. UART Core
14 IP Cores Prof. Anish Goel

15. RS-232 Interface
 The UART core implements RS-232 asynchronous transmit
and receive logic.
 The UART core sends and receives serial data via the TXD
and RXD ports. The I/O buffers on most Altera FPGA families
do not comply with RS-232 voltage levels, and may be damaged
if driven directly by signals from an RS-232 connector.
 To comply with RS-232 voltage signaling specifications, an
external level-shifting buffer is required (for example, Maxim
MAX3237) between the FPGA I/O pins and the external RS-
232 connector.
 The UART core uses a logic 0 for mark, and a logic 1 for space.
 An inverter inside the FPGA can be used to reverse the
polarity of any of the RS-232 signals, if necessary.
15 IP Cores Prof. Anish Goel

16. Optrex 16207 LCD Controller Core
16 IP Cores Prof. Anish Goel

17. LCD interface
 The Optrex 16207 LCD controller core provides the
hardware interface and software driver required for a
Nios II processor to display characters on 6×2-character
LCD panel
 Eleven signals that connect to pins on the Optrex 16207
LCD panel—These signals are defined in the Optrex
16207 data sheet.
■ E—Enable (output)
■ RS—Register Select (output)
■ R/W—Read or Write (output)
■ DB0 through DB7—Data Bus (bidirectional)
17 IP Cores Prof. Anish Goel

18. Altera Avalon Interface Specifications
 Avalon® interfaces simplify system design by allowing you
to easily connect components in an FPGA.
 The Avalon interface family defines interfaces for use in
both high-speed streaming and memory-mapped
applications.
 These standard interfaces are designed into the
components available in the SOPC Builder and the
MegaWizard® Plug-In Manager.
18 IP Cores Prof. Anish Goel

19. Avalon Interfaces in a System Design
19 IP Cores Prof. Anish Goel

20. Nios II Processor System
20 IP Cores Prof. Anish Goel

21. Nios II Processor Core Block Diagram
21 IP Cores Prof. Anish Goel

22. References…
 Altera Embedded Peripherals IP User Guide
 Nios II Hardware Development Tutorial
 Nios II Software Developer’s Handbook
 Nios II Processor Reference Handbook
 Avalon Interface Specifications
22 IP Cores Prof. Anish Goel