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Nios2 and ip core
1. Introduction to IP cores and softcore
processors
Prof. Anish Goel
IP Cores and Softcore Processors
Prof. Anish Goel
2. IP core (intellectual property core)
An IP (intellectual property) core is a block of logic or data that is used in making a
field programmable gate array ( FPGA ) or application-specific integrated circuit
( ASIC ) for a product.
As essential elements of design reuse , IP cores are part of the growing electronic
design automation ( EDA ) industry trend towards repeated use of previously
designed components.
Universal Asynchronous Receiver/Transmitter ( UART s), central processing units
( CPU s), Ethernet controllers, andPCI interfaces are all examples of IP cores.
IP cores fall into one of three categories: hard cores , firm cores , or soft cores .
Hard cores are physical manifestations of the IP design. These are best for plug-and-play
applications, and are less portable and flexible than the other two types of
cores.
Like the hard cores, firm (sometimes called semi-hard ) cores also carry placement
data but are configurable to various applications.
The most flexible of the three, soft cores exist either as a netlist (a list of the logic
gate s and associated interconnections making up an integrated circuit ) or hardware
description language ( HDL ) code.
IP Cores and Softcore Processors
Prof. Anish Goel
3. IP cores
Soft IP cores
Hard IP cores ROM, RAM, FIFO
RISC CPU
DSP – Multiplier
Flash memory (boot, user)
PCI, PCIe
JTAG
IP Cores and Softcore Processors
Prof. Anish Goel
4. Typical soft IP cores
PCI master-target, 32/64 bit, PCIe
Ethernet, UART
μP, μC (incl. old ones), RISC CPUs
Interface to DRAM, SSRAM
DSP: CORDIC, DDS, FFT, Filters
VME, USB, CAN, I2C, SPI, SD card
encryption / decryption
IP Cores and Softcore Processors
Prof. Anish Goel
5. Nios Soft Core Embedded Processor
IP Cores and Softcore Processors
Prof. Anish Goel
6. NIOS II Overview
Soft IP Core
A soft-core processor is a microprocessor fully described in
software, usually in an HDL, which can be synthesized in programmable
hardware, such as FPGAs.
Reduced Instruction Set Computer (RISC)
No pipeline, 5 or 6 stages pipeline configurations
Full 32-bit instruction set, data path, and address space
32 general-purpose registers
32 external interrupt sources
Access to a variety of on-chip peripherals, and interfaces to
off-chip memories and peripherals
Software development environment based on the GNU
C/C++ tool chain and Eclipse IDE
IP Cores and Softcore Processors
Prof. Anish Goel
8. Nios Embedded Processor Core
Configurable Soft Core Processor
32-Bit Pipelined RISC Architecture
– 16-Bit Instructions
– Most Instructions Take 1 Clock
Large Internal Register File
Configurable Data Path
– 16-bit (1100 LEs)
– 32-bit (1700 LEs)
Dynamic Bus Sizing
30 to 80 MIPS Performance
IP Cores and Softcore Processors
Prof. Anish Goel
9. Nios RISC Processor Block Diagram
Standard RISC Components
Fully-Synchronous Interface
IP Cores and Softcore Processors
Prof. Anish Goel
10. NIOS II Processor Core
IP Cores and Softcore Processors
Prof. Anish Goel
11. Implementation
The functional units of the Nios II architecture form the
foundation for the Nios II instruction set.
The Nios II architecture describes an instruction set, not
a particular hardware implementation.
Trade-offs:
– More or less of a feature - amount of instruction cache memory.
– Inclusion or exclusion of a feature - the JTAG debug module.
– Hardware implementation or software emulation - divider
IP Cores and Softcore Processors
Prof. Anish Goel
12. Pipelining
Static branch prediction is implemented using the branch
offset direction;
– a negative offset is predicted as taken
– a positive offset is predicted as not-taken
IP Cores and Softcore Processors
Prof. Anish Goel
13. UART Peripheral
Provides common serial interface with variable baud rate,
parity, stop and data bits, and optional flow control signals
IP Cores and Softcore Processors
Prof. Anish Goel
14. Timer Peripheral
32-bit and 64-bit counters.
Controls to start, stop, and reset the timer.
Two count modes: count down once and continuous count-down.
Count-down period register.
Option to enable or disable the interrupt request (IRQ) when
timer reaches zero.
Optional watchdog timer feature that resets the system if
timer ever reaches zero.
Optional periodic pulse generator feature that outputs a pulse
when timer reaches zero.
Compatible with 32-bit and 16-bit processors
IP Cores and Softcore Processors
Prof. Anish Goel
15. PIO Peripheral
1 to 32-bit Parallel I/O Port
Input Only
Output Only
Bi-directional Port
• On-chip: Separate Ports for Input & Output
• Off-chip: Tri-State Control
Edge Detection on Inputs
Interrupt Generation
– Maskable
– IRQ Source
• Input Level
• Edge Detection Register
IP Cores and Softcore Processors
Prof. Anish Goel
16. Serial Peripheral Interface (SPI)
Full Duplex, Synchronous Serial Interface
– Interface to:
• A/D, D/A
• Microcontrollers
• Serial EPROM
3-Wire Serial Communications Bus With Slave Select
– Master Out Slave In - MOSI
– Master In Slave Out - MISO
– SPI Clock - SCLK
– Slave Select - SS_n (Optional)
Master or Slave Operation
Supports Up to 16 Slave Devices
Programmable Word Size (1 to 16 bits)
Programmable Delay Slot (Enable-to-Active)
IP Cores and Softcore Processors
Prof. Anish Goel
17. Ethernet Interface
10/100-Mbps SMSC LAN91C111single-chip Ethernet
controller interface
Software support provided by the NicheStack TCP/IP
Stack - Nios II Edition
Included with the Nios II development kits
IP Cores and Softcore Processors
Prof. Anish Goel
18. Memory Interfaces
On-chip ROM and RAM
SDRAM
SSRAM
SRAM
Flash
Common Flash Interface Controller Core
Altera serial configuration devices
IP Cores and Softcore Processors
Prof. Anish Goel
