Yunn Chyi Chen has over 15 years of experience in hardware design and verification. She has a Master's degree in Electrical Engineering and has designed and verified 7 chips that have gone into mass production. She is proficient in Verilog, C++, and other languages and tools used in chip design. She is currently seeking a senior hardware design engineer position and has experience working as a contractor and at various semiconductor companies.

1. Yunn Chyi Chen (Aphrodite Chen)
1610 NW 23RD ST, Corvallis, OR 97330
mailto: eunicefalcon.chen@gmail.com
503 968 9209 (H)
OBJECTIVE
Apply Senior Hardware Design Engineer
EDUCATION
 Master of Electrical Engineering, Taiwan National Tsing Hua University.
 Bachelor of System and Science Engineering, Taiwan National Tsing Hua University.
 Portland Community College computer science program.
SUMMARY
 Solid Verilog RTL design experience -Completed 7 chips from design through verification and tape
out; 3 chips in mass production; also wrote many small scale Verilog modules and test benches.
 Hands-on experience from front-end architecture definition through back-end production,
testing for mass volume products. Including FPGA board emulation (Xilinx ISE), all ASIC
debugging and verification, demo boards and mass production and ASICs ECO and FIB.
 Experience in using embedded up6502, up8051, and ADSP-2181 processors IP in chips design.
 Excellent Team-player with project management experience in a multi-disciplinary environment.
 Awarded four U.S. and Taiwan patents.
 U.S. Permanent Resident
SKILL
 Verilog, C++, Keil, Java, Spice, Debussy, DC, SVN, Perl, Bash, Linux.
EXPERIENCE and TRAINING
Contractor, ATTOPSEMI (2015, Dec ~present)
 Various OTPs design kits
Provide OTP Verilog behavior, test bench and .lib files.
http://www.attopsemi.com/
PCC Computer Science course (2015)
 Taking C++, Linux installation and configuration, Data structure, System Programing (include
Java) lessons – one year solid C++ training.
Contractor Digital IC Designer, Singular Technology Co.(2010~)
 Triple DES and microprocessor8051 peripherals for Magnetic card reader
Coding Triple DES (Triple Data Encryption Standard), some peripherals of uP8051 core IP and integrating
analog IPs for Magnetic card reader chip. Major work covers Verilog coding, test bench setting up by Verilog
and Perl, gate synthesis by Design compiler, FPGA verification and integrating and tape-out.
http://www.singular.com.tw/
Digital IC Designer, TSMC (2008 – 2009)
 RFID TAG Chip

2. 2
Implemented the physical and link layer protocols for an ultra low power C1GEN2 RFID TAG chip with
elaborate clock and queue management in Verilog; built up the simulation test bench for verifications by
Verilog, Perl and Bash; execute FPGA emulation and test chip verification based on Global Unichip ESL
system which is with ARM and Altera FPGA working via PCI-E bus Development platform on Linux.
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.466.4253&rep=rep1&type=pdf
 RFID TAG chip verification and RFID TAG chip product testing
Initialize RFID reader system, which using AS3990 UHF reader chip and Silicon Labs C8051F340, to test
RFID TAG. Propose cost effective dies sorting method by implement simple extra circuits on chip.
Staff IC Design Engineer, UWave Technology (2003 – 2007)
 27 MHz Wireless Mouse Transmitter Chip
27 MHz transmitter chip was for wireless mouse applications, with special emphases on high reliability and
power efficiency. The chip was embedded with RF, PLL, DC-DC analog blocks, and power management,
up6502. Work covers coding power management, some peripherals of up6502 core, test bench, synthesis,
integrating analog parts and running analog and digital Cosim of power related parts, tape out.
 2.4GHz Wireless Audio Baseband
A baseband chip embedded a DSP processor ADSP-2181 core IP, audio ADC, DAC works with external Atmel
ATR2406 or ELANsat 2.4GHz RF to fulfill low compression distortion, low delay wireless speaker/earphone.
Work covers coding I2S, SPI, EEPROM interface, RF interface, frame encoding/decoding, up interface, clocks
arrangement…, integrating ADSP-2181 and analog parts; also covers FPGA emulation, ECO and mass
production testing.
 Baseband chip for 2.4GHz wireless PS2 game pad
2.4GHz baseband chip is to associate with nRF2401 for the Sony PS2 Station wireless game pad. Work
covers framer/de-framer, scrambler/descrambler and DSSS (direct sequence spread spectrum) modulation/
demodulation coding in Verilog and FPGA synthesis in Synplify and Xilinx XST. Working area also included
FPGA emulation debug in logic analyzer, scope and spectrum analyzer.
Digital IC designer, Macronix International (1999 - 2002)
 802.3ab 1000-T transceiver baseband design.
Work area includes scrambler, encoding and Transmitter filter and receiver feed forward equalization and
decision feedback equalizer Matlab and C simulation.
 10MHz/100 MHz L2 Ethernet Switch Chips
Responsible for the architecture define and implementation of a 4-port and 24-port L2 Ethernet 10/100M
Switch chips, including the MAC, routing table, buffer management, and memory with BIST coding in
Verilog. Building test bench in Verilog and Makefile; gate Synthesis in Design compiler, STA in Prime time;
also included pre-APR blocks placement, ECO and FIB, testing and mass production. The 24-port
MX98224EC Ethernet Switch chip gained wide market acceptance due to its small size and low cost.
http://www.hoovers.com/company-information/cs/company-
profile.MACRONIX_INTERNATIONAL_CO_LTD.aff92177c6397e56.html
Hardware(PCB board)/ASIC designer, Accton Tech
 16 ports and dual ports L2 Ethernet switch chips design
Design fabric chip of 16 ports L2 Ethernet switch chipsets; design shared memory architecture dual port L2
Ethernet Switch chip, and was in charge of verification and mass production.
 Multi-interface intelligent/Dumb Ethernet Hub/switch product and mass production
Design PCB schematic and was in charge of product mass production.

3. 3
PATENT
http://www.patentbuddy.com/Inventor/Chen-Aphrodite/1122105#More
 Method and apparatus for dynamically hiding a defect in an embedded memory. US Patent No. 6836438 B2
December, 2004
https://www.google.co.ve/patents/US6836438?dq=US+Patent+No.+6836438+B2&hl=zh-TW&sa=X&ved=0ahUKEwi-s8H-
sY3MAhUC12MKHfWfBaEQ6AEIGzAA
 Multiple ports Ethernet Switch chip and daisy chain test for multiple ports Ethernet Switch chip. US Patent
No. 20040015616 A1 January, 2004
https://www.google.co.ve/patents/US20040015616?dq=US+Patent+No.+20040015616+A1&hl=zh-
TW&sa=X&ved=0ahUKEwjUyIGuso3MAhUNy2MKHSx2DLQQ6AEIGzAA
 Method for adjusting inter-frame gap in ratio US Patent No. 6118793A September, 2000(P)
https://www.google.co.ve/patents/US6118793?dq=US+Patent+No.+6118793A&hl=zh-
TW&sa=X&ved=0ahUKEwidgLPWso3MAhUH1mMKHZdoCdMQ6AEIGzAA
 Slot control system with fixed sequence and dynamic slot effect utilizing slot processor for continuously
detecting operation request signal and immediately allowing next port or block operation when no
operation request signal. US Patent No. 6115758 September, 2000
https://www.google.co.ve/patents/US6115758?dq=US+Patent+No.+6115758+September&hl=zh-
TW&sa=X&ved=0ahUKEwi_qeb9so3MAhVU12MKHeOxB1wQ6AEIGzAA