ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
Design of LDPC Decoder Based On FPGA in Digital Image Watermarking TechnologyTELKOMNIKA JOURNAL
LDPC code and digital image watermarking technology, which is an effective method of digital copyright protection and information security, has been widely used. But this is a multi-disciplinary, multi technology application scheme. In order to realize FPGA design of LDPC decoder in the application scheme, an effective implementation method of digital watermarking application system must be found. In this paper, MATLAB software and Qt development environment are combined to achieve the digital watermarking application software design. It could get real-time input data for the LDPC decoder. Then the hardware of the LDPC decoder is primarily implemented by FPGA in the digital image watermarking system. And the serial port is used to make the output data of the decoder back to computer for verification. Through the simulation results, the Modelsim time simulation diagram is given, and the watermark image compared with the original image is got. The results show that the resource usage of our system is few, and the decoding rate is fast. It has a certain practical value.
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
Implementation of Soft-core processor on FPGA (Final Presentation)Deepak Kumar
Implementation of Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
"ZYNQ-7000 High Performance Electric Drive and Silicon Carbide Multilevel inverter with Scilab Hardware-in-the-loop"
By Giulio Corradi, Xilinx for ScilabTEC 2015
The Microarchitecure Of FPGA Based Soft ProcessorDeepak Tomar
this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and
J Gregory Steffan
Dept. of Electrical and Computer Engineering
University of Toronto
FPGA introduction for absolute beginners
- What is inside FPGA (Altera example)
- What are the major differences between firmware development for MCU and FPGA
- Some very basics of Verilog HDL language (by similarities with C/C++)
- Testbench approach and Icarus simulator demonstration
- Altera Quartus IDE demonstration -- creating project, compilation, and download
- Signal-Tap internal logic analyzer demonstration
(Verilog source code examples attached inside presentation)
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
An Automatic Generation of NoC Architectures: An Application-Mapping ApproachMostafa Khamis
Designing a combined hardware-software NoC emulation framework, which could be used as a powerful design infrastructure for enabling emulation and functional verification of several NoC architectures at different levels of abstraction for MPSoCs.
Newly developing 2D and 3D NoC-based router architectures to provide different network performance analysis that could evaluate and validate the proposed framework
Developing portable CNI to control and monitor the packets traffic between the PE and the connected router
Improving and Implementing a generic UVM environment that could be supported for all proposed different NoC platforms for network’ congestion-aware bus failure routing detection, and network performance analysis.
Implementing a logical modular for emulation flow, allowing the framework to auto-generate the hardware, the corresponding UVM verification environments, compile, emulate, and evaluate the whole MPSoC system.
Providing a lot of performance analyses for all different 2D and 3D router architectures with different network parameters and configurations under real traffic patterns injected by RISC-V PE that connected though a newly developed portable CNI.
A review of the history of digital design throughout the years until the era of programmable logic, and a detailed exploration of the architecture of FPGA chips, followed by an introduction to SoC FPGAs and some of their benefits.
Implementation of Soft-core processor on FPGA (Final Presentation)Deepak Kumar
Implementation of Soft-core processor(PicoBlaze) on FPGA using Xilinx.
Establishing communication between two PicoBlaze processors.
Creating an application using the multi-core processor.
"ZYNQ-7000 High Performance Electric Drive and Silicon Carbide Multilevel inverter with Scilab Hardware-in-the-loop"
By Giulio Corradi, Xilinx for ScilabTEC 2015
The Microarchitecure Of FPGA Based Soft ProcessorDeepak Tomar
this presentation is on the Paper "The Microarchitecure Of FPGA Based Soft Processor" by Peter Yiannacouras, Jonathan Rose and
J Gregory Steffan
Dept. of Electrical and Computer Engineering
University of Toronto
FPGA introduction for absolute beginners
- What is inside FPGA (Altera example)
- What are the major differences between firmware development for MCU and FPGA
- Some very basics of Verilog HDL language (by similarities with C/C++)
- Testbench approach and Icarus simulator demonstration
- Altera Quartus IDE demonstration -- creating project, compilation, and download
- Signal-Tap internal logic analyzer demonstration
(Verilog source code examples attached inside presentation)
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
An Automatic Generation of NoC Architectures: An Application-Mapping ApproachMostafa Khamis
Designing a combined hardware-software NoC emulation framework, which could be used as a powerful design infrastructure for enabling emulation and functional verification of several NoC architectures at different levels of abstraction for MPSoCs.
Newly developing 2D and 3D NoC-based router architectures to provide different network performance analysis that could evaluate and validate the proposed framework
Developing portable CNI to control and monitor the packets traffic between the PE and the connected router
Improving and Implementing a generic UVM environment that could be supported for all proposed different NoC platforms for network’ congestion-aware bus failure routing detection, and network performance analysis.
Implementing a logical modular for emulation flow, allowing the framework to auto-generate the hardware, the corresponding UVM verification environments, compile, emulate, and evaluate the whole MPSoC system.
Providing a lot of performance analyses for all different 2D and 3D router architectures with different network parameters and configurations under real traffic patterns injected by RISC-V PE that connected though a newly developed portable CNI.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
International Journal of Computational Engineering Research(IJCER) ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
The Field Programmable Gate Array (FPGA) industry is expanding both in market share and in innovation. The tailored FPGA features make them a better choice to include FPGA in an increasing number of applications in the upcoming years. A constant development of FPGA technology has led to minimize the gap of performance levels between FPGA and Application Specific Integrated Circuit (ASIC). Hence, in recent years, FPGA based platforms are proven more attractive than ASICs since their performance is high in addition to the low cost of the development process and short time to market. Therefore, nowadays, FPGA is highly attractive for a huge range of applications in communications, computing, avionics, security, automotive and consumer electronics. Field Programmable Gate Array industry has shown a steady growth with a market prediction value of USD 9 billion by 2023. Currently, the FPGA companies started growing in reserch areas such as Artifitial Intelligence (AI), Internet of Thing (IoT) and LIght Detection and Ranging (LIDAR). The aim of this paper is to review the developments in FPGA.
In this paper, proposed a novel implementation of a Soft-Core system using
micro-blaze processor with virtex-5 FPGA. Till now Hard-Core processors are used in
FPGA processor cores. Hard cores are a fixed gate-level IP functions within the FPGA
fabrics. Now the proposed processor is Soft-Core Processor, this is a microprocessor fully
described in software, usually in an HDL. This can be implemented by using EDK tool. In
this paper, developed a system which is having a micro-blaze processor is the combination
of both hardware & Software. By using this system, user can control and communicate all
the peripherals which are in the supported board by using Xilinx platform to develop an
embedded system. Implementing of Soft-Core process system with different peripherals like
UART interface, SPA flash interface, SRAM interface has to be designed using Xilinx
Embedded Development Kit (EDK) tools.
A PIC compatible RISC CPU core Implementation for FPGA based Configurable SOC...IDES Editor
Modern embedded systems are built around the soft
core processors implemented on FPGA. The FPGAs being
capable of implementing custom hardware blocks giving the
advantage of ASICs, and allowing the implementation of
processor platform are resulting in powerful Configurablesystem
on chip(C-SoC)platforms. The Microchip’s PIC
microcontroller is very widely used microcontroller
architecture across various embedded systems. The
implementation of such core on FPGA is very much useful in
CSOC based embedded systems. This type of designs can be
widely used in those controlling fields demanding low power
consumption and high ratio of performance to price. In this
project a reduced instruction set computer (RISC) CPU IP
core whose instructions are compatible with the Microchip
PIC16C6Xseries of microcontrollers is implemented in VHDL.
The core is based on 8-bit RISC architecture and top-Down
design methodology is used in developing the core. The RISC
CPU core is based on Harvard architecture with 14-bit
instruction length and 8-bit data length and two-stage
instruction pipeline. The architecture will be designed aiming
at single cycle execution of the instructions, except those
related to program branches. Since this type of CPU based on
RISC architecture, there are only 35 reduced instructions in
its instruction set, which are easy to be learned and used. The
performance of the 8-bit RISC CPU is better than those of
CPUs which are based on CISC architecture. Modelsim Xilinx
Edition (MXE) will be used simulation and functional
verification. The Xilinx Spartan-3E FPGAs will be used
synthesis and timing analysis. The results will be verified on
chip with chipscope tool.
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
Programmable logic controller performance enhancement by field programmable g...ISA Interchange
PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx’s Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.
THE PRESSURE SIGNAL CALIBRATION TECHNOLOGY OF THE COMPREHENSIVE TEST SYSTEMieijjournal
The pressure signal calibration technology of the comprehensive test system which involved pressure
sensors was studied in this paper. The melioration of pressure signal calibration methods was elaborated.
Compared with the calibration methods in the lab and after analyzing the relevant problems,the
calibration technology online was achieved. The test datum and reasons of measuring error analyzed,the
uncertainty evaluation was given and then this calibration method was proved to be feasible and accurate.
8 th International Conference on Education (EDU 2023)ieijjournal
8th International Conference on Education (EDU 2023) will provide an excellent
international forum for sharing knowledge and results in theory, methodology and
applications impacts and challenges of education. The conference documents practical and
theoretical results which make a fundamental contribution for the development of
Educational research. The goal of this conference is to bring together researchers and
practitioners from academia and industry to focus on Educational advancements and
establishing new collaborations in these areas. Original research papers, state-of-the-art
reviews are invited for publication in all areas of Education
Informatics Engineering, an International Journal (IEIJ)ieijjournal
Informatics is a rapidly developing the field. The study of informatics involves human-computer
interaction and how an interface can be built to maximize user efficiency. Due to the growth in IT,
individuals and organizations increasingly process information digitally. This has led to the study of
informatics to solve privacy, security, healthcare, education, poverty, and challenges in our environment.
The Informatics Engineering, an International Journal (IEIJ) is an open access peer-reviewed journal that
publishes articles which contribute new results in all areas of Informatics. The goal of this journal is to
bring together researchers and practitioners from academia and industry to focus on the human use of
computing fields such as communication, mathematics, multimedia, and human-computer interaction
design and establishing new collaborations in these areas.
Big data is a prominent term which characterizes the improvement and availability of data in all three
formats like structure, unstructured and semi formats. Structure data is located in a fixed field of a record
or file and it is present in the relational data bases and spreadsheets whereas an unstructured data file
includes text and multimedia contents. The primary objective of this big data concept is to describe the
extreme volume of data sets i.e. both structured and unstructured. It is further defined with three “V”
dimensions namely Volume, Velocity and Variety, and two more “V” also added i.e. Value and Veracity.
Volume denotes the size of data, Velocity depends upon the speed of the data processing, Variety is
described with the types of the data, Value which derives the business value and Veracity describes about
the quality of the data and data understandability. Nowadays, big data has become unique and preferred
research areas in the field of computer science. Many open research problems are available in big data
and good solutions also been proposed by the researchers even though there is a need for development of
many new techniques and algorithms for big data analysis in order to get optimal solutions. In this paper,
a detailed study about big data, its basic concepts, history, applications, technique, research issues and
tools are discussed.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired
PRACTICE OF CALIBRATION TECHNOLOGY FOR THE SPECIAL TEST EQUIPMENT ieijjournal
For the issues encountered in the special test equipment calibration work, based on the characteristics of
special test equipment, the calibration point selection,classification of calibration parameters and
calibration method of special test equipment are briefly introduced in this paper, at the same time, the
preparation and management requirements of calibration specification are described.
8th International Conference on Signal, Image Processing and Embedded Systems...ieijjournal
8th International Conference on Signal, Image Processing and Embedded Systems (SIGEM 2022) is a forum for presenting new advances and research results in the fields of Digital Image Processing and Embedded Systems.
Informatics Engineering, an International Journal (IEIJ)ieijjournal
Informatics is rapidly developing field. The study of informatics involves human-computer interaction and how an interface can be built to maximize user-efficiency. Due to the growth in IT, individuals and organizations increasingly process information digitally. This has led to the study of informatics to solve privacy, security, healthcare, education, poverty, and challenges in our environment.
International Conference on Artificial Intelligence Advances (AIAD 2022) ieijjournal
International Conference on Artificial Intelligence Advances (AIAD 2022) will act as a major forum for the presentation of innovative ideas, approaches, developments, and research projects in the area advanced Artificial Intelligence. It will also serve to facilitate the exchange of information between researchers and industry professionals to discuss the latest issues and advancement in the research area. Core areas of AI and advanced multi-disciplinary and its applications will be covered during the conferences.
Informatics Engineering, an International Journal (IEIJ)ieijjournal
Call for papers...!!!
Informatics Engineering, an International Journal (IEIJ)
https://airccse.org/journal/ieij/index.html
Submission Deadline: July 02, 2022
Here's where you can reach us : ieijjournal@yahoo.com or ieij@aircconline.com
http://coneco2009.com/submissions/imagination/home.html
8th International Conference on Artificial Intelligence and Soft Computing (A...ieijjournal
Call for papers...!!!
8th International Conference on Artificial Intelligence and Soft Computing (AIS 2022)
August 20 ~ 21, 2022, Chennai, India
https://csit2022.org/ais/index
Submission Deadline: July 02, 2022
Here's where you can reach us : ais@csit2022.org or aisconf@yahoo.com
https://csit2022.org/submission/index.php
Informatics Engineering, an International Journal (IEIJ) ieijjournal
Informatics Engineering, an International Journal (IEIJ)
Submission Deadline : June 18, 2022
submission link
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website link
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International Conference on Artificial Intelligence Advances (AIAD 2022)ieijjournal
International Conference on Artificial Intelligence Advances (AIAD 2022)
August 27 ~ 28, 2022, Virtual Conference
Webpage URL:
https://www.aiad2022.org/
Submission Deadline: June 04, 2022
Contact us:
Here's where you can reach us: aiad@aiad2022.org (or) aiadconf@yahoo.com
Informatics Engineering, an International Journal (IEIJ)ieijjournal
call for paper
Informatics Engineering, an International Journal (IEIJ)
Submission Deadline : May 28, 2022
Submit your paper through online :
http://coneco2009.com/submissions/imagination/home.html
Submit your paper through mail:
ieijjournal@yahoo.com or ieij@aircconline.com
for more details:
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Informatics Engineering, an International Journal (IEIJ) ieijjournal
Call for paper
Informatics Engineering, an International Journal (IEIJ)
https://airccse.org/journal/ieij/index.html
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Contact Us
Here's where you can reach us : ieijjournal@yahoo.com or ieij@aircconline.com
Paper Submission Link: http://coneco2009.com/submissions/imagination/home.html
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC.
Informatics Engineering, an International Journal (IEIJ)ieijjournal
Informatics is a rapidly developing the field. The study of informatics involves human-computer interaction and how an interface can be built to maximize user efficiency. Due to the growth in IT, individuals and organizations increasingly process information digitally. This has led to the study of informatics to solve privacy, security, healthcare, education, poverty, and challenges in our environment.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Top 10 Oil and Gas Projects in Saudi Arabia 2024.pdf
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATION
1. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.1, March 2016
DOI : 10.5121/ieij.2016.4102 13
FROM FPGA TO ASIC IMPLEMENTATION OF AN
OPENRISC BASED SOC FOR VOIP APPLICATION
Faroudja Abid and Nouma Izeboudjen
Microelectronic and Nanotechnology Laboratory, Centre de développement des
technologies avancées, Algiers, Algeria
ABSTRACT
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to
describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on
an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL
code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show
that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is
given.
KEYWORDS
ASIC; FPGA; Opencores; OpenRISC; SoC; VoIP
1. INTRODUCTION
The decision between FPGA and ASIC as an implementation media is primary derived by the
targeted application and the required performances. Several issues are considered for this choose
namely, power consumption, area usage, device size, design cost and time to market. FPGA
platforms offer reduced NRE (Non Requiring Engineering) cost and short time to market; they
are widely used in several applications where a complete system can be implemented on a single
device. However the FPGA presents a major drawback, which is the increase in power
consumption compared to ASIC or full custom design. Nevertheless a hybrid approach that
combines the two mediums, where an FPGA is used for prototyping and then the design is ported
on ASIC, can be a solution for designers looking for rapid and easy solution for functional
validation. On the other hand, when migrating from FPGA to ASIC, systems designer have to
consider several technical areas during the design phase [1]. Among these criteria, the RTL
description of the IP cores included in the design. These RTL descriptions should be technology-
independent, thus the design architecture can be mapped to an ASIC or FPGA; and the migration
between the two technologies can be done with few RTL code changes. The use of FPGA for
prototyping allows earlier defect detection in the design process and significant time saving.
In this paper we present the OpenRISC [2] based SoC for VoIP application; the design
architecture is based on technology-independent building blocks described at RTL level. The
design is first prototyped on an FPGA platform for functional validation [3, 4] and then
implemented as an ASIC. A few works emerged from industrial and academic researches to
design SoC based on soft processor for VoIP application. Among these implementations, the
IP04 based Blackfin processor by David Rowe, from Rowetel [5]; he gives an open hardware
2. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.1, March 2016
14
implementation which is used by Dan Amarandei et al. for Wideband VoIP Middleware [6].
Another implementation based Xilinx PowerPC processor is given by Stelios Koroneos from
Digital OPSIS [7]. However the proposed solutions are based on proprietary processors that are
technology dependent. In our work we have used portable building blocks from Opencores to
build an OpenRISC processor based SoC. The OpenRISC soft processor can be mapped to an
ASIC or FPGA with few RTL code changes when migrating between FPGAs and ASIC, whereas
the others embedded processors like Blackfin, MicroBlaze and PowerPC are proprietary and are
not available in the ASIC technology. By using IP cores from Opencores to design a SoC,
designer are able to prototype their system on FPGA platform with ASIC perspective. In [4, 8]
we presented FPGA implementation of the VoIP architecture based OpenRISC processor. Herein
we expose the ASIC design and implementation of that SoC. The purpose behind ASIC porting is
reducing power consumption, which is a critical issue in SoCs targeted for VoIP application.
This paper is organized as follow: In Section II, the related works regarding ASIC
implementation of the SoCs based OpenRISC are given. Section III deals with the FPGA and
ASIC advantages and drawbacks. In Section IV, the technology-independent approach is
presented. The FPGA prototyping of the proposed SoC architecture is presented in Section V.
Section VI exposes the ASIC implementation of the designed SoC; the synthesis results in term
of area utilization and power consumption are exposed in this section.
2. RELATED WORKS
Several works regarding the OpenRISC based ASIC implementations, where the design was
implemented as a standard cell ASIC using diverse technologies are reported in the literature. In
[9] James Tandon has developed a system used to measure temperature maps, and power supply
noise variation across a chip on remote devices through the custom protocol. The system includes
the OpenRISC core, I2C interface, Ethernet 10/100Mbit, UART, RAM and a boot ROM. The
system was prototyped using Altera StratixIII FPGA and then implemented as a standard cell
ASIC using the Rhom 0.18 μm process technology. The operating frequency is of 100 MHz and a
chip size of 25mm². In [10] the authors developed a SoC that run the uClinux distribution, the
ASIC was targeted for the frequency of 200MHz and has been designed using the TSMC 0.13μm
process technology, the system was prototyped using Xilinx Virtex2 FPGA. Others standard cells
based implementations of the OpenRISC processor as a chip are reported in [11-13]. In the work
exposed in [12], the OpenRISC was implemented as a chip using the UMC 13μm technology
process, with the operating frequency of 100 MHz. In [13], the OpenRISC with 8 KB data cache
and 8 KB instruction cache was synthesized using a 130nm process, the author stated that “When
optimized for area, the processor had an area of 2.16 mm² and a maximum frequency of 36 MHz.
When optimized for speed, the area was 2.20 mm² and the maximum frequency of 178 MHz”.
Other implementations based on structured ASIC [14, 15] which is an intermediate technology
between FPGA and ASIC; where a portion of silicon is reused were also considered [16, 17]. In
[16] the ASIC has been designed using the TSMC 0.18 μm process technology with the
structured ASIC approach, the operating frequency is of 90 MHz and a chip size of 13mm².
Commercial companies like Flextronics International and Jennic Limited manufactured the
OpenRISC as part of an ASIC. The technology-independent criteria and a portable RTL code of
the OpenRISC make it suitable for, mainly, designs that are prototyped on FPGA platform with
an ASIC perspective. It is noticeable that CMOS standard cell implementation is a widespread
approach for ASIC designs, the structured ASIC approach remain not widely adopted.
3. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.1, March 2016
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3. FPGA AND ASIC ADVANTAGES AND DRAWBACKS
3.1. FPGA advantages and drawbacks
FPGAs are reprogrammable platforms, widely used in various designs and divers target
applications. They are progressively used as final product platforms for low volume production.
In FPGA based system design, there is no manufacturing turn around time, thus the design can be
tested and evaluated quickly allowing shorter development cycle, short time to market and lower
NER costs. In addition there is no mask making compared to ASIC. Regarding the CAD
(Computer Aided Design) tools, the FPGA vendors provide tools that help designers to undertake
the steps involved in the FPGA design flow. Among them the ISE software from Xilinx and
Quartus II from Altera, these tools are available in low end version for free download. The full
version are also available for reasonable fee compared to the ASIC tools cost. However when the
design is targeted for low power application and high volume production, the size, power
consumption and cost increase. This presents a major drawback which limits the FPGA platforms
application to low volume production compared to ASIC. Regarding the FPGA design flow, it is
usually a GUI (Graphical User Interface) based tool. Herein the development tool used for the
design and implementation is the ISE (Integrated Synthesis Environment) Xilinx 13.1 tool, which
is used for all steps involved in the design flow; it includes synthesis and Place&Route.
3.2. ASIC advantages and drawbacks
ASIC are IC (Integrated Circuit) designed for specific applications and a customized hardware
implementations of the design. They can be classified to three major parts, namely, the full
custom based ASIC that is highest performance and small size however it is a more complex and
cost consuming. Secondly, the semi custom ASIC based on gate array and standard cell. The third
type is structured ASIC [14, 15]. ASIC implementation allows low power consumption, low cost
for important volume production, high speed and smaller die size that leads to board size
reduction. In opposite to FPGA designs that are digital only, ASIC technology allows analog
circuit and mixed signal design implementations. For power optimization there are several
techniques such as clock gating, multi-Vth, operand isolation, which can be used in ASIC
implementation. These techniques are, generally, not possible on FPGA. The drawbacks of ASIC
are mainly the long development cycle, thus important time to market. The NER and CAD tools
are significantly high cost. The verification of deep sub-micron effects is not required in FPGA,
whereas this verification is required in ASIC.
4. TECHNOLOGY INDEPENDENT APPROACH
4.1. Technology-independent approach concept
The technology-independent approach is based on the reuse of portable building blocks described
at RTL level for SoC design. This approach omits the reference to the target technology, this
criteria allows portability of the design based on the technology-independent IP cores, from ASIC
to FPGA or vice versa. By adopting this approach, SoC designer leverages, in one hand, the
reusable propriety of these IPs, thus a new SoC can be created by adding, dripping or modifying a
new core, this reuse process facilitates the rapid creation and verification. In the others hand
designer are able to prototype their design into FPGA platform with an ASIC perspective. Figure
1 schematizes the technology-independent approach.
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IPs Library
RTL code
(VHDL, Verilog)
ASIC design
flowFPGA design
flow
FPGA target ASIC target
Figure 1. Technology independent approach scheme
4.2. Design architecture
Figure 2 displays the overall architecture of the proposed SoC for VoIP application. From the
hardware viewpoint the architecture of the design is based on the IP reuse strategy [4] that
facilitates the rapid creation and design verification process and allows lower design cost. The
design includes a 32bit RISC processor core and a set of technology-independent elements
needed to provide VoIP functionality. Elements are mainly, the MAC/Ethernet (connection is
established by this IP), the debug unit for debugging purpose, a memory controller and Universal
Asynchronous Receiver Transmitter (UART). An AC97 controller core is also selected and added
for audio processing application. The designed SoC was firstly prototyped on Xilinx Virtex5
FPGA for functional validation. The details of the proposed SoC architecture and the system
prototyping were presented in previous works [4, 8].
Figure 2. VoIP SoC Hardware architecture
5. FPGA PROTOTYPING
5.1. FPGA design flow and tools
Figure 3 illustrates the FPGA design flow, from functional specifications to FPGA configuration.
FPGA design flow is usually GUI based tool. In this work, the development tool used for the
DDR2Flash
Serial Interface
e
ROM Boot Debug Unit OpenRISC or1200
Memory
Controller UART
AC97
Controller
MAC/Ethernet
Wishbone Bus
Physique interface
RS232
5. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.1, March 2016
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design and implementation is the ISE Xilinx 13.1 tool, which is used for all steps involved in the
design flow. It includes synthesis, Place&Route, bitstream generation and FPGA configuration
and test.
Figure 3. FPGA design flow
5.2 FPGA synthesis results
The design has been implemented on FPGA Virtex5 (LX50) platform and the synthesis is
performed using XST (Xilinx Synthesis Tool). The operating frequency is 66 MHz. Results show
that the architecture uses 50% of BRAM memories, 27 % of slice registers and 48% of slice
LUTs. It is noticeable that the BRAM memories are the most used resources, the use of the other
resources remain low. The power consumption is about 4.23W. Table 1 tabulates the FPGA
resources allocated to SoC components.
Table 1. FPGA resources allocated to SoC components.
6. ASIC IMPLEMENTATION
6.1. ASIC design flow and tools
The ASIC design flow defers moderately from the FPGA design flow. The main difference is in
the verification setups. Figure 4 presents the ASIC design flow; it involves more verification
Components # of LUT # of Slice Register # of BRAM # of Occupied Slice
OR1200 24% 8% 45% 35 %
Ethernet 6% 3% 2% 10 %
UART 1% 0% 0% 2%
AC97 2% 2% 0% 5%
Debug Unit 3% 2% 0% 6%
Specifications
RTL Description (HDL)
Synthesis
Place&Route
FPGA Configuration& Test (Bitstream)
Behavioural
Simulation
Static Timing
and power
analysis
6. Informatics Engineering, an International Journal (IEIJ), Vol.4, No.1, March 2016
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compared to the FPGA design flow. A detailed presentation of the steps involved in both FPGA
and ASIC design flows is given in [18].
Figure 4. ASIC design flow
6.2. ASIC synthesis results
The synthesis for ASIC implementation was performed using Cadence RTL Compiler v10.10-
s209_1 [19], with 0.18µm TSMC process technology. This step is completed using a compile
script. Compilation was based on the top-down approach, where all modules are compiled
starting from the top level of the design hierarchy. Few RTL changes are required when targeting
an ASIC implementation. The changes are mainly done in defines.v files and Verilog files that
include memories instances. We have set the configuration for an ASIC target and instantiate the
targeted ASIC memories. Note that there are several supported ASIC RAMs memories namely,
Artisan Single-Port Sync RAM, Artisan dual-Port Sync RAM, Avant Two-Port Sync RAM,
Virage Single-Port Sync RAM and Virtual Silicon Single-Port Sync RAM.
In our case we have chosen the Artisan Single-Port Sync RAM and Artisan dual-Port Sync RAM
memories. We have first used the random logic approach using flip flop for instances including
memories, synthesis results using this approach were reported in our previous work [20]. In this
work, a RAM compiler approach which is area-efficient has been used to improve the results. The
appropriates memories was generated by the ‘IMEC ASIC and design service team’
(www2.imec.be) using the memory compiler tool (SRAM-DP-HS SRAM Generator)) from
Artisan Components, INC with TSMC 0.18 µm technology process.
Back end
Front end
Equivalency
checking
Behavioral
Simulation
Equivalency
checking
Static
Timing
Analysis
Specifications
RTL Description
(HDL)
Synthesis
Place&Route
Tap out (final layout
GDSII format)
DFT (ATPG (BIST,
Scan, and JTAG)
Floorplanning
Static
Timing and
power
analysis
Technology
Library and
design contraints
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6.2.1. Area estimation
The area utilization of the OpenRISC based SoC is about 2.65 mm² and the OpenRISC processor
occupied the area of 2.34 mm². As expected the use of dedicated memories enables significant
reduction, in area and power consumption. Figure 5 presents the ASIC synthesis results of the
designed SoC in term of area utilization.
Figure 5. Area of standards cells (mm²)
6.2.2. ASIC power estimation
Herein we give the RTL power estimation, the histogram in Figure 6 shows the ASIC power
consumption of some IPs included in the designed SoC. The total power consumption is about
113.75 mW with 113.67 mW for dynamic power consumption and 0.072 mW for the static
power. Table 2 summarizes the instances power usage percentages. It is noticeable that the
OpenRISC is the most power consuming.
Table 2. ASIC synthesis results regarding instances power usage percentages
The histogram in Figure 7 represents the power for ASIC and FPGA. The FPGA power
estimation is done using the XPower Analyzer by Xilinx [21]; the total power consumption is
about 5160 mW. We recognize that the estimates may not be extremely accurate since measuring
the gap between the two media needs a specific measurement approach that gives accurate
measurement. Nevertheless the RTL power estimation results give a preliminary inference about
the power consumption gap between the two media. It is noteworthy to precise that the ASIC
power consumption is considerably less than the FPGA power consumption
Instances Instance Power Usage
Or1200_top 23 %
Or1200_top_cpu 17.5%
Ethmac 13.65%
UART 16550 2.44%
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0
20
40
60
80
100
120
1 2 3 4 5
Power(mW)
Dynamic and static Power consumption for IPs on ASIC
Série2
Série1
Figure 6. Histogram of power consumption for IPs on ASIC
Figure 7. Histogram of power for ASIC and FPGA
7. CONCLUSIONS
We presented in this work an ASIC design of a SoC for VoIP application. The SoC architecture is
based on the technology-independent building blocks described at RTL level. A hybrid approach
has been applied, where the FPGA platform is used for the functional validation of the design,
which is then implemented as an ASIC.
We exposed mainly synthesis results, primary regarding the area issue; that is an important issue
for ASIC design cost, and we have given an estimation of the RTL power consumption. In term
of area utilization, results show that the SoC occupied the area of 2.67 mm² in which the
OpenRISC processor occupied the area of 2.34 mm². Regarding the power consumption, the total
power consumption in ASIC is about 113.75 mW whereas in FPGA implementation the power
consumption is about 5160 mW. As expected the ASIC power consumption is considerably less
than the FPGA power consumption. We consider that, FPGAs are a good solution for functional
validation and prototyping of the design that will be implemented in ASIC technology. But they
cannot replace ASIC mainly for design requiring low power consumption.
Dynamic
power ■
Static
power■
SoC_VoIP Or1200 Ethernet Debug UART
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Authors
Faroudja ABID received her engineering degree in Electronics Engineering from the University of Tizi
ouzou, Algeria; and the M.S. from Ecole Nationale Polytechnique (ENP) of Algiers, Algeria. Currently,
researcher at the CDTA center. Her research interests include embedded system, FPGA design, ASIC
design, Real-time and System on Chip Design.
Nouma Izeboudjen received her engineering degree in Electronics Engineering from the University of
sciences and technology Houari Boumedienne, Algeria. And the P.H.D degree from Ecole Nationale
Polytechnique (ENP) of Algiers. Currently, researcher at the CDTA center. Her research interests include
embedded system, FPGA and ASIC design, System on Chip Design and neural network.