Faststream Technologies IP Interfaces includes Analog Data Acquisition controller IP, Multi-Protocol Synchronous Serial Engine IP, 18-bit Pipeline DSP Slice IP core, Improved ADC IP, AXI-USB 2.0 Device IP, External Flash Memory Interface IP, Precision Time Protocol IP, and Delay Locked Loop IP.

1. IP INTERFACES
ANALOG DATA ACQUISITION CONTROLLER IP
The analog data acquisition controller IP interfaces various industry-standard ADCs with digital
interfaces like SPI, I2
C, parallel, LVDS, etc. It also generates required control signals to
sequence the data acquisition task for a microcontroller thus off-loading these time-consuming
tasks from the host microcontroller.
Salient features:
• AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
• User-configurable acquisition parameters: Sampling frequency, number of samples in
bursts.
• Programmable ADC interface to connect different types of ADCs in addition to analog
multiplexers to connect multiple analog channels
• Optimized power consumption
Block diagram:

2. Applications:
• In conventional FPGAs require an external ADC to convert multiple analog signals into
digital values for real-time processing.
• Sensor node with multiple analog sensors.
MULTI-PROTOCOL SYNCHRONOUS SERIAL ENGINE IP
The Multi-Protocol Synchronous Serial Engine IP integrates basic serial interface
protocols like UART, SPI, and I2C into a single AXI interface port. The individual
modules for these protocols have been implemented in a ruggedized form to avoid bus
errors due to interfering noise from various sources thus making it suitable for application
in automobile electronics.

3. Salient features:
• AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
• Ruggedized SPI, I2C, and UART interface
• User-configurable number and type of interfaces through a configuration tool
• User-configurable parameters of each interface like baud rate/ datarate, modes, length of
transmission, etc.
• Supports master and slave modes for SPI and I2C interfaces
• Configurable number of slaves on SPI interface
• Contains hardware FIFO for UART, SPI, and I2C interfaces with configurable depth up
to 1024 words
Block diagram:
Applications:

4. • Sensor interfaces with SPI and I2C protocol.
• UART interfaces for data transmission between nodes.
18-BIT PIPELINE DSP SLICE IP CORE
The 18-bit Pipeline DSP slice IP Core provides the best utilization of device resources like
memory, I/O, processor, and clock. It is based on the pipelining technique which uses
instruction-level parallelism within a single processor. It supports many independent functions,
including multiplier, multiplier accumulator (MAC), multiplier-adder, higher bit adder, 3-input
adder, barrel shifter, wide bus multiplexers, magnitude comparator, and counter. It also
supports connecting multiple DSP slices IP Core to form wide math functions, DSP filters, and
complex arithmetic. The architectural highlights of the 18-bit Pipeline DSP slice IP core are as
follows:

5. • 18-bit by 18-bit, two's-complement multiplier with the 36-bit result, sign-extended to 48
bits
• Three-input, flexible 48-bit adder/subtractor with optional feedback of accumulator
register.
• Dynamic user-controlled operation select pins to adapt according to single/multiple slice
functions from clock cycle to clock cycle
• Cascading of 18-bit input bus and 48-bit output bus using
INTERCONIN/INTERCONOUT pins supporting propagation of partial products from
one slice to another.
• Multi-precision multiplier and arithmetic support right shifting by 17 bits to obtain wide
multiplier partial products
• Symmetric rounding and sequential/parallel support for greater computational accuracy
• Multi-level pipelining options for control and data signals to improve throughput
• MFC(Multi-Functional C-input) supports multiply-add operation, three-input addition,
and rounding mode
• Separate reset and clock enable for control and data registers, I/O registers, ensuring
maximum clock performance
IMPROVED ADC IP
Flash ADCs are one of the fastest ADCs available which can achieve Giga samples per second
conversion rates. One of the limitations of this ADC type is that their architectural complexity
increases exponentially with an increase in the bit resolution. Hence these are generally available
up-to 8-bit resolutions. On the contrary, other ADC architectures are slow sampling and are
available with high bit resolutions viz. 16-22 bit resolutions. It would be desirable to combine the
fast conversion speeds of flash ADCs with high resolutions of SAR and Σ-Δ ADCs.
The Improved ADC IP provides an interface with a flash ADC and supporting components in
implementing a multi-step ADC to achieve higher bit resolutions thus integrating the speed of
the flash ADC with the resolution of SAR ADC. The controller module in the IP generates all the
necessary signals for the ADC and the supporting components to operate in unison. It can be
used to double the resolution in bits for any ADC in consideration.

6. Salient features:
• The AXI4-Lite standard interface connects as a 32-bit slave on the AXI interface bus.
• Doubles the nominal flash ADC resolution
• Programmable sampling rates and ADC interface types to connect multiple types of
ADCs and DACs
Application:
• High-resolution requirement analog signals from sensors.
Block Diagram:

7. AXI-USB 2.0 DEVICE IP
USB is a generic interface in the modern days to connect to various high-speed data peripherals.
Many USB device/client controllers are introduced in the embedded systems market, which
enables interfacing a host microcontroller to quickly and easily connect to a USB host such as a
PC or industrial PC. One of the major limitations of these controllers is the bottleneck on data
rate imposed by the interface between the host microcontroller and the USB device controller
which more often is a serial UART interface, SPI interface, JTAG interface, or FIFO interface.
In FPGA based embedded systems with reconfiguration capability, it is desirable to implement
this USB controller on-chip and thus implement an SoC. Our AXI-USB 2.0 Device IP supports
high speed, high bandwidth isochronous transactions.
We present an AXI-USB 2.0 Device IP to implement on an FPGA in an embedded system. It
carries out all tasks like USB device enumeration, endpoint instantiations, etc., and enables bulk,
isochronous, interrupts, and control packet transfers over USB. With the addition of a low-cost
external USB PHY chip, a USB device can be realized using this IP in no time. The user
interface to the host microcontroller instantiated on the FPGA is provided in an AXI interface
format and thus, the USB controller is made as a memory-mapped device accessible from the
industry-standard AXI bus from the host microcontroller.
Salient features:
• AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
• USB serial interface engine implemented to support USB2.0 full speed and high-speed
interface
• Supports ULPI interface to external PHY chip
• Supports control, bulk, interrupt, and isochronous transfers on USB interface

8. • 8 endpoints instantiated with endpoint 0 as the control endpoint
• Handles USB enumeration process
EXTERNAL FLASH MEMORY INTERFACE IP
Flash memory forms a basic constituent in many FPGA based embedded systems using Xilinx
SRAM based FPGAs. This is primarily because they store the bitstream file for the FPGA using
which the FPGA configures itself at every startup. After configuration, the flash memory is
available for user data storage and can be used for non-volatile data storage as long as it is
outside of the bitstream area. The External Flash Memory Interface IP designed atFastream
Technologies allows accessing these memory locations as a memory-mapped interface and
makes the controller agnostic of the underlying SPI interface on which the memory is being
interfaced.
Salient features:
• AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
• Page-wise programming according to the flash memory requirements handled by the IP
• Memory single bit error detection and correction implemented in the IP-core.
• User-configurable, industry-standard NOR flash memories can be interfaced with the IP
on SPI and Quad-SPI interfaces.
Block diagram:

9. PRECISION TIME PROTOCOL IP
Time synchronization is of prime importance in distributed industrial control systems and in
automotive networks. The timestamps of events in a distributed control system should match
with considerable accuracy to be able to correlate them together or for the control system to
operate properly. Various time synchronization protocols are used on different networks which
allow synchronization up to various accuracies. Precision Time Protocol or PTP or IEEE1588 is
one such protocol that allows synchronization of an order of 1us with the master (most accurate)
clock in the network. On local area Ethernet networks, it is implemented in various ways most
often in software. This method is inherently less accurate for timestamping which results in a
reduction of synchronization accuracy. Implementing a time stamp unit in hardware that
generates time stamps as soon as the PTP packet arrives from the network allows more accurate
time stamps and hence, better synchronization. The precision time protocol IP designed at
Faststream technologies implements the PTP on Ethernet networks and sends the packet to the
MAC. A precise time stamping unit instantiated in the IP captures the time stamp as soon as the
packet is received and decoded. The values of offset and delay required to correct the local slave
clock are generated by the IP.

10. Salient features:
• AXI4-Lite standard user interface. Connects as a 32-bit slave on AXI interface
• Identifies PTP packets like sync, follow-up, and delay-response and sends delay-request
packets.
• PPS clock output
• Offset and drift adjustable clock internally used
Block diagram:

11. DELAY LOCKED LOOP IP
Generation of the clock signal with a fixed but programmable phase difference with respect to a
reference input clock is critical in many applications. An all-digital DLL design with several
features like a wide lock range for input frequencies, short locking time, and reduced jitter is
achieved by this IP. The all-digital nature of the DLL design allows the addition of clocking
resources in FPGA prototyping of new IPs and for FPGA-based embedded systems using
multiple clocking resources. Rigorous simulation has been carried out to evaluate the robustness
and performance of the IP. The Delay Locked Loop IP can be used for a variety of applications
that require precise phase shifts with respect to reference clocks to adjust for the channel routing
delays on the PCB.
Applications:
• BIST circuits for measurement of setup and hold times
• Phase detection and tracking
• Clock recovery from the input data stream
• High-speed DDR type interface applications to align data with clock edges
Salient features:

12. • Timing resolution: 80ps
• Operating frequency range: 160MHz - 700 MHz
• Lock time: 11 cycles
• Generates user-configurable precise phase shifts from 00 to 3600 with a resolution of 10
• Delays multiple periodic or aperiodic signals independent of voltage and temperature.
Block diagram: