FPGA based deign of Digital Communication Systems

1. Short Term Training Program on
“FPGA Based Digital Systems with Application
to SDR in Cognitive Environment”
FPGA Based Communication Systems
Prof. Anish Goel

2. Contents
 Digital Communication Systems
 BPSK Modulator
 FPGA Implementation
 Direct Digital Synthesiser
 AES Encryption
FPGA Based Comm Systems:Prof. Anish Goel2

3. Digital Communication System
FPGA Based Comm Systems:Prof. Anish
Goel
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4. Digital Communication
FPGA Based Comm Systems:Prof. Anish
Goel
 Components of the digital communication system are both digital and
analog parts.
 Digital part consists of digital source/user, source encoder/ decoder,
channel encoder/ decoder and the digital modulator/ demodulator.
 Analog part is made of the transmitter, receiver, the channel models
and noise models.
 Message to be sent is from a digital source, in our case, from a
computer.
 Source encoder accepts the digital data and prepares the source
messages.
 Role of the channel encoder is to map the input symbol sequence
into an output symbol sequence.
 Binary information obtained at the output of the channel encoder is
than passed to a digital modulator which serves as interface with the
communication channel.
 Main purpose of the modulator is to translate the discrete symbols
into an analog waveform that can be transmitted over the channel
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5. BPSK Modulation and Demodulation
FPGA Based Comm Systems:Prof. Anish
Goel
 Digital modulation is the process by which digital symbols are transmitted into
waveforms that are compatible with the characteristics of the channel.
 The modulation process converts the signal in order to be compatible with available
transmission facilities.
 At the receiver end, demodulation must be accomplished by recognizing the signals.
 The modulation technique used in this paper is BPSK (Binary Phase Shift Keying)
and it is widely used in digital transmission.
 BPSK modulation is the simplest form and most robust of all the PSK modulation
techniques.
 The BPSK modulator is quite simple and is illustrated in next fig.
 The binary sequence m(t) or modulating signal is multiplied with a sinusoidal carrier
and the BPSK modulated signal s(t) is obtained.
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6. BPSK waveforms
FPGA Based Comm Systems:Prof. Anish
Goel
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7. BPSK Demodulator
FPGA Based Comm Systems:Prof. Anish
Goel
 To demodulate the signal, it is necessary to
reconstitute the carrier.
 This process is made in the Carrier Recovery Circuit.
 Next, the BPSK modulated signal is multiplied with
the carrier, pass through an integrator and a decision
circuit to obtain in the end the modulating signal.
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8. BPSK implementation on FPGA
FPGA Based Comm Systems:Prof. Anish
Goel
Sine
1
Sine
1I
PN -
Seq
2:1
8
bit
Mu
x
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9. Waveforms
FPGA Based Comm Systems:Prof. Anish
Goel
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10. FPGA Implementation
FPGA Based Comm Systems:Prof. Anish
Goel
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11. SIGNAL GENERATOR USING DIRECT
DIGITAL SYNTHESIS
FPGA Based Comm Systems:Prof. Anish
Goel
 Signal generators are generally large in size due to its bulky
hardware and it is not portable also.
 It can only generate particular set of waveforms.
 We cannot create any arbitrary waveform. Nowadays digital signal
generators are available but still it is not reconfigurable and it cannot
create any type of waveform we want.
 In this demo we use FPGA to realize all the hardware parts of signal
generator in a better way and we use a method called Direct Digital
Synthesis to realize any type of waveform we want.
 Direct Digital Synthesis (DDS) is a method for digitally creating
arbitrary waveforms from a single, fixed-frequency reference clock.
 DDS has many advantages over its analog counterpart and improved
phase noise.
 It has precise control of the output phase across frequency switching
transitions.
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12. DDS System
FPGA Based Comm Systems:Prof. Anish
Goel
 The output of FPGA will be digital and this digital data is given
to Digital-to-Analog Convertor (DAC).
 DAC converts the digitally created signal to analog form thus
creating a versatile, flexible signal generator.
 The DAC and FPGA share a single clock source.
 Since we are using FPGA as a hardware part, in future easily
upgrade the signal generator by altering the FPGA design.
 There is no need of extra cost to buy new signal generator
unlike analog signal generator.
 Three main units of this project are
 Clock Source
 FPGA
 DAC
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13. DDS Design
FPGA Based Comm Systems:Prof. Anish
Goel
FPGA
DDS
DACDigital data
Clock Source
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14. Output Waveforms
FPGA Based Comm Systems:Prof. Anish
Goel
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15. Output Waveforms
FPGA Based Comm Systems:Prof. Anish
Goel
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16. AES
FPGA Based Comm Systems:Prof. Anish
Goel
 The Advanced Encryption Standard was
standardized in 2001 by the National Institute of
Standards and Technology (NIST).
 Since then, various hardware implementation
architectures and optimizations of AES algorithm
have been proposed for different applications and
their performance have been evaluated by using
ASIC libraries and FPGA.
 Cryptographic algorithm AES is currently used in a
very large variety of scenarios.
 The most common example is e-commerce and
financial transactions, which have strong security
requirements.
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17. AES Algorithm
FPGA Based Comm Systems:Prof. Anish
Goel
 AES is a symmetric-key block cipher with a data block
length of 128 bits, which supports different key lengths of
128, 192 or 256 bits.
 The AES is a round-based encryption algorithm. The
number of rounds, Nr, is 10, 12, or 14, when the key
length is 128, 192 or 256 bits, respectively.
 In the encryption of the AES algorithm, each round,
except the final round, performs four transformations:
SubBytes, ShiftRows, MixColumns and AddRoundKey,
while the final round does not have the MixColumns
transformation.
 The key used in each round, called the round key, which
is generated from the initial key by a separate key
scheduling module.
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18. AES Algorithm Steps
FPGA Based Comm Systems:Prof. Anish
Goel
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19. Substitute Bytes
FPGA Based Comm Systems:Prof. Anish
Goel
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20. Shift Rows
FPGA Based Comm Systems:Prof. Anish
Goel
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21. Mix Coloumn
FPGA Based Comm Systems:Prof. Anish
Goel
 effectively a matrix multiplication in GF(28) using prime poly m(x)
=x8+x4+x3+x+1
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22. Add Round Key
FPGA Based Comm Systems:Prof. Anish
Goel
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23. AES Key Expansion
FPGA Based Comm Systems:Prof. Anish
Goel
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24. Key Expansion Rationale
FPGA Based Comm Systems:Prof. Anish
Goel
 designed to resist known attacks
 design criteria included
 knowing part key insufficient to find many
more
 invertible transformation
 fast on wide range of CPU’s
 use round constants to break symmetry
 diffuse key bits into round keys
 enough non-linearity to hinder analysis
 simplicity of description
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25. AES Cracking
FPGA Based Comm Systems:Prof. Anish
Goel
https://www.reddit.com/r/theydidthemath/comments/1x50xl/time_and_energy
_required_to_bruteforce_a_aes256/
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