Andes Technology Corporation provides a product selector guide and overview of its AndesCore CPU architecture and associated products for Internet of Things (IoT) applications. The AndesCore architecture was designed specifically for the power, performance, and security needs of IoT devices, unlike architectures for PCs and smartphones. Key features of AndesCore include frequency throttling, a patented memory architecture, and custom instructions. AndesCore CPU cores range from small 2-stage pipelines to larger 8-stage pipelines and include options for security, custom instructions, and digital signal processing. Andes also offers associated platform IP and software development tools to simplify IoT product development.

1. Andes Technology Corporation
Product Selector Guide
AndesCore: CPU Architecure for the Future
In the past, the major driver of the industry
was the PC, then the mobile phone and its
associated devices. These product catego-
ries demanded a certain type of CPU archi-
tecture. The PC was driven by CPUs with
ever increasing clock frequnecy. The mobile
phone demanded high clocks but were sur-
rounded by coprocessors to handle special-
ized functions—video, audio, position location, camera, low-energy
Bluetooth links to a wide variety of external devices. With the advent
of IoT, the CPU is now in intelligent sensing devices requiring moderate
clock speeds but with extreme battery life. For the PC, power was less a
concern than for the mobile phone, which could rely on regular intervals
of battery recharge. Both, however, increasingly demanded increased
security. For the IoT device, power is the ultimate concern, followed by
performance and security.
The CPUs architectures that serve the PC and mobile phone were created
with their unique operating requirements in mind. With the advent of IoT,
both architectures have attempted to accommodate the extreme power
requirements of IoT devices: years of battery life, 32-bit CPU perfor-
mance, and unique security demanded by unattended operation. Andes
determined that IoT applications required a CPU architecture designed
with these unique capabilities built in not retrofitted on top of an archi-
tecture designed for mobile phones and PCs. Furthermore, the years of
legacy software constrains older architectures from major alterations to
deliver the demands of IoT applications.
Without the drawback of architectures dedicated to PCs and smart phones,
Andes new more up-to-date CPU architecture, AndesCore, has been designed
into IoT devices such as electronic shelf labels, which requires a 5-year life on
a coin cell battery. The architecture enabling enormous power savings while
providing high performance, and hacker resistant security includes frequency
throttling, a patented memory architecture, and custom instructions.
Andes’ portfolio of low-power 32-bit CPU cores satisfies a wide range
of applications such as mobile, digital-home, industrial, and automotive
designs. The portfolio spans from the ultra small 2-stage pipeline N7 and
3-stage pipeline N8, which comes in a high-security version, the S8, and
a version that allows designers to define application-specific instructions
using the Andes Custom Extension (ACE) capability called the E8. (See
table below.) The midrange of the portfolio, the N9 and N10, each have a
5-stage pipeline. The N10, with 32-bit reg-
isters, comes in a DSP-enabled version, the
D10, that offers 130 new DSP instructions,
including a single-cycle, 32x32 hardware
multiplier. The D10 supports 16-bit and
8-bit SIMD instructions, plus 64-bit signed
and unsigned addition and subtraction.
AndeStar™ instruction-set architecture
AndeStar™ is a patented 32-bit RISC-style CPU architecture. Its instruction
set includes 16-bit and 32-bit mixed-length instructions to achieve optimal
system performance, code density and power efficiency. AndeStar archi-
tecture supports 16 or 32 32-bit general purpose registers, instruction and
data cache, instruction and data local memory, DMA, MMU, MPU, copro-
cessors, DSP instructions, saturation instructions, 16MB or 4G address
space, interrupt mechanisms, etc. It also includes power management
instructions and interface protocol to simplify switching among different
SoC operating modes and a floating-point coprocessor supporting IEEE-
754 compliant instructions.

2. AndesCore™ CPU IP Product Families
N7 N8 E8 S8 N9 N10 D10 N13
I/O Bus Interfaces AHB-lite/APB AHB-lite/APB AHB-Lite/APB AHB-Lite/APB
AHB-lite/APB,
AHB/2AHB, AXI
AHB-lite/APB,
AHB/2AHB, AXI
AHB-lite/APB,
AHB/2AHB, AXI
AHB/AXI,
2AHB/2AXI,
2AXI(64-bit)
Architecture Version V3m V3m V3m V3m V3 V3 V3 V3
Hardware FPU FPU FPU FPU
Flash Fetch YES YES YES YES
Power Brake (Freq Scaling) YES YES YES YES YES YES YES YES
Pipeline Stages 2 3 3 3 5 5 5 8
Branch Prediction Static Dynamic Dynamic Dynamic
Inst/Data Caches FlashFetch^^ FlashFetch^^ FlashFetch^^ FlashFetch^^ 1/2-Way 1/2-Way 1/2/4-Way
Co-Processor Interface Yes Yes Yes
# of Registers 16 16 16 16 16/32 16/32 16/32 32
Address Space 16MB/4GB 16MB 16MB 16MB 16MB/4GB 4GB 4GB 4GB
MMU/MPU YES YES YES
Minimum KGates 13.0 13.8 13.8 20.9 29.5 38.2 48.9 95.1
Coremark/MHz 3.31 3.05 3.51 3.02 3.43 3.75 3.75 3.13
DMIPS/MHz 1.71 1.53 1.82 1.53 2.21 2.41 2.41 2.05
fMax† (MHz)†† 500 800 800 650 1000 1000 800 1500
Die Area (mm2)†† 0.013 0.015 0.015 0.022 0.036 0.056 0.060 0.092
Power (μW/MHz)†† 3.9 5.4 5.4 6.7 10 8.5 9.2 32
Special Features Security* Custom Inst.^ DSP SIMD L2 Cache/ECC
Peripheral Library
AG101P/
AE210P
AG101P/
AE210P
AG101P/
AE210P
AG101P/
AE210P
AG101P/
AE210P
AG101P/
AE210P
AG101P/
AE210P
AG101P
††28nm HPM †Freq. for slow process corner, 0.9vdd, 125C *Secure MMU, Secure Debug, Scrambling, Parity ^Andes Custom Extension™ (ACE) ^^a separate IP to
speed up instruction accesses from on-chip Flash and external Flash
For more information: e-mail info@andestech.com; Website: www.andestech.com; Tel: 1-408-809-2929; Address: Andes Technology USA Corp. 2375
Zanker Road, Suite 210 San Jose, CA 95131
The newest version of AndeStar, the V3, in the N9 through N13 cores, and
V3m in the N7 and N8 cores, includes all previous instructions and adds 19
new 32-bit and 19 new 16-bit instructions. The new instructions include
compare-and-branch on immediate, load/store with increment, shift-and-
ALU and the capability to share common instruction sequences. Combining
common operations reduces code size 30 percent
on average over the previous V2 ISA. The V3m is a
subset, which targets microcontroller applications,
excludes floating point, cache, MMU, and unaligned
accesses instructions.

3. AndeShape™ Platform IP and AndeSight™ IDE
To shorten time to market, Andes provides SoC designers periph-
erals—AndeShape™ Platform IP—and a flexible embedded soft-
ware development tool—AndeSight™ Integrated Development
Environment—to rapidly develop embedded SoCs. (See table be-
low.) AndeShape Platform IP comes in two versions. The AE210P
provides a wide range of highly-optimized standard peripherals to
simplify and accelerate SOC development for many MCU applica-
tions like IoT. The AG101P IP provides SOC designers richer and
high-speed peripherals for their high-end chip designs. AndeSight
is an Eclipse-based integrated software development environment
that provides easy and efficient embedded applications develop-
ment of target systems with small code size and fast performance.
AndeShape™ Platform IP (Peripherals)
AE210P – Generic Platform IP for
Micro-Controllers
AG101P – Generic Platform IP for
Embedded Systems
Architecture
Supports AndesCore™ N7/N8/E8/S8/N9/N10/D10 Supports all AndesCore™ Processors
APB-only AHB Bus Matrix with APB
AMBA AHB Bus for high speed devices
AMBA APB Bus for low speed devices
AHB Master/
Slave interfaces
Interrupt Signals Dedicated DRAM Interface for DMA and LCD Controller
AHB Bus Components
DMA Controller (DMAC) Static Memory Controller SDRAM Controller
Local Memory Bridge (LMBRG)
DMA Controller Ethernet MAC 10/100
LCD Controller
APB Bus Components
Timer (PIT)/PWM Watchdog Timer (WDT)
Timer Watch Dog Timer
Real Time Clock Interrupt Controller
I2C Controller (IIC) GPIO
GPIO Pulse Width Modulator
I²C controller
Serial Controller for SSP/
SPI/I2S/AC97UART Controller SPI Controller
Real Time Clock (RTC)
SD/MMC
Host Controller
UART Controller
Bus Controller/Bridge
AHB Bus Matrix
Controller (BMC)
AHB-to-APB Bridge
(APBBRG)
AHB Bus Controller AHB-to-APB Bridge
External Memory Interface SRAM/ROM/Flash
For more information: e-mail info@andestech.com; Website: www.andestech.com; Tel: 1-408-809-2929; Address: Andes Technology USA Corp. 2375
Zanker Road, Suite 210 San Jose, CA 95131