- Chip-Package-System (CPS) modeling involves integrated simulations of the chip, package and system to accurately model designs using advanced processes. - CPS co-design verification requires chip and package co-verification from both the chip side using a package model and the package/system side using a detailed extracted chip model. - Early analysis models of the chip are needed for early convergence of the package and system design. - A Chip Power Model extracted from the chip layout and data can be used to support simulations for issues like voltage regulation, jitter, impedance analysis, transients, and resonance effects across the CPS.

1. Chip-Package-System (CPS)Co-Design VerificationRonen Stilkol, Apache Design Solutions Chipex 2011 Track D: Power Management & Signal Integrity

2. What is Chip-Package-System?Chip-Package-System Sign-offPower, Thermal, Timing, EMI

3. Chip-Package-System (CPS)vdd_dvdd_agnd_dgnd_aBoard

4. Technology Impact on CPS Issues65nm vs 45nm45nm ,28nm vs 65nm 28nm : 65nm 65nm45nm45nm : 65nm Buffer di/dt RatioRelative DecapRelative ESRBuffer sizeDecap sizeDecap is less effective at advanced technologiesAdvanced technologies show more Di/DtOne die modeling is critical for CPS

5. Concurrent Chip-Package-System DesignZinPackageBoardTransient Analysis of entire system level PDN networkTraditional view of chip is black box or simplistic modelSignal Integrity analysis of high speed signalsDetail Model of Chip allow concurrent system-package-die SI&PI analysisImpedance Analysis of entire system level PDN network

6. Chip-Package-System (CPS)1.8V1.2VVRMCHIP 2PackageBoardBoardBoardBoardBoardBoard

7. Chip-Package-System (CPS)1.8V1.2VVRMCHIP 2PackageBoardBoard

8. Chip-Package-System (CPS)1.8V1.2VChip Power Model + Package Extraction+ PCB/Board ExtractionVRMCHIP 2PackageEMI NoisePower IntegrityThermal IntegrityPower Delivery Network ImpedanceCost Control (low cost market and/or high volume)BoardBoard

9. Chip-Package-System (CPS)AC AnalysisDynamic Voltage DropRed: Chip + Pkg analysisGreen: Chip + Pkg+ PCB analysisWith Package ModelWithout Package ModelModels of the Chip, Package and PCB are necessary for an accurate result.

10. Chip-Package-System (CPS)EMI/EMC AnalysisPackage/PCB EMI MapChip EmissionsNecessary to model the noise source (Chip) and propagation medium (Package/PCB)5th harmonic2nd harmonicSSO Timing Analysis

11. Model-Based CPS ConvergenceL MetalR MetalR PkgL PCBR PCBLeaf TxGlobal PDNviewVRMC4 PG BumpOn die DecapOn BoarddecapC MetalC PkgSoC DesignersviewPCB/Pkg RLC, S parameterL MetalR MetalLeaf TxC4 PG BumpOn die DecapC MetalPCB DesignersviewCPMR PkgL PCBR PCBVRMC4 PG BumpOn BoarddecapChip Power ModelC PkgOnly Common reference point

12. Chip Power Model (CPM™) Chip on-die Power Grid RLCModel creation Transistor current/cap/ESR Package/BoardModel Multi-domain, distributed model

13. DC to multi-GHz validity

14. Advanced chip excitation modes

15. Full chip correlationASICVendorsSystem HousesChip PowerModelTwo sides, co-verification

16. Chip Power Model (CPM)CHIP DATALayout(Early to Sign-off)LibraryCHIP ANALYSISDynamic VectorLessDynamic VCDStaticChip Power ModelStatic (Iavg, R)Frequency domain (RLC)Time-domain (I(t), RLC)Modes

17. Chip Power Model (CPM)PCB + PackagePads/bumps (Power & Ground) need to be associated to its correspondingChip PDN RLC Physical model of chip layoutTransistor/cell current /cap/ESR Electrical model of chip layout

18. Chip Power Model (CPM)Each port (or bump) reflects the current flow associated with that port (or bump) reflecting the on-die activityParasitics are associated with every port (or bump)Each port (or bump) are coupled with every other portActive Current SignaturePassive RC Values

19. Detailed Chip Power Model Advantage Detailed Chip Power ModelDetailed Chip Power ModelTraditional DieModelTraditional Die ModelChip Power ModelDesignLayoutLibraryChip CurrentRLC reduction: billions of parasitics to thousands of Spice elements

20. Distributed with full couplingsChip ParasiticsSingle Lumped Model

21. Chip Power Model : Parasitic Model BenefitsTraditional approaches to modeling the chip parasitics:Spreadsheet based

22. Hand-calculated estimates Limited coverage  Pooraccuracy, especially for large, multi-domain designsCPM advantages Accurate broadband response over wide frequency range

23. Captures all chip capacitive effects (PDN, device, signal net)