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How do we break the  Formal Verification Scalability Barrier ? Ziyad Hanna Jasper Design Automation May 4, 2011 May 4, 2011
Jasper Design Automation Gothenburg, Sweden EDA leader of formal technologies in delivering targeted ROI solutions for the design and verification  Mountain View, CA Haifa, Israel Belo Horizonte, Brazil HP
Design and Verification Activities …  Spec development  OS bring up Mask development  Benchmarking Heat  Test planning Reliability Verification  RTL Development  Unit testing Circuit marginality verification  Power estimation  Simulation Coverage Analysis  Noise Analysis Power Verification How to cope with all of this ? Assertion writing Synthesis  Device Driver development  RC estimation and verification  Formal verification Floor Planning  Timing Analysis Protocol Checking Process development  Custom block design  Equivalence Checking  Architecture Verification Library Design  Connectivity verification  Software Development  Emulation Performance Verification  Layout  FPGA Fracture Verification  Full  chip integration Firmware  Post –si Debug & Validation High Level Synthesis
Problem Statement  Verification complexity increases at an exponential rate Costly labor and IT resources Hard to predict the quality and TTM  Existing dynamic verification methods are unable to close the verification gap Logic escapes are still cannot be avoided Post-Silicon validation  Design problem, or Verification problem, or both ?
Formal Technology Comes of Age EDAC Market Statistics Service (MSS) aggregates and reports revenue growth by tool category Formal Property Checking category had 3rd fastest-growing revenue in EDA/IP (latest MSS report Q3’10)
Early Formal Tools Required Formal PhD Users What We’ve Learned About the Market Value Show Deployability Raise Expectations Effort Big EDA Vendors’ Formal Tools  Reduced Effort, Sacrificed Value
Scalability – Customers Perspectives  Handle bigger and more complex designs From small blocks, units, clusters, CPU to systems Coping with exponential design complexity   Solve hard problems in design and verification Spectrum of applications beyond model checking  Handle emerging design styles FF/Latch based designs, async, clock glitches, CDC … Enable project level multiuser/parallel engineering/reuse and collaboration methodologies Scale economically with high utilization of licenses
Scalability - Technology Perspectives  Interactive: users have full control and performing parallel tasks  ,[object Object]
Parallel: multithreading, computer clusters, farms and clouds
Elastic: Dynamic verification tasks, grow and shrink on-the-fly
Programmable: API for creating/expanding capabilities
Collaboration: interoperability and sharing results ,[object Object]
Parallel: multithreading, computer clusters, farms and clouds
Elastic: Dynamic verification tasks, grow and shrink on-the-fly
Programmable: API for creating/expanding capabilities
Collaboration: interoperability and sharing results ,[object Object]
VisualizeTMfor Interactive Debug & Exploration failure_condition Data structure corruption at cycle 16.  Can it then cause to violation interrupt? ,[object Object]
Trace concatenation
Auto-explorationConfigurations stack manager Pushes & pops constraints Modifies netlist on-the-fly
Scalability - Technology Perspectives  Interactive: users have full control and performing parallel tasks  ,[object Object]
Parallel: multithreading, computer clusters, farms and clouds
Elastic: Dynamic verification tasks, grow and shrink on-the-fly
Programmable: API for creating/expanding capabilities

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Track c how do we break - jasper

  • 1. How do we break the Formal Verification Scalability Barrier ? Ziyad Hanna Jasper Design Automation May 4, 2011 May 4, 2011
  • 2. Jasper Design Automation Gothenburg, Sweden EDA leader of formal technologies in delivering targeted ROI solutions for the design and verification Mountain View, CA Haifa, Israel Belo Horizonte, Brazil HP
  • 3. Design and Verification Activities … Spec development OS bring up Mask development Benchmarking Heat Test planning Reliability Verification RTL Development Unit testing Circuit marginality verification Power estimation Simulation Coverage Analysis Noise Analysis Power Verification How to cope with all of this ? Assertion writing Synthesis Device Driver development RC estimation and verification Formal verification Floor Planning Timing Analysis Protocol Checking Process development Custom block design Equivalence Checking Architecture Verification Library Design Connectivity verification Software Development Emulation Performance Verification Layout FPGA Fracture Verification Full chip integration Firmware Post –si Debug & Validation High Level Synthesis
  • 4. Problem Statement Verification complexity increases at an exponential rate Costly labor and IT resources Hard to predict the quality and TTM Existing dynamic verification methods are unable to close the verification gap Logic escapes are still cannot be avoided Post-Silicon validation Design problem, or Verification problem, or both ?
  • 5. Formal Technology Comes of Age EDAC Market Statistics Service (MSS) aggregates and reports revenue growth by tool category Formal Property Checking category had 3rd fastest-growing revenue in EDA/IP (latest MSS report Q3’10)
  • 6. Early Formal Tools Required Formal PhD Users What We’ve Learned About the Market Value Show Deployability Raise Expectations Effort Big EDA Vendors’ Formal Tools Reduced Effort, Sacrificed Value
  • 7. Scalability – Customers Perspectives Handle bigger and more complex designs From small blocks, units, clusters, CPU to systems Coping with exponential design complexity Solve hard problems in design and verification Spectrum of applications beyond model checking Handle emerging design styles FF/Latch based designs, async, clock glitches, CDC … Enable project level multiuser/parallel engineering/reuse and collaboration methodologies Scale economically with high utilization of licenses
  • 8.
  • 9. Parallel: multithreading, computer clusters, farms and clouds
  • 10. Elastic: Dynamic verification tasks, grow and shrink on-the-fly
  • 11. Programmable: API for creating/expanding capabilities
  • 12.
  • 13. Parallel: multithreading, computer clusters, farms and clouds
  • 14. Elastic: Dynamic verification tasks, grow and shrink on-the-fly
  • 15. Programmable: API for creating/expanding capabilities
  • 16.
  • 17.
  • 19. Auto-explorationConfigurations stack manager Pushes & pops constraints Modifies netlist on-the-fly
  • 20.
  • 21. Parallel: multithreading, computer clusters, farms and clouds
  • 22. Elastic: Dynamic verification tasks, grow and shrink on-the-fly
  • 23. Programmable: API for creating/expanding capabilities
  • 24.
  • 25. Managing Proof Capacity – Automatic Abstraction CEX? Model Checking at depth k cycles done No CEX? Automatic Abstraction Learning, Increase k, refinement True? Model Checking done False?
  • 26. Managing Proof Capacity – Interactive Abstraction Design Tunneling – formal analysis guided expansion algorithms Interactive State Space Tunneling Design Abstraction and Proof Accelerators
  • 27. Performance Evolution (on SUN OPENSPARC Design) Phase-1 Phase-2 Phase-3 Emerging hardware gives 2X speedup Parallel Proofs boost the performance by additional 10X Engine technology boost the proofs by additional ~4X
  • 28.
  • 29. Parallel: multithreading, computer clusters, farms and clouds
  • 30. Elastic: Dynamic verification tasks, grow and shrink on-the-fly
  • 31. Programmable: API for creating/expanding capabilities
  • 32.
  • 33. Seamless tracking & reporting✖ P0 P1 P2 P3 P9 P10 P11 ✔ ✔ ✔ ✖ P4 ✖ P5 Throughput ✖ P6 ✔ P7 ✔ P8 ✔ ✔ ✔ ✖ P13 Capacity
  • 34.
  • 35.
  • 36. Parallel: multithreading, computer clusters, farms and clouds
  • 37. Elastic: Dynamic verification tasks, grow and shrink on-the-fly
  • 38. Programmable: API for creating/expanding capabilities
  • 39.
  • 40. Conclusions Scalability is a multi-dimensional goal and requires a holistic approach to achieve it Scalability from user perspective is a key enabler for making formal key technology to deploy With scalability in mind, formal technology has come of age