Fan-Out and Embedded Die: Technologies & Market Trends 2015 Report by Yole Developpement

February © 2015
From Technologies
to Market
Fan-Out and
Embedded Die:
Technologies &
Market Trends
Sample

2
REPORT OUTLINES
• Report scope & definitions • Embedded Die in substrates
o Scope of the report o Motivations and drivers
o Companies cited in this report o Products and technologies
o Glossary • Products available
• Executive summary • Roadmaps
• Advanced packaging growth o Supply chain
• Fan-Out platform • Players and positioning within the supply chain
o Motivations and drivers o Embedded Die Package commercialization status
o Products and technologies o Market forecasts
• Products available o Equipment & materials
• Roadmaps • Challenges related to yield & supply chain
o Supply chain for FOWLP • Cost considerations
• Players and positioning within the supply chain • Conclusions & perspectives
o FOWLP commercialization status • Company presentation
o Market forecasts
o Equipment & materials
• Improvement of materials
• Panel for FOWLP status
©2015 | www.yole.fr | Fan-Out and Embedded Die: Technologies & Market Trends

3
REPORT SCOPE
The main objectives of this report are the following:
o To update the business status of both embedded wafer level package technologies (FOWLP and Embedded Die
Package) markets
o To provide a market forecast for the coming years, and estimate future trends
o To analyze key market drivers, benefits and challenges of embedded wafer level packages by application
o To describe the different existing technologies, their trends and the roadmaps
The FOWLP and Embedded Die Package markets are studied from the following angles
o State-of-the-art technology and trends
o End-user applications and drivers
o Market value
o Industrial supply chain & value chain

4
THE EVOLUTION OF SEMICONDUCTOR PACKAGING
A bridging technology between ICs and PCBs
Packaging fills
the gap in
between ICs
and PCBs
improvement
speeds
Feature sizes CMOS
transistors: 28nm
Feature sizes of PCBs
1970
Through
hole
technology
1980
Surface mount
devices
DevelopmentinCMOSprocessingcapabilities
DevelopmentinPCBprocessingcapabilities
1990
CSPs/BGAs
SiPs
2000
WLCSP
more SiPs
Flip Chip BGA
PoP
2010
3DIC
TSV
Fan-out WLCSP
Cu pillars
Silicon interposers

5
PACKAGING ADDEDVALUE:
More Moore and More than Moore
3D approach
allows to get
all the benefit
from chip
miniaturization
and package
integration
More Moore : miniaturization
130nm 90nm 65nm 45nm 32nm 22nm 14nm 10nm
Analog+
RF
PassivesPowerSensorsEnergy
Sources
Biochips
MoreThanMoore:diversification
SoC
SiP
IPD
RF CMOS
SMOS
Analog
Power
Low Power
CMOS
High Perf.
SOI
Non
Volatile
Memory
GaAS RF
MEMS
…
3D integration is seen today as a
new paradigm for the future of the
semiconductor industry, as it will
enable several more decades of
chip evolution at ever lower cost,
higher performance and smaller-
size features.
…

6
WAFER-LEVEL-PACKAGING MARKET DRIVERS
WLP
•Lower packaging cost
•Lower test cost
 I/Os density
•Lower pitches
•No standard
•Smaller dies
•Higher density of
I/Os
 Integration
•IPD
•SiP
•3D
 Thermal performance
•Lower power consumption
•Higher package density
 Electrical performance
•Smaller Interconnect lines
•Higher frequencies
•Higher ackage speed
•Lower parasitics
 Form-factor
•Smaller thickness
•Lower footprint
• Improve chip-to-board
coupling
• New materials
• Batch processing
• Panel capability
• Lower thickness
• Multiple RDL
• Interconnect
optimization
• Smallest thickness of the
market
• Integration
capability
• Low pitch
capability
 Cost
Numerous
market
drivers lead
to aWLP
solution

7
TWO TYPES OF EMBEDDED WAFER-LEVEL-PACKAGES
• A different approach depending on
substrate type:
• FOWLP is based on a
reconfigured molded wafer
infrastructure
• Embedded die in package is
based on a PCB type of panel
infrastructure
There are
two main
substrate
types for
embedding
technologies

8
FAN-OUT WLP PRINCIPLE
Embedding
in a molding
compound
allow thin
packaging
Pick and place
Wafer level
Molding
Carrier removal / de-bonding
Tape lamination
StandardWLB process
(Passivation, pattern, RDL,
bonding)
Dicing
Source: Infineon
Carrier (Metal)
Carrier with foil and chips
Molding with liquid moldcompound
WLP Fan-Out wafer
After singulation
Reconstituted wafer
after molding

9
FAN-OUT WLP KEY DIFFERENTIATORS
Numerous
advantages
position
FOWLP as a
promising
solution
Simplified supply chain and
manufacturing
infrastructure
No restriction in
bump pitch
No laminate
substrate
required
Shorter
interconnections
Fan-out zone
adaptable to
customer needs
High degree of
package design
freedom
Reliable, miniaturized high
performance package
Smaller footprint and thinner
package than Flip-Chip BGA
Better board level
reliability compared to
WL-CSP
RoHS and REACH
compliant package
Excellent electrical
performance
Lower thermal
resistance compared to
Flip-Chip BGA
Mold Chip

10
FAN-OUT WLP DRIVERS:WHERE IS THE THRESHOLD?
• A lot of products are already
packaged using Fan-in
solution which is cheaper
than Fan-Out
• With die size reduction and
higher pins count
manufacturers will have two
options:
• Reducing ball pitch in
order to have more
connections within the die
surface
• Going Fan-Out and
allowing an easier
redistribution
• Since pitch reduction is very
challenging, Fan-Out
approach is offering a good
opportunity
FOWLP has
a sweet spot
area where
Fan-In
cannot fit
Diesize(mm/side)
Pi n s - c o u n t
Fan-out
Fan-in

11
FAN-OUT POTENTIAL APPLICATIONS
Opportunities for FOWLP in mobile phones
FOWLP has
the potential
to fit in
many
applications
Orange: Devices that can be found in
FOWLP packages today
Discrete passives
Green: Devices that could be found
in the future in FOWLP
Grey: Devices that will likely remain
on WLCSP or flip-chip package or
move to 3DIC

12
FOWLP ACTIVITIES: GLOBAL MAP OF MAIN PLAYERS
FOWLP
catches the
interest of
many
companies

13
FAN-OUT WLP:TECHNICAL CHALLENGES
FOWLP
technical
challenges to
overcome
IC 1 IC 2Mold
Chip-to-mold non-
planarity
Die shift
Reliability
Warpage
Topography

14
TECHNOLOGY ROADMAP FOR FOWLP
Key parameters
Roadmap of
FOWLP
follows the
high
demanding
expectations
from the
market
2013 2014 2015 2016
Line/Space
Package minimum
thickness (with BGA)
Max level of RDL
Minimum die-to-die
distance
Minimum die side size
Minimum mold
clearance distance
Minimum bump pitch
Maximum package
size

15
FOWLP ACTIVITY MARKET FORECAST
A high
growth is
expected
CAGR ~ 10%
Transition phase
Ramp-up with fab-less wireless
IC players and wide FOWLP
infrastructure/supply-chain
$0M
$300M
$600M
$900M
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
FO-WLPrevenues(M$)
FOWLP activity revenues (M$)
Overall evolution since eWLB technology introduction
Yole Developpement ©

16
EMBEDDED DIE PACKAGING PROCESS FLOW
Example with “chip-first – face-up” approach
Principle of
embedded
die package
in substrate
1) Die Bonding
2) Lamination
3) Laser drilling
Adhesive on
copper foil
Pick & place on
copper foil
Relamination
process
Copper plating, imaging and etching
3) Structuring
Source:AT&S

17
EMBEDDED DIE PACKAGE KEY DIFFERENTIATORS
Embedded
Die package
advantages
Good for copy protection
New suppliers Low manufacturing
cots thanks to very
mature products
High potential for
reducing I/Os thanks to
design (wire-bond layout)
High potential for
components
integration
Small footprint thanks to
more space given to surface
components
High mechanical reliability
Improved thermal
performance thanks to
proximity with active
High design flexibility since
chip can be positioned
wherever we want
Reduced parasitics
thanks to short
interconnections
Chip
Laminated PCB

18
EMBEDDED DIE PACKAGING
Technical challenges
Embedded
Die Package
technical
challenges to
overcome
Embedded SiP
Warpage
Yield
Die positionning
Resolution

19
EMBEDDED DIE PACKAGING:A NEW SUPPLY CHAIN
• Supply chain and
responsibilities can be
defined case by case upon
players will of implication
• Embedded die packaging
opens the door for
substrate suppliers to
realize the whole packaging,
assembly and test
themselves  Good
opportunity for substrate
suppliers to create new
business and potential
threat for OSATs market
PCB
manufacturers
can create a
new supply
chain in
semiconductor
industry
Wafer thinning
Embedded Die
Customization
Wafer sort / Die
preparation
PCB Core
Fabrication
Component
placement
Multi-layer build up
fabrication
Embedded Die PCB
sort
Solder paste
print
Component
placement and
reflow
Product level
assembly and
test
1) Die Customization (IDM orWafer Level Technology Provider)
2)Embedded Die Substrate Fabrication (PCB manufacturer)
3) Product level assembly and final testing

20
TECHNOLOGY ROADMAP FOR EMBEDDED DIE
Key parameters
• Today, Embedded Die Packaging
technology only targets low-cost,
low I/O pin-count applications
(mainly power and analog ICs)
• However, to enter the digital
space and more complex SiP
module realization, embedded die
technologies are set to evolve
Roadmap of
Embedded
Die package
shows the
targets to
achieve
before being
fully
competitive
in mobile
market
2013 2014 2015 2016
Line/Space
Package minimum
thickness
Chip layer stacking
Pad Pitch on die
Chip thickness
(min-max)

21
EMBEDDED DIE ACTIVITY MARKET FORECAST
Embedded
Die package
market is
still a niche
$0M
$100M
$200M
$300M
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
Embedded die package revenues forecast (M$)
Overall evolution since technology introduction

23©2015 | www.yole.fr | Name of the report
MEMS &
Sensors
LED/OLED
Compound
Semi.
Imaging Photonics
MedTech
Manufacturing
Advanced
Packaging
PV
Power
Electronics
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24
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• Events
www.i-Micronews.com

25
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26
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Korea
40% of our business is in
EU countries
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27
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analysis,
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Suppliers: material,
equipment, OSAT,
foundries…
Financial investors,
R&D centers

28
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Email: laferriere@yole.fr
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