Download as PDF, PPTX
![6/23/2014 © 2014 ANSYS, Inc. 14
Interconnect Melt-down
# Signal bus CD check
BEGIN_ESD_RULE
NAME signal_bump2diode_CD_check
TYPE CD
ZAP_CURRENT 1.3A # ~2kV HBM zap
B2C_NET_GROUP SIGNAL
SHOTGUN_MODE 1
END_ESD_RULE
#Power Bus CD Check
BEGIN_ESD_RULE
NAME Pwr_Bus_CD_check
TYPE CD
ZAP_CURRENT 1.3A #~2kV HBM Zap
C2C_NET_GROUP POWER GROUND
FROM_CLAMP_TYPE D1 D2
TO_CLAMP_TYPE PWRCLMP
END_ESD_RULE
#Power2Ground CD check
BEGIN_ESD_RULE
NAME PWR2GND_CD_check
TYPE BUMP2BUMP
ZAP_CURRENT 1.3A # ~2kV HBM Zap
TERMINAL_NET_GROUP POWER GROUND
CLAMP_TYPE PWRCLMP
SHORT_BUMP_IN_NET_GROUP POWER GROUND
END_ESD_RULE
IO Pad
Pad
VCC
VSS
Define Interconnect CD limits
Mx = x mA/um
My = y mA/um
Mz = z mA/um
RDL = r mA/um
D1
D2
Power
Clamps
# Clamp IV Model
BEGIN_CLAMP_IV
NAME <I-V_clamp_name>
Ron <Ron+> [<Ron->]
VT1 <VT1+> [<VT1->]
VH <VH+> [<VH->]
ROFF <Roff+> [<Roff->]
END_CLAMP_IV
Signal Bus CD checks Power/Ground Bus CD checks
Power2Ground CD checks
How can PathFinder help ?](https://image.slidesharecdn.com/ansyspathfinderesd-141016123717-conversion-gate01/75/How-to-Identify-and-Prevent-ESD-Failures-using-PathFinder-14-2048.jpg)
Uploaded byAnsys
How to Identify and Prevent ESD Failures using PathFinder
The document discusses electrostatic discharge (ESD) issues in the context of integrated circuits and how to identify and prevent them using Pathfinder design tools. It highlights the importance of ESD integrity analysis, common ESD failure types, and design strategies to mitigate ESD risks. Pathfinder is presented as a comprehensive solution for performing layout connectivity checks, resistance checks, and dynamic checks to ensure robust ESD design compliance.
In this document
Powered by AI
Overview of the presentation focused on identifying and preventing ESD issues using PathFinder.
Definitions of ESD, its mechanisms, and the various types of electrostatic discharge events.
Introduction to PathFinder tools for ESD integrity, including layout technology, ESD rules, and checks for clamping models.
Identification of common ESD failure types in SoCs and their impacts on silicon success. Key statistics on ESD issues.
Details on interconnect melt-downs and common root causes for failures leading to device breakdown.
Discussion on cross-domain ESD issues, including high resistance scenarios and incorrect ESD discharge paths.
Core technologies of PathFinder, including its usability, accuracy, and benefits in ESD clamp design.
Summary of PathFinder's capabilities in ESD integrity analysis and its integration into reference design flows.
More Related Content
Similar to How to Identify and Prevent ESD Failures using PathFinder
How to Identify and Prevent ESD Failures using PathFinder
- 1. 6/23/2014 © 2014ANSYS, Inc. 1 How to Identify and Prevent ESD Issues Using PathFinder™ Design Automation Conference 2014
- 2. 6/23/2014 © 2014ANSYS, Inc. 2 Electrostatic Discharge “A transfer of charge between two bodies at different electrostatic potentials, either through contact or via an ionized ambient discharge (a spark).” What is ESD? I/O buffers ESD Clamps ESD Clamps IO Pad I/O pin Drain/Source junction or gate-oxide damage Metal/via melt-down High current event causing latent or catastrophic failures to IC Intended path Unintended path
- 3. 6/23/2014 © 2014ANSYS, Inc. 3 Human Body/Machine Model(HBM/MM) + + + Charged Device Model(CDM) Discharge currents for different types of ESD events Source: http://www.esda.org/documents/IndustryCouncilWhitePaper2.pdf What is ESD?
- 4. 6/23/2014 © 2014ANSYS, Inc. 4 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB
- 5. 6/23/2014 © 2014ANSYS, Inc. 5 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB R-Extraction
- 6. 6/23/2014 © 2014ANSYS, Inc. 6 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB Isolated bumps Disconnected clamps Missing pin2pin ESD path X Layout Connectivity Checks Layout Connectivity Checks
- 7. 6/23/2014 © 2014ANSYS, Inc. 7 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB Resistance Checks R? R? R? R? R? R? Any Point Layout Connectivity Checks Resistance Checks
- 8. 6/23/2014 © 2014ANSYS, Inc. 8 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB Isolated bumps Disconnected clamps Missing pin2pin ESD path X LayouRtR eCs-oEisnxtnatenrccateicv Ctitihyoe Cnchksecks R? R? R? R? R? R? Any Point Interconnect Failure Checks Metal/via bottlenecks Current crowding on diode fingers Layout Connectivity Checks Resistance Checks Interconnect Failure Checks
- 9. 6/23/2014 © 2014ANSYS, Inc. 9 PathFinder™: SoC and IP ESD Integrity Layout (DEF/GDS) Technology Spice Netlist/ Clamp Models ESD rules PathFinder gnd vdd vddA gndA gndB vddB Isolated bumps Disconnected clamps Missing pin2pin ESD path X LayouRtR eCs-oEisnxtnatenrccateicv Ctitihyoe Cnchksecks R? R? R? R? R? R? Any Point Interconnect Failure Checks Metal/via bottlenecks Current crowding on diode fingers Layout Connectivity Checks Resistance Checks Interconnect Failure Checks Dynamic Checks Monitor device stress Dynamic Checks Root-cause Analysis IP/Full-chip Capacity Early Stage to Sign-off
- 10. 6/23/2014 © 2014ANSYS, Inc. 10 Common ESD Issues in SoCs Device breakdown ESD Device 40% BEOL 30% ESD Network 10% Cross Domain 15% misc 5% ESD Failure Types ESD failures impact first silicon success Interconnect melt-down Cross-domain ESD issues
- 11. 6/23/2014 © 2014ANSYS, Inc. 11 Inefficient or missing clamps Device Breakdown Source: Cao et al., ESD design challenges and strategies in deeply-scaled integrated circuits, PhD dissertation, Stanford Univ, 2010. ESD Design window from 130 nm to 32 nm technology vss sig D1 D2 vcc Functional devices V>V(break-down) High ESD bus resistance +ve Zap Power2 Ground Zap -ve Zap Why is it more important now? What are the common causes for such failures?
- 12. 6/23/2014 © 2014ANSYS, Inc. 12 vss sig D1 D2 vcc Functional devices Device Breakdown Signal Bus R checks # Signal bus R check BEGIN_ESD_RULE NAME sigbump2diode_Rcheck TYPE BUMP2CLAMP ARC_R 0.1 TERMINAL_NET_GROUP SIGNAL CLAMP_TYPE1 D1 D2 END_ESD_RULE Power Bus Resistance check #Power Bus R Check BEGIN_ESD_RULE NAME Pwr_Bus_R_check TYPE CLAMP2CLAMP ARC_R 0.1 TERMINAL_NET_GROUP POWER GROUND FROM_CLAMP_TYPE D1 D2 TO_CLAMP_TYPE PWRCLMP END_ESD_RULE Power2Ground R check #Power2Ground R check BEGIN_ESD_RULE NAME PWR2GND_R_check TYPE BUMP2BUMP LOOP_R 5 PARALLEL_R 1 TERMINAL_NET_GROUP POWER GROUND CLAMP_TYPE PWRCLMP SHORT_BUMP_IN_NET_GROUP POWER GROUND END_ESD_RULE How can PathFinder help ?
- 13. 6/23/2014 © 2014ANSYS, Inc. 13 Positive Zap Negative Zap IO Pad Pad VCC VSS Mx My Mz RD L D1 D2 Clamps Current crowding on ESD device Insufficient via-cuts/ ineffective clamps Insufficient wire width on ESD pathways Interconnect Melt-down Why is it more important now? What are the common causes for such failures?
- 14. 6/23/2014 © 2014ANSYS, Inc. 14 Interconnect Melt-down # Signal bus CD check BEGIN_ESD_RULE NAME signal_bump2diode_CD_check TYPE CD ZAP_CURRENT 1.3A # ~2kV HBM zap B2C_NET_GROUP SIGNAL SHOTGUN_MODE 1 END_ESD_RULE #Power Bus CD Check BEGIN_ESD_RULE NAME Pwr_Bus_CD_check TYPE CD ZAP_CURRENT 1.3A #~2kV HBM Zap C2C_NET_GROUP POWER GROUND FROM_CLAMP_TYPE D1 D2 TO_CLAMP_TYPE PWRCLMP END_ESD_RULE #Power2Ground CD check BEGIN_ESD_RULE NAME PWR2GND_CD_check TYPE BUMP2BUMP ZAP_CURRENT 1.3A # ~2kV HBM Zap TERMINAL_NET_GROUP POWER GROUND CLAMP_TYPE PWRCLMP SHORT_BUMP_IN_NET_GROUP POWER GROUND END_ESD_RULE IO Pad Pad VCC VSS Define Interconnect CD limits Mx = x mA/um My = y mA/um Mz = z mA/um RDL = r mA/um D1 D2 Power Clamps # Clamp IV Model BEGIN_CLAMP_IV NAME <I-V_clamp_name> Ron <Ron+> [<Ron->] VT1 <VT1+> [<VT1->] VH <VH+> [<VH->] ROFF <Roff+> [<Roff->] END_CLAMP_IV Signal Bus CD checks Power/Ground Bus CD checks Power2Ground CD checks How can PathFinder help ?
- 15. 6/23/2014 © 2014ANSYS, Inc. 15 Cross-domain ESD Issues High Ground bus R Insufficient/unconnected bridge diodes Unintentional ESD discharge path VSS1 VDD1 Power Clamp VSS2 VDD2 Power Clamp Bridge diodes RVSS Bridge diodes GPIO GPIO GPIO Analog IO GPIO Analog/RF (AVDD) GPU (VDDG) Memory/Cache (VDDM) High Speed I/O CPU CORE (VDDC) Intentional ESD discharge path Why is it more important now? What are the common causes for such failures?
- 16. 6/23/2014 © 2014ANSYS, Inc. 16 Bus Resistance Checks Clamp connectivity checks VSS1 VDD1 Power Clamp VSS2 VDD2 Power Clamp Bridge diodes RVSS Bridge diodes Cross-domain ESD Issues # Signal bus CD check BEGIN_ESD_RULE NAME VSS_bus_R_Check TYPE C2C FROM_CLAMP_TYPE PWRCLMP TO_CLAMP_TYPE B2B_DIODE ARC_R 0.5 END_ESD_RULE #Cross-domain CD Check BEGIN_ESD_RULE NAME Cross_domain_CD_Check TYPE CD ZAP_CURRENT 1.3A #~2kV HBM Zap NET_PAIR VDD1 VSS2 END_ESD_RULE How can PathFinder help ? # Clamp connectivity Checks in PathFinder TCL> perform clampcheck # pin2pin connectivity –allNetConn # report disconnected net pairs -rptDisconn Cross-domain CD checks
- 17. 6/23/2014 © 2014ANSYS, Inc. 17 PathFinder Core Technologies & Benefits Capacity Full-chip capacity with package impact Accuracy ESD snap-back device modeling Current crowding on diode fingers IV curve support Usability Rich GUI for debug and optimization Root-cause the bottleneck in ESD bus
- 18. 6/23/2014 © 2014ANSYS, Inc. 18 ESD-aware SoC Design Flow Analysis driven clamp placement vdd gnd ESD Clamp ESD Clamp ESD Clamp X IO ring ESD bus planning Floor plan Resistance and current density limit sign-off GPIO GPIO GPIO Analog IO GPIO Analog/ RF (AVDD) GPU (VDDG) Memory/Cache (VDDM) High Speed I/O CPU CORE (VDDC) Final sign-off IO Ring IP level IO Pad level
- 19. 6/23/2014 © 2014ANSYS, Inc. 19 Summary • Full chip-level ESD integrity analysis solution • PathFinder coverage: – Layout connectivity checks – Resistance checks – Interconnect failure checks – Dynamic CDM checks for IPs • Part of ESDA reference flow and TSMC reference flow