Zero- Defect Methodology for automotive and other key applications

1. • May 9, 2016
Zero- Defect Methodology
for Automotive and Other Key
Applications
March, 2016 Authors:
Ray Hou (GUC Automotive BD)
Jason Lin (GUC Operations Manager)
Igor Elkanovich (Verisense CTO)
Lewis Chu (GUC Marketing Director) - presenter

2. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
• Public company, traded in Taipei Stock Exchange
• Partially owned by TSMC
• Services : ASIC, Chip design service, IPs
• Worldwide offices: US, China, Europe, Japan and Korea
• Verisense, GUC Israeli partner, offers leading ASIC & FPGA design services
GUC Corporation Information
0
10
20
30
2010 2011 2012 2013 2014 2015
16nm
20nm
28nm
40nm
65nm
90nm
0.13um
0.18um above
GUC Tape Outs per year
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3. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Automotive IC Reliability Requirements
• Reliability: < 5 FIT
– FIT (failure in time) is defined as a failure rate of 1 per billion hours
– 1 FIT is equivalent to having an MTBF of 1 billion hours
• Defects < 5-10 DPPM
– DPPM: defective parts per million ppm
• High max. ambient temperature
Min. Max.
0 - 40 °C 150 °C
1 - 40 °C 125 °C
2 - 40 °C 105 °C
3 - 40 °C 85 °C
Grade
Operation Ambient Temperature
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4. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
GUC Comprehensive Reliability Management
• Reliability control at all stages thought the flow
DFR DFM DFT
Reliability Manufacturing Testing
Risk/
Robustness
checking
ZD testing
method
Outlier
program
Tightened
Control
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5. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Failures Distribution in Time
Early failures Random failures Wear-out failuresFailures category
Main cause Defect Process Baseline Product design
Mechanism •High Test coverage
•Outlier screening
•3-temp. testing
•Visual spec. tighten
•Burn-in testing
•SPC/Cpk control
•Equipment monitor
•Reliability monitor
•Continuous improvement
•Circuit design robustness
•Design for Manufacturing
•Package/material robustness
•Drift analysis for spec margin
Screen
weak chip
Reduce process variation
Enhance
design robustness
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EM void in a Cu line
under a via
Brittle failure (Si fracture)
due to temperature cycling

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• May 9, 2016
DFT Approach for Automotive Product
DFT Item Automotive product
Digital • Stack at faults coverage > 99%
• Transition faults coverage > 85%
• Pseudo Stuck-at IDDQ faults coverage > 80%
• Small Delay (Optional)
• Bridge (Optional)
SRAM • March 68N
• Checkerboard & Inverse background data
• Physical mapping
ROM • ReadOnly 2N
Analog • Functionality and Spec check
• Additional signal to increase analog testability
internal reference voltage monitor
analog bias tuning setting to touch performance boundary
• Analog test modes built in
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7. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Silicon Process Variation
• Variation measured by Process Monitor (PM)
7,000
9,200
11,600
6,800
8,800
11,000
6500
7500
8500
9500
10500
11500
12500
13500
14500
15500
16500
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200 5600 6000 6400 6800
Count
Chip Sorting
PM Silicon vs. SPICE Correlation
BUFD4-7T35P140-HVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-SVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-HVT
(SS_0.9V_25C)
BUFD4-7T35P140-HVT
(TT_0.9V_25C)
BUFD4-7T35P140-HVT
(FF_0.9V_25C)
BUFD4-7T35P140-SVT
(SS_0.9V_25C)
BUFD4-7T35P140-SVT
(TT_0.9V_25C)
BUFD4-7T35P140-SVT
(FF_0.9V_25C)
7,000
9,200
11,600
6,800
8,800
11,000
6500
7000
7500
8000
8500
9000
9500
10000
10500
11000
11500
12000
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200 5600 6000 6400 6800
Count
Chip Sorting
PM Silicon vs. SPICE Correlation
BUFD4-7T35P140-HVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-SVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-HVT
(SS_0.9V_25C)
BUFD4-7T35P140-HVT
(TT_0.9V_25C)
BUFD4-7T35P140-HVT
(FF_0.9V_25C)
BUFD4-7T35P140-SVT
(SS_0.9V_25C)
BUFD4-7T35P140-SVT
(TT_0.9V_25C)
BUFD4-7T35P140-SVT
(FF_0.9V_25C)
7,000
9,200
11,600
6,800
8,800
11,000
6500
7000
7500
8000
8500
9000
9500
10000
10500
11000
11500
12000
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200 5600 6000 6400 6800
Count
Chip Sorting
PM Silicon vs. SPICE Correlation
BUFD4-7T35P140-HVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-SVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-HVT
(SS_0.9V_25C)
BUFD4-7T35P140-HVT
(TT_0.9V_25C)
BUFD4-7T35P140-HVT
(FF_0.9V_25C)
BUFD4-7T35P140-SVT
(SS_0.9V_25C)
BUFD4-7T35P140-SVT
(TT_0.9V_25C)
BUFD4-7T35P140-SVT
(FF_0.9V_25C)
7,000
9,200
11,600
6,800
8,800
11,000
6500
7000
7500
8000
8500
9000
9500
10000
10500
11000
11500
12000
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200 5600 6000 6400 6800
Count
Chip Sorting
PM Silicon vs. SPICE Correlation
BUFD4-7T35P140-HVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-SVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-HVT
(SS_0.9V_25C)
BUFD4-7T35P140-HVT
(TT_0.9V_25C)
BUFD4-7T35P140-HVT
(FF_0.9V_25C)
BUFD4-7T35P140-SVT
(SS_0.9V_25C)
BUFD4-7T35P140-SVT
(TT_0.9V_25C)
BUFD4-7T35P140-SVT
(FF_0.9V_25C)
7,000
9,200
11,600
6,800
8,800
11,000
6500
7000
7500
8000
8500
9000
9500
10000
10500
11000
11500
12000
0 400 800 1200 1600 2000 2400 2800 3200 3600 4000 4400 4800 5200 5600 6000 6400 6800
Count
Chip Sorting
PM Silicon vs. SPICE Correlation
BUFD4-7T35P140-HVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-SVT
(Silicon_0.9V_25C)
BUFD4-7T35P140-HVT
(SS_0.9V_25C)
BUFD4-7T35P140-HVT
(TT_0.9V_25C)
BUFD4-7T35P140-HVT
(FF_0.9V_25C)
BUFD4-7T35P140-SVT
(SS_0.9V_25C)
BUFD4-7T35P140-SVT
(TT_0.9V_25C)
BUFD4-7T35P140-SVT
(FF_0.9V_25C)
Slow PM
Fast PM
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8. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
VMK: Variation Measurement Kit
• PMs inserted on regular grid
• PMs represent all used VTs, channel
lengths, gates types
• Interface protocols: APB, JTAG, I2C
• Automatic test pattern generation
• Spice simulated in all corners for
reference
• Statistic is collected through all wafers
production
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9. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Soft Error Rate and Solution
• Soft errors are induced by external radiation (e.g. alpha
particles)
• Solutions
– Design: filp-flop
– Memory: ECC
– Package: low-alpha materials
P9

10. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
DFM: Extended Physical Rules Check
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11. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
DFM: Tightening Electromigration Rules
• EM rating for automotive:
• Additional Poly/High-R/Metal-gate R current density rule
Figure : Poly EM requirement for regular products
Figure : Rating factor for automotive products
Figure : Rating factor for regular products
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12. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Potential Defect Identification
• Production test tightening for Outliers segregation
Upper/Lower Spec Limits
Tightening Tightening
P12

13. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Outlier Program at Production Test
• ELFR (Early Life Failure Rate)
– more than 2000 samples or production ramp-up, with HTOL method to
identify the early failure mode/rate for CIP
• Dynamic Voltage Stress (DVS) testing to screen weaker parts
– 1.2x ~ 1.8x stress voltage during testing
– Failure Analysis of failed parts to seek the process improvement or spec
refining
• Statistical Yield/Bin Limit (SBL/SYL) in testing
– to separate the maverick parts for risk assessment
– Maverick mechanism (yield limit by step/machine) on assembly process
• Wafer selection rule with specific WAT risk parameters
– to separate marginal/risk wafer for assessment/tightened screening
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14. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Summary
• Reliability is handled throughout all stages
– DFT, physical implementation and production
• GUC flow is based on volume production experience -
allows minimal defects and very low FIT
– Silicon-proven comprehensive DFT and testing methodology
– Overcome challenging of 28nm/16nm DFM rules
– Proprietary Solution for Process Variation Monitoring
– Intelligent Mechanisms for Testing: ELFR, DVS testing, SBL/SYL
and Maverick mechanism
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15. GUC Property – Security CCopyright © 2016 GUC Uncompromising Performance
• May 9, 2016
Thank you !
www.guc-asic.com
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