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Xavier van Ruymbeke, App. Engineer, Arteris
- 1. ○ May 9, 2016 Enhancing Data Center Flash Storage Endurance Using Network-on-Chip Interconnect IP ChipEx2016, Israel Xavier van Ruymbeke Application Engineering Manager, Arteris xavier.van-ruymbeke@arteris.com@arteris.com Copyright © 2016 Arteris
- 2. ○ May 9, 2016 Arteris Snapshot Copyright © 2016 Arteris Founded 2003; Headquarters in Silicon Valley Global PresenceInterconnect IP Leadership Large&GrowingCustomerBase Customersshipped ~600M unitsin 2014 Connected byArteris Ecosystem Shanghai TokyoCampbell Seoul TaipeiBangalore Paris Israel Strong R&D and Support R&D Engineering 48%App Engineering 29% Sales 14% G&A 9% Marketing 2% Top Semis use Arteris Publicly Disclosed Customers Toshiba In Leading Systems Over 100 NoC-based SoCs in production 1 6 9 13 20 41 52 58 67 76 80 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2 NoCSolution 2006 Main Interconnect 1st Generation FlexNoC 2010 Main Interconnect 2nd Generation FlexWay 2010 Subsystem Interconnect FlexLLI 2011 Interchip Link FlexPSI 2013 Interchip Link FlexNoC Resilience 2014 For Mission Critical Electronics FlexNoC Physical 2015 Physical Awareness w/FlexNoC V3
- 3. ○ May 9, 2016 Need for on-chip data protection emerging in data center flash controllers Copyright © 2016 Arteris Data Center SSD ○ Huge bandwidth – Logical Block Addressing (LBA) and Cascading Slices to access 10+ TB ○ Low latency – NVMe replaces AHCI ○ Updated standards: JEDEC JESD218B (Endurance), SNIA Solid State Storage (SSS) Performance Test Specification (PTS) ○ Result: More complexity, more gates… • But on-chip errors reduce SSD endurance and reliability More complex systems = Data protection required! 3
- 4. ○ May 9, 2016 Data center SSD controller complexity requires larger, more complex interconnect Copyright © 2016 Arteris Data RAM Subsystem (Buffers, Parity, Sequence) DMA Engine FlexNoC® Top Level Interconnect Peripheral Subsystem . SPI I2C UART GPIO ROM On-chip interconnect IP DRAM Subsystem DDR3/4 DDR3/4 PHY PHY Memory Scheduler DRAM Controller XOR Engine ECC Flash Control CPU Subsystem R5/7 R5/7 R5/7 R5/7 R5/7 R5/7 Cache LLPP NVMe PCIe Subsystem . . Interconnect Timer Debug PCIePHY Data RAM Data RAM Data RAM Data RAM SRAM RAID Flash 4
- 5. ○ May 9, 2016 Controller complexity and size increase probability of digital logic failures Copyright © 2016 Arteris Particle hitting the gate and changing its output Wire broken: Un-driven input Destroyed Gate: Stuck at Data center flash controllers must adapt to inevitable errors ○ Digital integrated circuits can fail in many ways: • Transient electrical problems – glitches on power supply, clock supply • Soft errors – Alpha particles, cosmic rays, thermal neutrons • Physical damage – shorts or open wires, destroyed logic gates ○ Designing for data protection requires covering all of them • Not just Soft Errors 5
- 6. ○ May 9, 2016 Why implement data protection in the SoC interconnect? Implementing protection in the interconnect is better because… 1. Complexity – SW is much more effort to develop and maintain than using certifiable HW IP 2. Quality – HW IP is pre-tested and can be pre-certified while future SW quality is a risk 3. Control – Semi vendors can set a baseline of data protection features that must be implemented, so they are at less risk of poor quality software developed without their knowledge, input or feedback. Copyright © 2016 Arteris Implementing data protection in hardware is less risky than implementing solely in software! 6
- 7. ○ May 9, 2016 Protecting on-chip interconnect data makes the SoC more reliable Each feature is optional and configurable: Parity on packet header in transport • Cover faults on packet content in transport layer Packet Consistency checkers • Capture bad routing or partial packet deletion/duplication in transport User defined ECC/parity on payload • Cover all faults affecting payload • Can be input/output from socket or generate/terminate Initiator timeout • Capture single packet deletion or Initiator misbehavior Target timeout • Capture slave misbehavior ARM Cortex® R5/R7 support Register parity bit • Cover Faults on NoC configuration register Copyright © 2016 Arteris NoC= ? = ? = ? = ? = ? = ? = ? = ? NIUNIUNIUNIU NIUNIUNIUNIU Master IP Master IP Master IP Slave IP Slave IP Slave IP Master IP Slave IP NIUNIUNIU NIUNIUNIU NIU NIU SafetyController Fault cc cc cc cc cc cc cc cc ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P 7
- 8. ○ May 9, 2016 Data protection advanced features Unit duplication and checkers • Cover faults in NIU, firewall, power disconnect elements able to transform the access content Safety Controller • Fault reporting and BIST checking for duplicated unit checkers Copyright © 2016 Arteris NoC= ? = ? = ? = ? = ? = ? = ? = ? NIUNIUNIUNIU NIUNIUNIUNIU Master IP Master IP Master IP Slave IP Slave IP Slave IP Master IP Slave IP NIUNIUNIU NIUNIUNIU NIU NIU SafetyController Fault cc cc cc cc cc cc cc cc ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P ECC/P These are effective for unique use cases, but are more costly in power consumption and die area. 8
- 9. ○ May 9, 2016 Protect SoC data with end-to-end data protection ○ Core Interface Protection supports • User-defined protection schemes ○ To ensure safe connection from core to NoC, core-side protection logic • Detects and corrects errors upon transaction requests • Generates protection semantics to IP core upon transaction responses ○ Packet transport protection logic Detects and corrects transport-level errors Copyright © 2016 Arteris Protected IP Core Resilient NoC Core-side Error Detection & Correction Protected Core Interface Transport Parity/ECC Transport Parity/ECC Core-side Protection Generation Request Response 9
- 10. ○ May 9, 2016 Simplest, lowest cost option is parity protection ○ Inserted and terminated by NIUs and units that modify packets ○ Packet Header protection • One parity bit per group of header bits • EVEN parity • Group size determined by “TimingImpact” parameter Low: 8 bits (more number of resilience bits in header) Medium: 16 bits High: 32 bits (less number of resilience bits in header) ○ Packet payload protection • One parity bit per data byte (including byte enable) Copyright © 2016 Arteris Group N N Groups Group N-1Group N-2Group 2Group 1Group 0 0/1 0/1 0/1 0/1 0/1 0/1 Header Width = N Groups even parity bit Calculation one bit per Group … 10
- 11. ○ May 9, 2016 Protect ARM Cortex-R5/R7 transactions with built-in interconnect ECC support ○ Control • All command redundancy is generated/terminated • 32/64 bits AXI socket support • ODD/EVEN parity support ○ Data • Cortex ECC terminated/generated in the Initiator NIU • Optional byte-level ECC generation inside NoC ○ Option to do network interface unit (NIU) duplication NIUinitiator Cortex NIUinitiator S2G G2T ECC checks NIUTarget G2T S2G ECC checks transport Cortex ECC terminated, Byte ECC generation Byte ECC terminated, custom ECC generation Copyright © 2016 Arteris 11
- 12. ○ May 9, 2016 Implement user-defined payload ECC to protect other data ○ Per-socket, user-defined number of DataInfo bits per bytes ○ NoC wide, transport level user-defined number of DataInfo bits per bytes ○ Conversion to/from socket DataInfo semantics from/to Transport DataInfo semantics • Done inside the NIUs at generic level • If socket and transport DataInfo are identical (same number of bits per bytes, same semantic): can be just copied transparently • If socket and transport DataInfo are different (different number of bits per bytes, and/or different semantic): conversion logic need to be provided by the user and will be located in NIU placeholders ○ Socket Protocols supporting ECC: • AXI – with narrow bursts split to single word transactions • AHB – with AHB target using Byte Enables • OCP – with targets providing correct ECC on SData/SDataInfo for write responses NIUinitiator NIUinitiator S2G G2T Socket <> Transport NIUTarget G2T S2G Transport <> Socket transport Socket defined DataInfo bits per byte Socket defined DataInfo bits per bytes NoC transport number of bits per payload byte Conversion placeholder Conversion placeholder Copyright © 2016 Arteris 12
- 13. ○ May 9, 2016 Duplicate parts of the interconnect to achieve higher reliability ○ Generic and specific NIUs are duplicated • Includes reorder buffers, scheduler – no restrictions ○ Units modifying packets are duplicated • Target power disconnect, Firewall ○ Duplicate logic delayed by one or two cycle • Using separate clock input and reset input • Avoid common faults due to power glitches and clock branch defects ○ A Checker is used to compare outputs • Checker has separate clock gater ○ Differences in output are reported as faults ○ Some unit configurations cannot be duplicated • NIUs with multiple generic interfaces (LLI, OCP MT) • Target power disconnect with asynchronous crossing • These units can be present in the system but won’t be duplicated Reference Unit Functional Unit Delay Inputs Checker Outputs ClkClk’ FaultBIST Control Copyright © 2016 Arteris 13
- 14. ○ May 9, 2016 Need checkers, fault reporting and BIST to ensure data protection Copyright © 2016 Arteris • Sequence testing patterns through delay registers • Report issues in the comparison logic (stuck-at faults typically) ○ One Checker per duplicated unit ○ In Mission mode: Compares Unit outputs • Early Unit outputs delayed by one cycle • Early/Late Unit regular outputs bit-compared • Logic fault outputs from both units compared to 0 • Redundant report of packet and/or NIU check faults ○ In BIST mode: Checks comparison logic) Safety Controller Checker Checker Clk Clk’ Fault BIST control BIST control Mission Interrupt Latent Interrupt Clk …. 14
- 15. ○ May 9, 2016 Protect only the parts of controller that affect system reliability the most Accelerators Peripheral Data-Protected NoC I/OMem Ctrl Peripheral DRAM ROM/Flash CPUs Peripheral I/O ECC - Core SafetyController =? =? =? =? =? Fault cccccc cc cc cc Consistency checker Equality checker Fault NoC Without Protection Firewall (SW programmable) =? Copyright © 2016 Arteris 15
- 16. ○ May 9, 2016 Data center and SSD flash controllers require on-chip data protection ○ Interconnect size as a percentage of die size, and complexity, increase as the number of functional IP blocks increases ○ Data traveling on the interconnect is at risk of corruption ○ Technologies exist today to protect data traveling over the on-chip interconnect, which increases system reliability and endurance Copyright © 2016 Arteris Meeting data center storage reliability goals requires on-chip interconnect data protection 16
- 17. ○ May 9, 2016 Copyright © 2016 Arteris 17
Editor's Notes
- JEDEC new standard: SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD JESD218B Mar 2016
- If core is unprotected, can still use transport protection logic to ensure protection within the NoC Word based ECC is converted to bite based ECC in FlexNoC in the NIUs