This document provides an agenda for a presentation on signal integrity that includes: defining signal integrity and why it is important; methods for signal integrity analysis including analytical, measurement, and simulation; modeling transmission lines and reflections; analyzing power planes and power integrity; and characteristics needed for successful signal and power integrity analysis and system design. Examples are provided throughout to illustrate key concepts.

1. 13 th .Apr. 2010 In-myoung Song Tel : 82)10-9034-8480 E-mail : imsong91@gmail.com Introduction of Signal Integrity

2. Agenda Before Start What is the Signal Integrity ? Why SI ? Signal Integrity Analysis Method Why Wave Equation ? Reflection Example Transmission Line Power Plane Analysis Electrical Design Setup Process Characterization, Modeling and Simulation for System Design System Design for Signal Integrity Verification Measurement System Set-up What you need for SI Analysis ? What you need for PI Analysis ? Think from example ISI Transmission Line Modeling Different Edge rate w/ Same Frequency Common Clock System Power Integrity SSN Return path Power Z vs. SSN Further Study Reference Book

3. Before Start Where is the signal path according to V(t) ? + V(t)

4. Before Start Knee Frequency (Cutoff Frequency)? In electronics, cutoff frequency ( f c ) is the frequency either above which or below which the power output of a circuit, such as a line, amplifier, or electronic filter is 1/2 the power of the passband, and since voltage V 2 is proportional to power P , V is 1/sqrt(2) of the V in the passband. This happens to be close to −3 decibels, and the cutoff frequency is frequently referred to as the −3 dB point. Also called the knee frequency, due to a frequency response curve's physical appearance.

5. Before Start RC Single-pole pulse

6. What is the Signal Integrity ? Artwork/Layout Artwork Or Layout Same schematic? Same performance?

7. What is the Signal Integrity ? Hidden schematics ? What is the ideal wire? No delay : means the start and end point of wire are equipotential. There are not any hidden schematics. But in real world, this is a dream. In the real world. All metals have some delay, even if very small. If the wavelength is short according to that delay, there are potential difference at every point in the wire. So that we can feel the electric and magnetic field. Ohm’s law is not accepted. Use Transmission line theory.

8. Why SI ? Signal integrity and why you should care about it In the past, interconnect delays and ringing were ignored because there was plenty of time for reflections to settle out. These day, system clock rates have steadily increased, this means signals have much faster edge rates and minimal settling time. Reflections can be caused by many factors, including capacitive loading, impedance mismatching, stubs and improper terminations. Crosstalk results from the coupling between traces and is a distinct problem in higher-density boards with faster edge rates. Subnanosecond edges are composed of high frequency harmonics that can easily couple into an adjacent interconnect causing crosstalk.

9. Signal Integrity Analysis Method Analytical Method Very Cheap Very Fast Not acceptable to all cases Only used for the estimation of the simulation result Measurement Method Huge Expensive Very Slow Many measurement Techniques are needed All debugging techniques are not available Simulation Method Somewhat Expensive Middle speed Many kinds of CAD tool are needed Single line w/ Ideal Plane Multiple line w/ Ideal Plane Multiple line w/ Non-Ideal Plane

10. Why wave equation ? Maxwell Equation Telegrapher Equation

11. Reflection Example T r = 0. 1ns/0.6V, Rout = 25 Ohms

12. Reflection Example

13. Reflection Example When R2=25 Ohms? For more exact value of R2, refer to Loadline Analysis

14. Reflection Example

15. Transmission line The wave velocity on PCB is slower than on AIR There are many rule of thumb Trace Delay : TD Rising/Falling Time : Tr/Tf Treat the trace as Transmission line when (5~10) X TD > Tr/Tf Don’t forget using EFFECTIVE DIELECTRIC CONSTANT Micro-Strip (PSR or Non-PSR) Strip (CCL or P.P) Dielectric Constant is a function of frequency and dependant on manufacturing even if same material.

16. Transmission line Calculation of Signal Velocity in Dielectrics If Length = 10mm, TD is about 70 ps. If (5~10) X TD > Tr/Tf meets that is [Tr/Tf < (350 ps~700 ps)] This is a Transmission line, so we should do a Simulation

17. Power Plane Analysis Power Ground Plane Resonance Simultaneous Switching Noise DC Drop

18. Electrical Design Setup Process Characterization Measurement of electrical/mechanical parameter. Using VNA/TDR/TDT. Need De-embedding technique. It takes a lot of time to characterize. Modeling Good characterization makes good modeling correlation between CAD tool and measurement waveform. Difficult to choose an appropriate CAD tool . Lumped ? Or Distributed ? Simulation Performance estimation such as Signal Quality, Power Plane resonance, Plane Impedance Profile, SSN, Crosstalk, and etc.

19. Characterization, Modeling, and Simulation for System Design * Ref : Gigalab Hanyang Univ. Parasitic RLC Power Integrity SSN (Delta-I Noise) Resonance Signal Integrity Crosstalk Timing Waveform Distortion Transmission Line Parameters ( RLCG, Propagation Constant, Characteristic Impedance, etc ) < General SOP Package System > < Circuit Model for Design > Circuit Model Parameter Characterization Simulation Simulation Modeling !! Characterization !!

20. “ Electrical Design” means “Performance Estimation” based on Accurate Characterization, Modeling, and Simulation !! System Design for Signal Integrity Verification * Ref : Gigalab Hanyang Univ.

21. Impedance Analyzer RF Probe Station TDR/TDT VNA Network Analyzer - High-Freq. S-Parameter - Freq.-Variant Parameters - Signal Transient Char. Impedance Analyzer - Low-Freq. Impedance - Capacitance - Long Line Inductance TDR/TDT - Time-Domain Reflection - Time-Domain Trans. - Discontinuity Charac. Measurements System Set-Up * Ref : Gigalab Hanyang Univ.

22. What you need for SI analysis ? Modeling data Active IC component : IBIS/Spice Model Passive component : Equivalent Circuit Model Trace (copper) Transmission line model Time domain : T-element, W-element, U-element, FWS … Frequency domain : S-parameter Lumped line model Rule of thumb : electrical length < λ /10 R, L, G, C Electrical parameter : Dielectric Constant, Loss tangent, Conductivity Mechanical parameter : Physical cross-section’s dimension CAD Tool 2D, 2.5D, 3D field solver and IBIS or Spice Simulator Datasheet Find the DC/AC Spec. and calculate DC/AC Margin

23. What you need for PI analysis ? Modeling data Active IC component : IBIS/Spice Model Decoupling Capacitor : Equivalent Circuit Model Plane pair Modeling (copper) : CAD Tool Electrical parameter : Dielectric Constant, Loss tangent, Conductivity Mechanical parameter : Physical cross-section’s dimension CAD Tool 2D, 2.5D, 3D field solver and IBIS or Spice Simulator Datasheet or Spec. Find the DC/AC Spec. and calculate DC/AC Margin Maximum dynamic current Maximum voltage ripple Tolerance

24. Think from example (Star) Case1 Case2 Vt Rt TL0 DRV TL1 RCV A TL2 RCV B TL3 RCV C TL4 RCV D TL5 Item TL0 TL1 TL2 TL3 TL4 TL5 Vt Rt Z 0 ( Ω ) 51 50 50 50 50 50 0.75 16.66 Length (mm) 470 51 51 51 51 15 Item TL0 TL1 TL2 TL3 TL4 TL5 Vt Rt Z 0 ( Ω ) 51 50 50 50 50 50 0.75 16.66 Length (mm) 470 79 79 79 79 15

25. Think from example (Star) 10 pulse of 1 and 0 (Frequency : 400Mhz) Blue? Low Overshoot?

26. Think from example (Star) 1024 PRBS (Frequency : 400Mhz)

27. Think from example (H-Tree) Item TL0 TL1, TL2 TL3~TL6 Z 0 ( Ω ) 51 70 110 Length (mm) 470 30 26 TL0 DRV TL3 RCV A TL4 RCV B TL5 RCV C TL6 RCV D TL1 TL2

28. Think from example (H-Tree) 1024 PRBS (Frequency : 400Mhz)

29. ISI Inter-Symbol Interference : Pattern dependent skew 30 bits ‘0’ and ‘1’,vs, only 16 th bit is ‘1’

30. Transmission Line Modeling Distributed W-element Rs : the skin effect matrix Gd : power loss due to the rotation of dipoles under the alternating field Field Solver Model S Model FWS (Full Wave Spice) Model *SYSTEM_NAME : cond_sys * * Half Space, AIR * ------------------------------------ Z = 3.045200e-001 * AIR H = 3.000000e-001 * ------------------------------------ Z = 4.520000e-003 * al2o3 H = 4.500000e-003 * ------------------------------------ Z = 2.000000e-005 * //// Bottom Ground Plane /////////// * ------------------------------------ Z = 0 * L(H/m), C(F/m), Ro(Ohm/m), Go(S/m), Rs(Ohm/(m*sqrt(Hz)), Gd(S/(m*Hz)) .MODEL cond_sys W MODELTYPE=RLGC, N=1 + Lo = 1.081618e-006 + Co = 5.764322e-011 + Ro = 2.625003e+002 + Go = 0.000000e+000 + Rs = 1.226710e-002 + Gd = 2.414554e-014

31. Transmission Line Modeling Lumped Line Modeling T Line model vs L-C cascade network

32. Transmission Line Modeling

33. Transmission Line Modeling

34. Different Edge rate w/ Same Frequency

35. Different Edge rate w/ Same Frequency

36. Common Clock System Clock Driver Timing Spec. T co_clkA , T co_clkB , Jitter Controller Timing Spec. T co_data_min , T co_data_max , T data_skew Memory Timing Spec. T su , T hd Interconnect Timing Spec. T flt_clkA , T flt_clkB , T flt_data Clock Driver clkA T co_clkA clkB Clk_in T flt_clkA T flt_clkB T co_clkB D c T co_data Controller clkC clkM D m T flt_data Memory T co_min T co_max clkC D c T su T hd clkM D m

37. Common Clock System T flt_data < T cycle – T co_data_max – T su + T flt_clkA – T flt_clkB + (T co_clkA – T co_clkB ) – Jitter T flt_data > T hd – T co_data_min + T flt_clkA – T flt_clkB + (T co_clkA – T co_clkB ) Watch out! Flight time measurement Corner Case Fast, Slow Measurement Level Threshold level ( V meas or V il /V ih ) Flight Time Compensation Receiver – Test Load Crosstalk Budget Even mode or Odd mode Power Noise Budget ETC

38. Power Integrity Target Impedance How can we measure it ? Dynamic Current Circuit Simulation On DDR2/DDR3 : IDD7 – IDD2 Voltage Ripple Tolerance Datasheet : Supply voltage Typical, Min, Max Which frequency ? Knee frequency : 0.5/T r or 0.35/T r Decoupling Capacitor libraries Murata, TDK, SEMCO, AVX, and ETC Resonance and Anti-resonance Series Resonance / Parallel Resonance IDD7 : The maximum current drawn by each chip IDD2 : The minimum current is associated with the idle current http://www.jedec.org/download/search/JESD79-2B.pdf

39. Power Integrity 10 x 10 2 pF = 1 nF 12 x 10 2 pF = 1.2 nF 10 x 10 3 pF = 10 nF 10 x 10 4 pF = 100 nF 10 x 10 5 pF = 1 uF 22 x 10 5 pF = 2.2 uF

40. Power Integrity (Example) DDR3 Module(4 Devices) IDD7 – IDD2 = 250 mA – 50mA = 200mA from Datasheet Voltage Ripple = (Max/Min) – Typ = (1.575/1.425)-1.5 = ±0.075V Z target = 0.075/(4*200m) = 93.75 m Ω Rising Time : 230 psec from IBIS Model Falling Time : 196 psec from IBIS Model F knee = 0.35/min(t r ,t f ) = 1.79 GHz

41. Power Integrity (Example) M O R E C A P.

42. SSN (Example) SSN : Simultaneous Switching Noise Dynamic Current Fast Transition of State between ‘0’ and ‘1’ Power Delivery Network (PDN) Inductance

43. SSN (Example) 6 Bits Switching 3 Bits Switching 6 Bits Switching w/ 2 Dec_Cap

44. Return Path (Example) Return path discontinuity Plane has no gap Plane has a gap S21 Port1 Port2 Port14 Port15 Plane has no gap Plane has a gap S1514

45. Return Path (Example) Re-routing to avoid Impedance Mismatching Plane has no gap Plane has a gap S21 Rerouting

46. Power Z vs. SSN(Example) A1 – Blue A2 - Red

47. Power Z vs. SSN(Example) 400 Mhz (PRBS) : Power

48. Power Z vs. SSN(Example) 400 Mhz (PRBS) : Signal

49. Power Z vs. SSN(Example) 1000 Mhz (PRBS) : Power

50. Power Z vs. SSN(Example) 1000 Mhz (PRBS) : Signal

51. Power Z vs. SSN(Example) It is difficult to forecast the result of SSN based on Power Plane Impedance Profile. Because there are many frequency components at digital signal, the Power Plane Impedance can’t tell many things to us. To find the best design of Power Plane, we had better check the SSN result after optimizing Power Plane Impedance Profile.

52. Further Study IBIS Model validation Noise Budget Determination Timing Budget Determination Crosstalk of offset timing De-embedding Technique IC + Package + Board Co-simulation Harmonics when the duty cycle is not 50% Even/Odd harmonics Eye Opening Measurement by In-house Software

53. Reference Book Signal Integrity – Simplified by Eric Bogatin Signal Integrity Issues and Printed Circuit Board Design by Douglas Brooks Timing Analysis and Simulation for Signal Integrity Engineers by Greg Edlund High Speed Digital Design by Howard Johnson and Martin Graham Digital Signal Integrity : Modeling and Simulation with Interconnects and Packages by Brian Young Power Integrity Modeling and Design for Semiconductor and Systems by Madhavan Saminathan and Ege Engin High Speed Signal Propagation : Advanced Black Magic by Howard Johnson Advanced Signal Integrity for High-speed Digital Designs by Stephan H. Hall and Howard L. Heck High-Speed Circuit Board Signal Integrity by Stephen, C. Thierauf Jitter, Noise, and Signal Integrity at High-speed by Mike Peng Li Handbook of Digital Techniques for High-speed Design by tom Granberg Semiconductor Modeling by Roy g. Leventhal, ….. High-Speed Digital System Design by Stephen H. Hall, Garrett W. Hall, and James A. McCall

54. Q & A *** Thank you *** http://www.signalintegrity.co.kr Theory : Inductance, Capacitance, Loss, Energy, Digital Design, System operation, Spice, IBIS, Field Solving, 2D Modeling, 3D Modeling, 2.5D Modeling, CAD Tool, Maxwell Equation, Wave Velocity, TEM/TE/TM Mode, Quasi-static, Resonance, Coupling, Radiation, Common mode noise, Differential mode noise, Differential Signal, DDR, Common clock, Source-Sync. clock, Dielectric, Skin depth, Fringing effect, Artwork, PCB, Connector, Cable, Return path, FFT, Knee frequency, Network parameter, TDR/TDT, VNA, Transmission Line, Characteristic Impedance, Jitter, Skew, ISI, SSN, BER, Return path, Proximity effect, Threshold level, Dynamic current, Timing, Capacitive Coupling, Inductive Coupling, and etc