This document provides a user manual for the Π-FP software, which simulates power integrity in integrated circuit floorplans. It describes how Π-FP models on-chip power grids, distributed current sources, transmission lines, and capacitance. Key aspects include simulating symmetric two-layer on-chip grids, distributing current sources and capacitance uniformly across blocks, and solving equations to calculate voltage changes along transmission line elements. Example simulations demonstrate how Π-FP can analyze power noise within chips and across multiple connected chips, packages, and boards.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Comparator holds a dominant place in fast ADC circuit for the conversion of analog to digital signal. In this modernized digital world every utilization circuits requires an ADC’s with low power to consumption. This in turn reflects in the design of comparators during the design process of the fast ADC circuits, scope is due to the higher number of comparator usage. As the technologies are scaling down, the number of transistor per unit area increases, so that the sub threshold leakage current increases which leads to power consumption in any circuit. This sources the project idea to design a comparator. It is presumed during the design that, it consumes low power in its double tail configuration which when replaces an inverter circuit in latch stage of the double tail comparator by a sleepy inverter. This presumption is validated through the analysis of the simulation results. The power consumption of the designed proposed double tail comparator is 30μw when compared to 35 μw in the conventional type. 2-bit flash ADC circuit is designed and analyzed under two different configurations of the double tail comparator. From the results, it is clear that the power consumption of the ADC circuit designed with proposed sleepy inverter based double tail comparator is observed to be 45mw.
Hysteresis SVM for Coupled Inductor Z Source Diode Clamped 3-Level Inverter B...IAES-IJPEDS
Due to its advantages such as it can defeat problems such as leakage current
and insertion of DC in the grid and provides low stress on power devices,
Diode-clamped three-level inverter (DCTLI) is habitually used in
transformerless photovoltaic (PV) connected to grid network. But it still has
a problem of shoot-through which dwells in its legs, so its operation not
reliable. Z source network is employed to permit operation without shoot
through risk and improve its reliability. Coupled inductors are replaced the
line transformers in to attain lower cost, reduced size, and improved its
reliability and efficiency. Coupled inductor which avoids leakage current
problem and losses. It employs coupled inductor z source diode clamped
three level inverter (CI-Z-DC-TLI) to boost the voltage and further progress
the consistency of the proposed system by avoiding the shoot through the
problem. The proposed system assures that common-mode voltage
and shoot-through risk is avoided. Moreover, controlling DC-TLI with
Hysteresis SVM algorithm which improves output voltage and current
control. Simulation and experimental results of this proposed system were
analyzed using MATLAB environment and FPGA hardware.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Comparator holds a dominant place in fast ADC circuit for the conversion of analog to digital signal. In this modernized digital world every utilization circuits requires an ADC’s with low power to consumption. This in turn reflects in the design of comparators during the design process of the fast ADC circuits, scope is due to the higher number of comparator usage. As the technologies are scaling down, the number of transistor per unit area increases, so that the sub threshold leakage current increases which leads to power consumption in any circuit. This sources the project idea to design a comparator. It is presumed during the design that, it consumes low power in its double tail configuration which when replaces an inverter circuit in latch stage of the double tail comparator by a sleepy inverter. This presumption is validated through the analysis of the simulation results. The power consumption of the designed proposed double tail comparator is 30μw when compared to 35 μw in the conventional type. 2-bit flash ADC circuit is designed and analyzed under two different configurations of the double tail comparator. From the results, it is clear that the power consumption of the ADC circuit designed with proposed sleepy inverter based double tail comparator is observed to be 45mw.
Hysteresis SVM for Coupled Inductor Z Source Diode Clamped 3-Level Inverter B...IAES-IJPEDS
Due to its advantages such as it can defeat problems such as leakage current
and insertion of DC in the grid and provides low stress on power devices,
Diode-clamped three-level inverter (DCTLI) is habitually used in
transformerless photovoltaic (PV) connected to grid network. But it still has
a problem of shoot-through which dwells in its legs, so its operation not
reliable. Z source network is employed to permit operation without shoot
through risk and improve its reliability. Coupled inductors are replaced the
line transformers in to attain lower cost, reduced size, and improved its
reliability and efficiency. Coupled inductor which avoids leakage current
problem and losses. It employs coupled inductor z source diode clamped
three level inverter (CI-Z-DC-TLI) to boost the voltage and further progress
the consistency of the proposed system by avoiding the shoot through the
problem. The proposed system assures that common-mode voltage
and shoot-through risk is avoided. Moreover, controlling DC-TLI with
Hysteresis SVM algorithm which improves output voltage and current
control. Simulation and experimental results of this proposed system were
analyzed using MATLAB environment and FPGA hardware.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
A 60 GHz CMOS Power Amplifier for Wireless CommunicationsIJECEIAES
This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dBm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm 2 .
A Plasma Tweeter is an audio device which uses a pair of electrodes as a source of sound. It has a clear reproduction and Omni directional radiation pattern. A plasma tweeter has a better frequency response than a conventional speaker and does not involve any moving part (diaphragm) and thus has less reverberation and no wear and tear. Plasma tweeters invented earlier were very expensive. This paper presents a plasma audio system which is making the regular audio system more efficient because of the use of the latest plasma tweeter. Here the objective is to create a low cost and more efficient version of the most speakers invented till now with the complete audio system.
Five Level Hybrid Cascaded Multilevel Inverter Harmonic Reduced in PWM Switch...ijsrd.com
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as a inverter. This paper describes a harmonics reduced in a hybrid cascaded multilevel inverter circuit with pulse width modulation (PWM) scheme. These scheme pulse width modulations in modified method are uses reduce switching device. These methods are a conventional inverter and hybrid inverter combine form. This topology used the combined form of a new five level hybrid cascaded multilevel inverter. The multilevel carrier based pulse width modulation methods are used in this topology five level output voltage wave forms is shown in FFT window MATLABE/SIMULINK is used to simulate the inverter circuit operation and control signals.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired
Low Power SI Class E Power Amplifier and Rf Switch for Health Careieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research(IJCER) is an intentional online Journal in English monthly publishing journal. This Journal publish original research work that contributes significantly to further the scientific knowledge in engineering and Technology.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
A 60 GHz CMOS Power Amplifier for Wireless CommunicationsIJECEIAES
This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dBm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm 2 .
A Plasma Tweeter is an audio device which uses a pair of electrodes as a source of sound. It has a clear reproduction and Omni directional radiation pattern. A plasma tweeter has a better frequency response than a conventional speaker and does not involve any moving part (diaphragm) and thus has less reverberation and no wear and tear. Plasma tweeters invented earlier were very expensive. This paper presents a plasma audio system which is making the regular audio system more efficient because of the use of the latest plasma tweeter. Here the objective is to create a low cost and more efficient version of the most speakers invented till now with the complete audio system.
Five Level Hybrid Cascaded Multilevel Inverter Harmonic Reduced in PWM Switch...ijsrd.com
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as a inverter. This paper describes a harmonics reduced in a hybrid cascaded multilevel inverter circuit with pulse width modulation (PWM) scheme. These scheme pulse width modulations in modified method are uses reduce switching device. These methods are a conventional inverter and hybrid inverter combine form. This topology used the combined form of a new five level hybrid cascaded multilevel inverter. The multilevel carrier based pulse width modulation methods are used in this topology five level output voltage wave forms is shown in FFT window MATLABE/SIMULINK is used to simulate the inverter circuit operation and control signals.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and
RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can
transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the
specification requirements of the desired
Low Power SI Class E Power Amplifier and Rf Switch for Health Careieijjournal1
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software. And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate goal for such application is to reach high performance and low cost, and between high performance and low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
A Novel Configuration of A Microstrip Power Amplifier based on GaAs-FET for I...IJECEIAES
Power Amplifiers (PA) are very indispensable components in the design of numerous types of communication transmitters employed in microwave technology. The methodology is exemplified through the design of a 2.45GHz microwave power Amplifier (PA) for the industrial, scientific and medical (ISM) applications using microstrip technology. The main design target is to get a maximum power gain while simultaneously achieving a maximum output power through presenting the optimum impedance which is characteristically carried out per adding a matching circuit between the source and the input of the power amplifier and between the load and the output of the power amplifier. A "T" matching technique is used at the input and the output sides of transistor for assure in band desired that this circuit without reflections and to obtain a maximum power gain. The proposed power amplifier for microwave ISM applications is designed, simulated and optimized by employing Advanced Design System (ADS) software by Agilent. The PA shows good performances in terms of return loss, output power, power gain and stability; the circuit has an input return loss of -38dB and an output return loss of -33.5dB. The 1-dB compression point is 8.69dBm and power gain of the PA is 19.4dBm. The Rollet's Stability measure B1 and the stability factor K of the amplifier is greater than 0 and 1 respectively, which shows that the circuit is unconditionally stable. The total chip size of the PA is 73.5× 36 mm 2 .
This paper presents the design and development of an integrated wireless power transfer and data communication system. The power and data transfer share a common inductive link that consists of two identical Helical coils placed on both sides of a carbon composite barrier. Power and data are transferred simultaneously through a 5-mm thick carbon composite barrier without any physical penetration or contact. Power transfer measurements show that the system can deliver 9.7 AC power to the receiving coil with a power transfer efficiency of 36% through the carbon composite barrier. The system achieves a bidirectional half-duplex data communication with the data rate of unit 1.2kbit/s.
PROJECT DESCRIPTION
DOWNLOAD
The main objective of this project is to develop a device for wireless power transfer. The concept of wireless power transfer was realized by Nikolas tesla. Wireless power transfer can make a remarkable change in the field of the electrical engineering which eliminates the use conventional copper cables and current carrying wires.
Based on this concept, the project is developed to transfer power within a small range. This project can be used for charging batteries those are physically not possible to be connected electrically such as pace makers (An electronic device that works in place of a defective heart valve) implanted in the body that runs on a battery.
The patient is required to be operated every year to replace the battery. This project is designed to charge a rechargeable battery wirelessly for the purpose. Since charging of the battery is not possible to be demonstrated, we are providing a DC fan that runs through wireless power.
This project is built upon using an electronic circuit which converts AC 230V 50Hz to AC 12V, High frequency. The output is fed to a tuned coil forming as primary of an air core transformer. The secondary coil develops a voltage of HF 12volt.
Thus the transfer of power is done by the primary(transmitter) to the secondary that is separated with a considerable distance(say 3cm). Therefore the transfer could be seen as the primary transmits and the secondary receives the power to run load.
Moreover this technique can be used in number of applications, like to charge a mobile phone, iPod, laptop battery, propeller clock wirelessly. And also this kind of charging provides a far lower risk of electrical shock as it would be galvanically isolated.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation IJECEIAES
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 , and a subthreshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation Yayah Zakaria
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for
the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 and a subthreshold slope
of 0.44V/dec. Sentaurus TCAD simulations is the tool which
offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Design and Fabrication of S-Band MIC Power Amplifierijcisjournal
In this paper, we demonstrate an approach to design FET (pHEMT) based amplifier. The FET is from
Berex Inc.The design is carried out using the measured S-parameter data of the FET.ADS is used as design
tool for the design. A single-stage power amplifier demonstrated 13dB output gain from 3GHz-4GHz .The
saturated output power of 1W and the power added efficiency (PAE) up to 43%.The amplifier is fabricated
on a selective device GaAs power pHEMT process in MIC (Microwave Integrated Circuit) Technology.
MICs are realized using one or more different forms of transmission lines, all characterized by their ability
to be printed on a dielectric substrate.Active and passive components such as transistors/FET, thin or thick
film chip capacitors and resistors are attached
Abstract:
This paper reports on the design of an ultra wideband power amplifier using 0.25um GaN- HEMT Technology device obtained from the Triquint Semiconductor. There is huge interest in transistors based on Gallium Nitride in recent years due to its high breakdown voltage and its capability to operate in High frequency applications. The load pull analysis is carried out to obtain both the required source and load impedances. The
power amplifier with over 10W output power and 42% power added efficiency in the frequency range of 3-5GHz is presented in this paper. The PA is designed using a computer aided design tool called Advanced System Design (ADS).ADS provide two different simulation opportunities. These are referred as schematic simulation and
electromagnetic simulation called Momentum. Schematic Simulations are performed on the proposed PA in this paper.
Keywords:- GaN-HEMT Technology, Load pull analysis, Advanced system design(ADS)
Implementation of pull up pull-down network for energy optimization in full a...IJARIIT
Nowadays the requirements of energy optimized low power circuits in higher-end applications such as
communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power
circuits but the static power dissipation need to improve such kind of circuits. The conventional topology has been
implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an
unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the
static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC
180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to
reduce the static power dissipation in full adder is used to improve the operating speed of each individual.
Development of Wireless Power Transfer using Capacitive Method for Mouse Char...IJPEDS-IAES
Wireless power transfer (WPT) is a non-contact power transfer within a
distance. With the advantage of not-contact concept, WPT enhances the
flexibility movement of the devices. Basically, there are three types of the
WPT which are inductive power transfer (IPT), capacitive power transfer
(CPT) and acoustic power transfer (APT). Among these, capacitive power
transfer (CPT) has the advantages of confining electric field between coupled
plates, metal penetration ability and also the simplicity in circuit topologies.
Therefore, we focus on the capacitive method in this paper. To be specific,
this paper aims to develop a wireless mouse charging system using capacitive
based method. This method enables wireless power transmission from mouse
pad to a wireless mouse. Hence, no battery requires to power up the mouse.
In this paper, a high efficiency Class-E converter is described in details to
convert the DC source to AC and the compensation circuit of resonant tank is
also proposed at the transmitter side in order to improve the efficiency. In the
end, a prototype is developed to prove the developed method. The
performances analysis of the developed prototype is discussed and the future
recommendation of this technique is also presented.
4. Contents
Chapter 1
Introduction to Π-FP 5
Chapter 2
Tutorial 12
Chapter 3
Netlist and parameters 17
# comment 18
Global on-chip grid definition 19
On-chip current sources 20
On-chip capacitance 21
Transmission lines 22
Connection node 23
Ideal cap 24
.TRAN 25
Accuracy parameter 26
.PLOT 23
.PRINTNODE 27
Chapter 4
Graphical output using GNUplot 28
Chapter 5
Invocation and Misc. 34
5. Chapter 1
Introduction to Π-FP
Increased functionality, power density and lower supply voltages place increasing
demands on the power distribution networks of current and future systems containing
large scale integrated circuits. Careful power planning is necessary to reduce power
noise related problems such as timing errors, increased stress in thin gate oxides and
circuit failure. Π-FP is a fast, system level power integrity aware floor planner. It
calculates resistive and inductive voltage changes in on-chip and system level power
grids as a function of grid parameters, time dependent current sources, on and off chip
capacitance. By separating the power net into a global net (two layer symmetric on-
chip and external t-lines) where most of the energy is stored in the magnetic field and
dissipated as heat, and a local net (everything else) where almost all of the energy is
stored in the electric field (de-cap), the problem can simplified to the point where
simulation run times can be reduced by many orders of magnitude.
Figure 1.1 shows the main components in a system level power network designed
using Π-FP . A key component is the on-chip global power distribution grid. This is a
two layer symmetric grid constructed using an array of closely spaced transmission
line pairs. The wires in each power/ground pair are placed at or near the minimum
design space to minimise inductance and maximise capacitance in the global grid. The
designer connects all active and inactive (de-cap) circuits to this grid using an array of
short vertical wires (vias). If enough of these connections are made then all resistive
and inductive voltage drops in the vertical direction are small enough to ignore (the
typical distance to all other wiring layers in the IC is no more than a few microns).
Figure 1.1. Components in a system level power network
6. Figure 1.2 Symmetric connections to the on-chip power grid.
This also ensures that all voltage drops in horizontal wires in all other layers are small
enough to ignore. Under these conditions a significant portion of on-chip voltage
drops and increases are caused by horizontal current flow in the global two layer grid.
Π-FP is a multi-chip simulation tool. Any number of connected IC’s, transmission
lines and floor plan grids can be simulated. In high speed systems the interactions
between multiple IC’s, package and board level components often dominate power
noise characteristics. Large capacity, system level, dynamic power noise simulations
are now possible using Π-FP and symmetric transmission line power grid designs.
Figure 1.2 illustrates the importance of symmetry in high-speed power network
designs. Connecting the current source at point A rather than point B ensures that
voltage and current waves are equal in magnitude and have opposite signs in supply
and return nets. Equal and opposite currents in closely spaced transmission line pairs
have the advantage of minimising unwanted magnetic coupling between the power
supply and other networks. This symmetry also means that it is not necessary to
calculate power noise on both rails. We can simulate one rail only using a single
uncoupled partial differential equation as shown in figure 1.3.
In Π-FP current supplied to active devices in the chip is modelled using a distributed
current source. The user supplies a single current profile for each circuit block (e.g.
obtained from a transistor or gate level simulation). The “block” could represent the
current sourced by a single transistor or gate but this level of detail is usually not
necessary for power grid analysis. Worst case power noise occurs when
6
7. Figure 1.3. A short section of power grid wire showing the distributed capacitance and current source
large numbers of closely spaced gates switch simultaneously or circuit blocks are
switched on and off (e.g. for power saving).
The current source is distributed uniformly across the block area. This approximation
is valid for a block which is well connected, i.e. it has many (symmetric) tap points
uniformly distributed across the block. The user also supplies a value of decoupling
capacitance for each block. This capacitance is also distributed uniformly across the
block area.
Dividing each transmission line pair into short elements the voltage change across
each element is given by:
dt
dI
LdxIR
w
dx
dV s
(1.1)
dt
dV
CdxdxIdI 0 (1.2)
where dx is the length of the element, w is the wire width, Rs is the sheet resistance, L
is the inductance per unit length of the wire, I0 is current per unit length and C is
capacitance per unit length. Efficient algorithms are used to solve these equations for
all on and off chip transmission line pairs.
7
8. Figure 1.4 Simple Π-FP result for a single IC and ideal voltage sources.
Figure 1.4 shows Π-FP results for a single IC with ideal voltage sources at the chip
boundary. This type of simulation can be used to get a quick estimate for on-chip grid
dimensions and decoupling capacitance before running a complete system level
simulation. The IC is 4x4mm in size. Each transmission line pair in the two layer
global on-chip grid has 10um wide, 20mOhm/sq wires and each pair is spaced
periodically at 80um. The inductance per unit length of each transmission line pair is
10nH/cm and the IC has a default de-cap per unit area of 5nF/cm2
. This default cap
can be overridden at any location on the chip if required. Both inductance and
resistance are frequency dependent between 1 and 10GHz so a number of simulation
runs with different Rs and L may be needed to find the worst case power noise.
On and off chip decoupling capacitance are important parameters in any high speed
power noise simulations. This can be obtained using an extraction tool or estimated
from the number of transistors/gates and the wire density within a specified region. In
a more realistic example a number blocks of varying size/cap would be defined in
different regions of the IC to study the effect of on-chip de-cap on noise level and
distribution. Note that this capacitance is the total capacitance between power and
ground nets within the defined region. It includes all parasitics and any de-cap added
intentionally by the designer. A simple linear ramp is defined for a single active
current source in a small region of the IC. All other circuits are assumed to switched
off. Note that inductance dominates voltage drop and ground bounce at high
frequency (dI/dt). The voltage wave front propagates out from the current source at a
velocity given by:
AsLC
1
where s is the periodic distance between transmission line pairs in the on-chip grid, L
is inductance per unit length and CA is the capacitance per unit area in the region
8
9. surrounding the source. These results also show clearly the effect of minimising
inductance by reducing the space between power and ground wires in each
transmission line pair. This is not necessary at low frequency where, as the graph
shows, we get a frequency independent IR drop and ground bounce.
Figure 1.5 shows a result using a more realistic gate switching profile. This plot is
output by the on-chip field solver and shows the maximum and minimum supply
voltage change (delta[Vdd-Gnd]) across the chip surface. As the current ramps down
the energy stored in the magnetic field surrounding on-chip power grid wires is
returned to the grid causing an increase in supply voltage. This energy is, of course,
available to power active circuits during subsequent clock cycles but it is not always
available at the place and time you need it! Supply bounce (Vdd up, Gnd down) can
cause damage to thin dielectrics, particularly if it is already close to its specified
maximum value (e.g. for high speed operation). It also contributes to timing variations
etc. Supply bounce can also be caused by resonance in the on-chip grid, package and
elsewhere. All of these effects can be studied using Π-FP .
Figure 1.5. Power noise at t=212ps showing voltage wave propagation across a 4x4mm IC. The supply
voltage dropped by a maximum of 62mV and increased by a maximum of 58mV during this
simulation.
9
10. In these simple examples any energy which is not dissipated as heat in the on-chip
grid is reflected from the ideal voltage sources at the chip boundary. When the IC is
connected to the package and board level power network the results can be very
different. These long transmission lines have much greater inductance and can give
rise to powerful system level transients when blocks are switched in and out during
normal IC operation. The system illustrated in figure 1.6. includes a package grid and
5 long board level connections to the power supply. The average current consumption
of all active current sources in this simulation is 1.43A. A simple static analysis using
this current distributed uniformly across the chip surface gives 29.5mV maximum IR
drop. Figure 1.7. shows what happens when all the current sources shown are clocked
at 2.5GHz at time t=0. It takes approximately 300 clock cycles for this system level
transient to die out.
Figure 1.6. Example using a package grid and board level connections.
10
11. Figure 1.7. System level transient at the node indicated caused by the simultaneous switch on of many
on-chip current sources.
Clearly measures have to taken to suppress these transients or prevent them from
disrupting on-chip power supplies. Ideal or non-ideal decoupling capacitors can be
added to the off-chip transmission line network in Π-FP, if required.
11
12. Chapter 2
Tutorial
Figure 2.1. Multi-chip simulation
Π-FP is a multi-chip floor planning simulation tool. Any number of connected IC’s,
transmission lines and power supplies can be simulated. The starting point for any
power noise analysis is the dynamic current sources connected to each on-chip grid.
Figure 2.2 shows an example of the time varying current profiles used to model gate
switching currents within a defined area of an IC. In Π-FP this model is implemented
using the following statement in the netlist:
Ichip1 0.04 0.03 0.02 0.013 profile1.txt 40
In this statement the name “chip1” is the name of the IC containing this current
source. The next four parameters are the location and dimensions of the source and
“profile1.txt” is a file containing a piecewise linear representation of the profile. The
final parameter is the number of times this profile is repeated during the simulation.
For example, a simple linear ramp could be implemented using the following two
lines in a separate text file:
0.0 0.0
100e-12 0.0100
The profile can be used for multiple sources if required. In this example the current
ramps to 100mA in 100ps. The block dimensions could be as small as a single gate
but this level of detail is usually not necessary since worst case power noise occurs
when large numbers of gates switch simultaneously within localised areas of the chip.
12
13. Figure 2.2. Dynamic current sources
Each current source is attached to an on-chip global power distribution grid. The grid
is implemented using the following statement in the netlist:
Gchip1 0.4 0.4 0.0010 0.0080 0.020 10e-9 20e-9
The IC is 4x4mm in size. Each transmission line pair in the global two layer
symmetric grid has 10um wide, 20mOhm/sq wires and each pair is spaced
periodically at 80um. The inductance per unit length of each transmission line pair is
10nH/cm and the default capacitance per unit area is 20nH/cm2
. This default de-cap
can be overridden at any location on the chip surface using the following statement:
Cchip1 0 0 0.2 0.2 2e-9
In this simple example 2nF is distributed uniformly across a 2x2mm area of the chip
surface. In a more realistic example a number blocks of varying size/cap would be
defined in different regions of the IC to study the effect of on-chip de-cap on noise
level and distribution. Note that this capacitance is the total capacitance between
power and ground nets within the defined region. It includes parasitics from all layers
and any de-cap added intentionally by the designer.
So far no connections to the package, board or power supply have been added but we
can run the simulation with just these three statements. In this case the tool adds ideal
voltage sources to the on-chip grid boundary. Results of simulations using a linear
13
14. ramp for the current profile are shown in fig.1.4, chapter. 1 and a result using a 200ps
current pulse is shown in fig.1.5, chapter 1. The wave velocity across a low resistance
grid can be obtained from the equation for a lossless transmission line.
2
2
2
2
1
dx
Vd
LCdt
Vd
(2.1)
where L is inductance per unit length and C is capacitance per unit length.
Substituting the wave
)( kxtj
eV
(2.2)
into (2.2) gives the wave velocity
LCk
1
(2.3)
The capacitance per unit length associated with each power grid wire is (figure 2.3)
AsCC (2.4)
where CA is the capacitance per unit area in the region surrounding the wire and s is
the wire spacing.
Combining (2.3) and (2.4) gives
AsLC
f
1
(2.5)
where and f are the wavelength and frequency of the power grid noise.
Figure 2.3. Relationship between C and CA in a power grid.
14
15. In Π-FP, transmission lines and lumped decoupling capacitors model the power
network in each IC package, all board level connections and the power supply. Figure
2.4 shows a single transmission line pair. Power and ground wires have the same
resistance per unit length thus the magnitude of any IR drop is equal to ground bounce
Figure 2.4. A transmission line
at each point on the line. The inductance of the pair includes magnetic flux from both
power and ground wires. This flux should be minimised by routing the wires at
minimum space wherever possible. Designs using singly routed power or ground
wires are not allowed. Unpaired power grid wires couple strongly to other nets in high
speed systems so these are best avoided at the design stage.
A transmission line is included in the netlist using:
Tname node1 node2 R L C length
Where R,L and C are per unit length. Only two node names are required in the
transmission line definition. Power and ground wires must always be routed together
so there is no need for separate node names for supply and return nets.
The electromagnetic field solver calculates potential changes everywhere on the chip,
including the spaces containing dielectric between each wire. This means that there is
no on-chip network and set of nodes at which to connect the external transmission
lines. We need to create a node for each transmission line to connect to an on-chip
grid. This done using:
Nchip1 node1 0.04 0.05
This node is located at x=0.4mm, y=0.5mm on chip1. The node name should
correspond to a node in the package/board transmission line network. When a
transmission line is added to the netlist all ideal voltage sources are removed from on-
chip grids and the tool operates in full system mode. Figures 2.5 and 2.6 show results
with one transmission line connected to this node. As expected the on-chip supply
voltage continues to drop with each clock cycle. A single transmission line is not
enough to power this IC even if only one small area of the circuit is active. A large
lumped de-cap is used to model an ideal voltage source. It is added to the right hand
side of the transmission line.
L1 node2 1e-3
15
16. Since there is no current flow to ideal voltage sources at the chip boundary all voltage
contours are now normal to the chip edge. Initial and subsequent voltage drops are
significantly higher than they were with ideal sources in place.
Figure 2.5. On-chip and external transmission line results at t=420ps.
Figure 2.6. A single transmission line is not enough to re-charge the on-chip grid quickly enough.
16
17. Chapter 3
Netlist and parameters
This chapter describes each netlist statement and associated parameters.
17
19. Netlist: Global on-chip grid definition
Gchipname <chip_width> <chip_height> <tline_wire_width> <tline_periodic_space>
<sheet_resistance> <inductance> <Default_cap>
Parameters
Chipname A unique name for the IC.
Chip_width Width of the IC (cm).
Chip_height Height of the IC (cm).
Tline_wire_width Width of supply and return wires in the two layer global
power distribution grid (cm).
Tline_periodic_space Distance between the center lines of supply/return
transmission line pairs in the on-chip global grid (cm).
Sheet_resistance Sheet resistance of wires in the two layer on-chip grid
(Ohms/sq).
Inductance Inductance per unit length of on-chip transmission line
pairs (H/cm).
Default_cap Default capacitance per unit area in regions where no
capacitance blocks have been defined (F/cm2
).
Example
Gcpu1 0.35 0.38 0.0020 0.0090 0.025 8e-9 12.5e-9
19
20. Netlist: On-chip current sources
Ichipname <x_location> <y_location> <width> <height> <filename> <repeats>
Chipname The name of the global on-chip grid defined elsewhere in the
netlist.
X_location Horizontal distance between the left chip edge and the left
edge of the current source (cm).
Y_location Vertical distance between the bottom chip edge and the
bottom edge of the current source (cm).
Width Width of the current source (cm).
Height Height of the current source (cm).
Filename File containing PWL current source profile
Repeats The number of times this profile is to be repeated.
Example
Ichip1 0.04 0.04 0.02 0.02 /profiles/profile1.txt 20
Example PWL profile
0.0 0.0
20e-12 0.010
30e-12 0.015
… ….
<time(s)> <current(A)>
etc.....
20
21. Netlist: On-chip capacitance
Cchipname <x_location> <y_location> <width> <height> <cap>
Chipname The name of the global on-chip grid defined elsewhere in the
netlist.
X_location Horizontal distance between the left chip edge and the left
edge of the capacitance block (cm).
Y_location Vertical distance between the bottom chip edge and the
bottom edge of the capacitance block (cm).
Width Width of the de-cap block (cm).
Height Height of the de-cap block (cm).
cap Total capacitance within the block area (F)
Example
Cchip1 0.0210 0.0324 0.0133 0.0232 6.2e-12
21
22. Netlist: Tranmission lines
Tname <nodename1> <nodename2> <R> <L> <C> <length>
Name The name of the transmission line pair.
Nodename1 First node name.
Nodename2 Second node name.
R Resistance per unit length (Ohms/cm).
L Inductance per unit length (H/cm).
C Capacitance per unit length (F/cm).
Length The length of the transmission line pair (cm).
Example
T1 1 2 5 10e-9 10e-12 0.0100
22
23. Netlist: Connection node
Nchipname <nodename> <X> <Y>
chipname The name of the on-chip grid to which this node will be
attached
Nodename A node in the transmission line network.
X X coordinate of the node (cm).
Y Y coordinate of the node (cm).
Example:
Nchip1 1 0.05 0.05
23
24. Netlist: Ideal cap
Lcapname <nodename> <cap (F)>
nodename A node in the transmission line network.
cap Lumped capacitance added to node (F).
Example
Lcap1 2 1e-9
24
26. Netlist: Accuracy parameter.
Each transmission line pair is divided into short sections. The suggested length of this
section is set using this parameter (default 0.0080).
Example
Divide each tline pair into 80um lengths.
.ACC 0.0080
26
27. Netlist: .PLOT <nplots>
The number of prints/plots during the simulation (equally spaced time intervals).
Default 10.
Example.
.PLOT 50
27
28. Netlist: .PRINTNODE <nodename|ALL>
Sets the node currents/potentials to print to standard output.
Examples.
To print nodes n1 and a2 use:
.PRINTNODE n1
.PRINTNODE a2
To print all nodes use:
.PRINTNODE ALL
28
29. Chapter 4
Graphical output using GNUplot.
The simulator outputs voltage and current data for nodes, transmission lines and on-
chip grids in text files with a .dat extension. A set of default GNUplot scripts is also
created during the simulation. GNUplot is a general purpose plotting program
available in various cross platform versions. It can be obtained from
www.gnuplot.info.
The following netlist contains a single on-chip grid and a single transmission line pair.
Node 1 of the the t-line is connected to the on-chip grid at coordinates x=1.1mm,
y=1.1mm. The piecewise linear current profile in the file pulse.txt is also shown.
.TRAN 200e-12
.PLOT 20
.ACC 0.0060
.PRINTNODE ALL
Ggrid1 0.2 0.2 0.0005 0.0080 0.030 10e-9 10e-9
Igrid1 0.1 0.1 0.02 0.02 pulse.txt 1
Ttline1 1 2 0.01 10e-9 100e-12 0.3
Ngrid1 1 0.11 0.11
pulse.txt
0 0
22E-12 0.030901699
40E-12 0.058778525
60E-12 0.080901699
80E-12 0.095105652
100E-12 0.1
120E-12 0.095105652
140E-12 0.080901699
160E-12 0.058778525
180E-12 0.030901699
200E-12 0
The following file is output during each simulation run:
node.gnuplot
In this simulation the file contains the following GNUplot script:
29
30. set size 1,0.5
set style data linespoints
set xlabel 'time(ns)'
unset mouse
# To plot a single node use one of the following in Gnuplot
#-------------------------------------------------
set title 'node 1 delta(Vs-Vg)'
set multiplot
set origin 0,0.5
plot 'nodev.dat' using 1:2 title '(mV)'
set title 'net current out of node 1'
set origin 0,0
plot 'nodei.dat' using 1:2 title '(mA)'
unset multiplot
pause 1
#-------------------------------------------------
set title 'node 2 delta(Vs-Vg)'
set multiplot
set origin 0,0.5
plot 'nodev.dat' using 1:3 title '(mV)'
set title 'net current out of node 2'
set origin 0,0
plot 'nodei.dat' using 1:3 title '(mA)'
unset multiplot
pause 1
This script can be used to plot all node potentials and currents at one second intervals.
At a command prompt type:
(w)gnuplot node.gnuplot
To plot a single node, remove all the other nodes from this script. For example to plot
node 1 only use:
set size 1,0.5
set style data linespoints
set xlabel 'time(ns)'
unset mouse
#-------------------------------------------------
set title 'node 1 delta(Vs-Vg)'
set multiplot
set origin 0,0.5
plot 'nodev.dat' using 1:2 title '(mV)'
set title 'net current out of node 1'
set origin 0,0
plot 'nodei.dat' using 1:2 title '(mA)'
unset multiplot
pause -1
30
31. GNUplot will create the following plot showing the supply voltage variation and the
net current flowing out of this node.
The style of the plot can be changed by modifying the set statements at the start of the
script. For example to use a mouse to zoom in ant out of the plot remove the ‘unset
mouse’ statement. See the GNUplot manual for more details.
31
32. A GNUplot script is created for each transmission line. These files have the form:
<name>_tline.gnuplot
For example to plot the single transmission line in this system use:
(w)gnuplot tline1_tline.gnuplot
This will plot the transmission line potential variation at 20ps intervals. This script
can also be edited to plot the power noise at a fixed time. For example:
32
33. On chip grid potentials can be plotted using the script <name>_grid.gnuplot. For
example:
33
34. Chapter 5
Invocation of command-line version
The simulator (if compiled independently of the GUI) may be invoked by the
command line:
<executable_name> <netlist_file_name>
For example, in Linux systems, the command line may look like:
pifp mychip.pfn OR </path/>pifp mychip1.pfn
where pifp is the executable name, and mychip1.pfn is the netlist output in
simple text formatting from the tool GUI or compiled manually.
34