This document provides guidelines for designing the printed circuit board (PCB) power distribution network (PDN) for TI OMAP3630, AM37xx, and DM37xx microprocessors. It outlines a 5-step methodology: 1) Requirements for the PCB stackup, 2) Optimizing the physical layout, 3) Static IR drop analysis, 4) AC analysis, and 5) Design checklist. Key recommendations include closely coupling power and ground planes, minimizing dielectric thickness, and optimizing via and trace routing to reduce parasitic inductance and improve high-frequency performance.
Modified design for Full Swing SERF and High Speed SERFIJERA Editor
In this chapter we have discussed the research work done on the basis of literature review and study. The
research methodology and the techniques to modify the present designs in order to achieve better performance
have been discussed with their merits and demerits. In this paper FS-SERF and HS- SERF full adder topologies
are presented. The analysis of Power, Delay, Power Delay Product (PDP) optimization characteristics of SERF
Adder is designed. In order to achieve optimal power savings at smaller geometry sizes, proposed a heuristic
approach known as FS-SERF and HS-SERF adder model.
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsTELKOMNIKA JOURNAL
Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore
power amplifiers are the most important parts of electronic circuits. This is why the designing of power
amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design
of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using
a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The
configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The
proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also
utilized for getting the good matching condition. The advanced design system (ADS) software is used for
design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent
power gain; is changed between 28.5 and 20 dB with an output power of 12.45dBm at 1dB compression
point. For the input reflection coefficient (S11) is varied between -20 and -42 dB. While the output reflection
coefficient (S22) is varied between -10 dB and -49 dB over the wide frequency band of 3.2-3.8 GHz.
The document discusses the implementation of distribution automation (DA) on an MV network in South Africa to improve reliability metrics like SAIDI. It describes using DA on the Emondlo NB 125 network as a pilot site by installing telecontrollable section breakers at normal open points to automatically isolate faults and restore supply. A contingency analysis showed the network could withstand load transfers between the interconnected Emondlo, Dagbreek, and St James networks to enable DA functionality while maintaining acceptable voltage levels.
IRJET- Power Scheduling Algorithm based Power Optimization of MpsocsIRJET Journal
This document discusses power scheduling algorithms and techniques for power optimization in multi-core processors. It first introduces dynamic voltage frequency scaling (DVFS) as an efficient method for providing sufficient energy to cores that need it, but notes it is lacking when implemented under design constraints. Several papers are then summarized that propose and analyze different approaches for improving power delivery and regulation in multi-core systems, including using low dropout regulators (LDOs), decoupling capacitors, power gating, and switched capacitor converters to reduce power consumption and improve efficiency. The goal is to develop computer-aided design (CAD) methodologies for efficient power delivery in on-chip processors.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
IRJET- High Efficiency Bridge-Less Battery Charger for Light Electric Veh...IRJET Journal
The document describes a proposed high-efficiency bridge-less battery charger for light electric vehicles. The proposed charger uses MOSFET switches instead of bridge rectifier diodes to reduce conduction losses. It employs an isolated step-up AC-DC converter with a series-resonance circuit to provide zero current switching and reduce switching losses. Experimental results showed the proposed converter achieved 92.02% peak efficiency at 255 kHz with a 12V input and 50V output.
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...IRJET Journal
The document proposes a new switched-capacitor multilevel inverter topology with reduced switch count that can produce a nine-level staircase output voltage from multiple DC sources. It utilizes asymmetric DC voltage sources from renewable energy farms to reduce the number of inverters needed. The topology inherently solves the capacitor voltage balancing problem and can step up the input voltage without a bulky transformer. It is intended for use in high frequency AC power distribution systems to achieve benefits like smaller component sizes and higher power density. The performance of the proposed topology is evaluated using MATLAB/Simulink.
A Review of Analysis and Modeling of Grid Connected Three Phase Multilevel Un...IRJET Journal
This document reviews a five-level multiple-pole structure for a grid connected three phase multilevel unity power rectifier that aims to improve power factor and reduce total harmonic distortion using fewer components. The proposed design is a five-level/multiple-pole multilevel unity power factor rectifier that achieves unity power factor and input current shaping with a reduced number of components. It uses a simple control method based on average current control at a low switching frequency to compensate for grid current harmonics. Simulation results show the design has better dynamic response and tracking under unbalanced grid conditions compared to other existing rectifier topologies.
Modified design for Full Swing SERF and High Speed SERFIJERA Editor
In this chapter we have discussed the research work done on the basis of literature review and study. The
research methodology and the techniques to modify the present designs in order to achieve better performance
have been discussed with their merits and demerits. In this paper FS-SERF and HS- SERF full adder topologies
are presented. The analysis of Power, Delay, Power Delay Product (PDP) optimization characteristics of SERF
Adder is designed. In order to achieve optimal power savings at smaller geometry sizes, proposed a heuristic
approach known as FS-SERF and HS-SERF adder model.
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsTELKOMNIKA JOURNAL
Amplification is one of the most basic and prevalent microwave analog circuit functions. Wherefore
power amplifiers are the most important parts of electronic circuits. This is why the designing of power
amplifiers is crucial in analog circuit designing. The intent of this work is to present an analysis and design
of a microwave broadband power amplifier by using two stages topology. A two stages power amplifier using
a distributed matching network for WiMAX applications is based on ATF-21170 (GaAs FET). The
configuration aims to achieve high power gain amplifier with low return loss over a broad bandwidth. The
proposed BPA is designed with a planar structure on an epoxy (FR4) substrate. The planar structure is also
utilized for getting the good matching condition. The advanced design system (ADS) software is used for
design, simulation, and optimization the proposed amplifier. The complete amplifier achieves an excellent
power gain; is changed between 28.5 and 20 dB with an output power of 12.45dBm at 1dB compression
point. For the input reflection coefficient (S11) is varied between -20 and -42 dB. While the output reflection
coefficient (S22) is varied between -10 dB and -49 dB over the wide frequency band of 3.2-3.8 GHz.
The document discusses the implementation of distribution automation (DA) on an MV network in South Africa to improve reliability metrics like SAIDI. It describes using DA on the Emondlo NB 125 network as a pilot site by installing telecontrollable section breakers at normal open points to automatically isolate faults and restore supply. A contingency analysis showed the network could withstand load transfers between the interconnected Emondlo, Dagbreek, and St James networks to enable DA functionality while maintaining acceptable voltage levels.
IRJET- Power Scheduling Algorithm based Power Optimization of MpsocsIRJET Journal
This document discusses power scheduling algorithms and techniques for power optimization in multi-core processors. It first introduces dynamic voltage frequency scaling (DVFS) as an efficient method for providing sufficient energy to cores that need it, but notes it is lacking when implemented under design constraints. Several papers are then summarized that propose and analyze different approaches for improving power delivery and regulation in multi-core systems, including using low dropout regulators (LDOs), decoupling capacitors, power gating, and switched capacitor converters to reduce power consumption and improve efficiency. The goal is to develop computer-aided design (CAD) methodologies for efficient power delivery in on-chip processors.
IRJET-Design of Capacitor Less LDO Regulator by using Cascode Compensation Te...IRJET Journal
The document discusses two approaches to designing low dropout voltage regulators (LDOs). The first approach uses a basic LDO design with a compensation capacitor to achieve stability. This design has a dropout voltage of 200mV and provides an output voltage of 1.4V with a bandwidth of 475.67 KHz and phase margin of 43.85 degrees. The second approach aims to design a capacitor-less LDO using cascode compensation technique. This design achieves a lower dropout voltage of 100mV and higher bandwidth of 2.55 MHz and phase margin of 63 degrees through the use of an 80pF miller compensation capacitor and 50 kOhm series resistor to shift the right half plane zero and improve stability without requiring an
IRJET- High Efficiency Bridge-Less Battery Charger for Light Electric Veh...IRJET Journal
The document describes a proposed high-efficiency bridge-less battery charger for light electric vehicles. The proposed charger uses MOSFET switches instead of bridge rectifier diodes to reduce conduction losses. It employs an isolated step-up AC-DC converter with a series-resonance circuit to provide zero current switching and reduce switching losses. Experimental results showed the proposed converter achieved 92.02% peak efficiency at 255 kHz with a 12V input and 50V output.
IRJET- A Novel Modified Switched Capacitor Nine Level Inverter Topology with ...IRJET Journal
The document proposes a new switched-capacitor multilevel inverter topology with reduced switch count that can produce a nine-level staircase output voltage from multiple DC sources. It utilizes asymmetric DC voltage sources from renewable energy farms to reduce the number of inverters needed. The topology inherently solves the capacitor voltage balancing problem and can step up the input voltage without a bulky transformer. It is intended for use in high frequency AC power distribution systems to achieve benefits like smaller component sizes and higher power density. The performance of the proposed topology is evaluated using MATLAB/Simulink.
A Review of Analysis and Modeling of Grid Connected Three Phase Multilevel Un...IRJET Journal
This document reviews a five-level multiple-pole structure for a grid connected three phase multilevel unity power rectifier that aims to improve power factor and reduce total harmonic distortion using fewer components. The proposed design is a five-level/multiple-pole multilevel unity power factor rectifier that achieves unity power factor and input current shaping with a reduced number of components. It uses a simple control method based on average current control at a low switching frequency to compensate for grid current harmonics. Simulation results show the design has better dynamic response and tracking under unbalanced grid conditions compared to other existing rectifier topologies.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Silicon Carbide (SiC), new power switches (PSW) require new driver circuits which can take advantage of their new capabilities. In this paper a novel Gallium Nitride (GaN) based gate driver is proposed as a solution to control SiC power switches. The proposed driver is implemented and is performance compared with its silicon (Si) counterparts on a hard switching environment. A thorough evaluation of the energy involved in the switching process is presented showing that the GaN based circuit exhibits similar output losses but reduces the control power needed to operate at a specified frequency.
IRJET- Design and Analysis of Single Phase Modified Quasi-Z-Source Cascaded H...IRJET Journal
This document proposes a single-phase modified quasi-Z-source (MqZS) hybrid three-level inverter and a single-phase modified quasi-Z-source cascaded hybrid five-level inverter (MqZS-CHI) to boost output voltage with fewer components than existing topologies. The MqZS-CHI connects two three-level inverters in series to produce a nine-level output voltage. It reduces inductors and improves boost ability over prior quasi-Z-source cascaded and neural-point clamped multilevel inverters which have limited boost factors. Simulation and experimental results are presented to validate the performance of the proposed topologies and modulation techniques.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
IRJET-Modern Z-Source Power Conversion Topologies: A ReviewIRJET Journal
This document provides a review of modern Z-source power conversion topologies. It begins by discussing limitations of traditional voltage source and current source converters, such as only being able to perform buck or boost operation. The Z-source network was introduced to overcome these limitations by providing both buck and boost functionality using an LC component configuration. The document then reviews several modifications of the basic Z-source network topology, including quasi-Z-source, embedded Z-source, trans-Z-source, Γ-Z-source, and LCCT Z-source networks, analyzing their components, features, and benefits. It concludes that modified Z-source networks have advantages like high reliability, efficiency, buck-boost capability, and reduced harmonic
IRJET- Voltage Drop Compensation in Distribution System using Cascaded H-Brid...IRJET Journal
1) The document proposes a cascaded multilevel inverter based dynamic voltage restorer (DVR) to compensate for voltage sags in distribution systems.
2) A cascaded multilevel inverter is used in the DVR to generate stepped output voltages with low harmonic distortion. This reduces voltage stress on switches compared to traditional DVR designs.
3) Clarke's and Park's transformation techniques are applied to control the cascaded multilevel inverter switches using pulse width modulation for voltage compensation during faults.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
1) The document proposes techniques for reducing power consumption in VLSI circuits, including minimizing bus transitions using coding schemes, resistive feedback paths to eliminate glitches, and voltage scaling.
2) A resistive feedback method is developed to eliminate glitches in CMOS circuits which reduces power consumption and improves performance.
3) Simulation results show that the proposed resistive feedback technique is effective at minimizing glitches and reducing unnecessary power dissipation compared to a design without feedback paths.
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
This document describes the design of a low-power compact CMOS variable gain amplifier (VGA) for modern RF receivers. A two-stage class AB VGA design is presented, with each stage comprising a direct transconductance amplifier and a linear transimpedance amplifier. Post-layout simulation results show the VGA achieves a bandwidth of over 200MHz and a gain range from -33dB to 32dB, while dissipating only 2mW from a 1.2V supply. The core chip area is 0.026mm2, smaller than recent VGA designs. Performance comparisons show the proposed VGA has the widest bandwidth and smallest die area compared to other designs.
IRJET- Design and Analysis of Typical Chemical Industry Electrical Distributi...IRJET Journal
This document describes the design and analysis of the electrical distribution system for a typical large-scale chemical industry plant using ETAP software. The existing 11kV distribution network is analyzed and found to be insufficient for current load demands. A new optimized distribution network is proposed, including three 11kV/415V distribution transformers, duplicate and sectionalized main buses, motor control centers, and backup diesel generators. Load flow analysis is performed on the proposed network under normal and abnormal conditions. The results show improvements in voltage profile, losses, and power factor compared to the existing network.
Design of bridgeless high-power-factor buck-converter operating in discontinu...IRJET Journal
The document proposes a new bridgeless buck converter operating in discontinuous capacitor voltage mode (DCVM) for power factor correction. Key advantages of the proposed topology include lower conduction losses compared to conventional topologies due to fewer simultaneously conducting semiconductor components. The DCVM operation provides zero-voltage switching for the power switches and zero-voltage turn-on for the output diode, improving efficiency. Simulation results show the converter achieves high power factor and low total harmonic distortion in the input current under different load conditions.
As a consequence of sensitive, diverse and complex loads in today's distribution networks, improving power quality in distribution systems has attracted great attention. Power quality issues involve voltage sags, transient interrupts and other distortions in sinusoidal waveforms. Enormous methods have been proposed for power quality modification. One of the methods by which power quality problems might be addressed is to apply power electronic devices in the form of custom power devices. One of such devices is Dynamic Voltage Restorer (DVR) which is connected in series to distribution networks. At the same time, through injection of voltage to the network it is able to control voltage amplitude and phase. It is adopted lend to compensate for voltage sags through injecting series and synchronous three phase voltage. Consisted of three single phase inverters and a DC bus, it can protect susceptible loads against various types of voltage sags as well as other disturbances in the power supply. Moreover, it is capable of generating and absorbing active and reactive power. Therefore, in this paper, different structures of DVR have been investigated and eventually proposed a new structure for DVR based on Γ-Source asymmetric inverter. With the proposed structure, severe voltage sags can be retrieved 80- 90 percent. The simulation results that obtained by using MATLAB/Simulink indicate the properly functioning of proposed structure.
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...IRJET Journal
This document describes the design and implementation of a high-speed on-chip monitoring circuit using a SAR-based comparator. It discusses a 10-bit pipelined analog-to-digital converter that uses a pipeline comparator architecture to achieve high speed and resolution. The design uses dynamic amplifiers in the multiplying digital-to-analog converters to enable high-speed operation even at low supply voltages. A 16-bit prototype achieves 160 MS/s conversion rate at 0.55V supply voltage. The document also reviews various comparator architectures and identifies current-mode algorithmic comparators as well as operating transistors in subthreshold region as promising approaches for achieving very low power consumption suitable for applications such as distributed sensor networks.
This document presents a study on using a multi-level inverter based DSTATCOM (distributed static synchronous compensator) and DVR (dynamic voltage restorer) with a neuro-fuzzy controller to improve power quality by mitigating voltage sags. It proposes a cascaded multilevel inverter topology with isolated DC energy storage and reduced switches. Simulation results show the MLI-based DSTATCOM and DVR can compensate voltage sags by injecting current and voltage respectively to regulate the bus voltage. The output with compensation has 1500V voltage compared to 1000V without compensation during a 500V sag.
Development of substations emulator for akure electric power distribution sys...Alexander Decker
This document describes the development of a substation emulator for the electric power distribution system in Akure, Nigeria. Key points:
1) Line diagrams of Akure's power distribution network were digitized, mapping the connections between injection stations and 11kV feeders serving substations. Geographic data on substations was also captured.
2) A distribution automation system was integrated using remote terminal units to monitor substation voltages and currents in real-time via GSM. Threshold alarms trigger status updates.
3) The digitized network and automation data were combined into an engineering software that provides a visual interface to monitor the dynamic behavior of Akure's entire power distribution network.
Dual technique of reconfiguration and capacitor placement for distribution sy...IJECEIAES
Radial Distribution System (RDS) suffer from high real power losses and lower bus voltages. Distribution System Reconfiguration (DSR) and Optimal Capacitor Placement (OCP) techniques are ones of the most economic and efficient approaches for loss reduction and voltage profile improvement while satisfy RDS constraints. The advantages of these two approaches can be concentrated using of both techniques together. In this study two techniques are used in different ways. First, the DSR technique is applied individually. Second, the dual technique has been adopted of DSR followed by OCP in order to identify the technique that provides the most effective performance. Three optimization algorithms have been used to obtain the optimal design in individual and dual technique. Two IEEE case studies (33bus, and 69 bus) used to check the effectiveness of proposed approaches. A Direct Backward Forward Sweep Method (DBFSM) has been used in order to calculate the total losses and voltage of each bus. Results show the capability of the proposed dual technique using Modified Biogeography Based Optimization (MBBO) algorithm to find the optimal solution for significant loss reduction and voltage profile enhancement. In addition, comparisons with literature works done to show the superiority of proposed algorithms in both techniques.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAsIOSR Journals
This document analyzes and compares different power gating techniques to reduce leakage current and ground bounce noise in FPGAs. It discusses stacking power gating, diode-based stacking power gating, and diode-based staggered phase damping techniques applied to a benchmark 74182 carry look ahead adder circuit implemented as a lookup table (LUT) in FPGAs. Simulation results show that the diode-based staggered phase damping technique provides up to 99% reduction in ground bounce noise and 75% reduction in leakage current. Performance analysis of the LUT implemented on different FPGAs also shows the diode-based staggered phase damping technique to be most effective at reducing leakage current and ground bounce noise.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
Steven Legacy finds a way to pass on the heir title to his sister Sophie before unexpectedly passing away. Sophie grows up and marries Shan Frio, with whom she has a son named Luke. Janny gives birth to Steven's son Owen before passing away. Ajay's ghost tries to convince the family that Owen should be heir instead of Sophie's children, but they refuse to accept his sexist views. The chapter ends with Sophie giving birth to her son Luke.
An ant works hard without supervision and is very productive. A lion notices this and thinks she could produce even more with oversight. He hires a cockroach supervisor who implements extensive paperwork and meetings. This decreases the ant's productivity. More managers are hired, further reducing productivity until an audit reveals the department is overstaffed. The ant is fired for a poor attitude. The fable warns about over-management decreasing efficiency.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Silicon Carbide (SiC), new power switches (PSW) require new driver circuits which can take advantage of their new capabilities. In this paper a novel Gallium Nitride (GaN) based gate driver is proposed as a solution to control SiC power switches. The proposed driver is implemented and is performance compared with its silicon (Si) counterparts on a hard switching environment. A thorough evaluation of the energy involved in the switching process is presented showing that the GaN based circuit exhibits similar output losses but reduces the control power needed to operate at a specified frequency.
IRJET- Design and Analysis of Single Phase Modified Quasi-Z-Source Cascaded H...IRJET Journal
This document proposes a single-phase modified quasi-Z-source (MqZS) hybrid three-level inverter and a single-phase modified quasi-Z-source cascaded hybrid five-level inverter (MqZS-CHI) to boost output voltage with fewer components than existing topologies. The MqZS-CHI connects two three-level inverters in series to produce a nine-level output voltage. It reduces inductors and improves boost ability over prior quasi-Z-source cascaded and neural-point clamped multilevel inverters which have limited boost factors. Simulation and experimental results are presented to validate the performance of the proposed topologies and modulation techniques.
A Review of Low-Energy 1-Bit Full Adder Techniques for Power Deprived Applica...ijsrd.com
In this work a comparison and study of different low power 1-bit full adder techniques at deep submicron technologies is carried out. The study concentrates in the crucial factors which determine the applicability of the design for particular applications. The comparison of different adders has been carried out on the basis of these parameters i.e. delay, power consumption, output swing, PDP etc. The comparison is carried out between designs with low device count. On the basis of comparison a conclusion has been drawn in which the shortcomings of present designs have been discussed with future possibilities of improvement. The designs compared are TGA, SERF and modified SERF.
IRJET-Modern Z-Source Power Conversion Topologies: A ReviewIRJET Journal
This document provides a review of modern Z-source power conversion topologies. It begins by discussing limitations of traditional voltage source and current source converters, such as only being able to perform buck or boost operation. The Z-source network was introduced to overcome these limitations by providing both buck and boost functionality using an LC component configuration. The document then reviews several modifications of the basic Z-source network topology, including quasi-Z-source, embedded Z-source, trans-Z-source, Γ-Z-source, and LCCT Z-source networks, analyzing their components, features, and benefits. It concludes that modified Z-source networks have advantages like high reliability, efficiency, buck-boost capability, and reduced harmonic
IRJET- Voltage Drop Compensation in Distribution System using Cascaded H-Brid...IRJET Journal
1) The document proposes a cascaded multilevel inverter based dynamic voltage restorer (DVR) to compensate for voltage sags in distribution systems.
2) A cascaded multilevel inverter is used in the DVR to generate stepped output voltages with low harmonic distortion. This reduces voltage stress on switches compared to traditional DVR designs.
3) Clarke's and Park's transformation techniques are applied to control the cascaded multilevel inverter switches using pulse width modulation for voltage compensation during faults.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
1) The document proposes techniques for reducing power consumption in VLSI circuits, including minimizing bus transitions using coding schemes, resistive feedback paths to eliminate glitches, and voltage scaling.
2) A resistive feedback method is developed to eliminate glitches in CMOS circuits which reduces power consumption and improves performance.
3) Simulation results show that the proposed resistive feedback technique is effective at minimizing glitches and reducing unnecessary power dissipation compared to a design without feedback paths.
Design of a low-power compact CMOS variable gain amplifier for modern RF rece...journalBEEI
This document describes the design of a low-power compact CMOS variable gain amplifier (VGA) for modern RF receivers. A two-stage class AB VGA design is presented, with each stage comprising a direct transconductance amplifier and a linear transimpedance amplifier. Post-layout simulation results show the VGA achieves a bandwidth of over 200MHz and a gain range from -33dB to 32dB, while dissipating only 2mW from a 1.2V supply. The core chip area is 0.026mm2, smaller than recent VGA designs. Performance comparisons show the proposed VGA has the widest bandwidth and smallest die area compared to other designs.
IRJET- Design and Analysis of Typical Chemical Industry Electrical Distributi...IRJET Journal
This document describes the design and analysis of the electrical distribution system for a typical large-scale chemical industry plant using ETAP software. The existing 11kV distribution network is analyzed and found to be insufficient for current load demands. A new optimized distribution network is proposed, including three 11kV/415V distribution transformers, duplicate and sectionalized main buses, motor control centers, and backup diesel generators. Load flow analysis is performed on the proposed network under normal and abnormal conditions. The results show improvements in voltage profile, losses, and power factor compared to the existing network.
Design of bridgeless high-power-factor buck-converter operating in discontinu...IRJET Journal
The document proposes a new bridgeless buck converter operating in discontinuous capacitor voltage mode (DCVM) for power factor correction. Key advantages of the proposed topology include lower conduction losses compared to conventional topologies due to fewer simultaneously conducting semiconductor components. The DCVM operation provides zero-voltage switching for the power switches and zero-voltage turn-on for the output diode, improving efficiency. Simulation results show the converter achieves high power factor and low total harmonic distortion in the input current under different load conditions.
As a consequence of sensitive, diverse and complex loads in today's distribution networks, improving power quality in distribution systems has attracted great attention. Power quality issues involve voltage sags, transient interrupts and other distortions in sinusoidal waveforms. Enormous methods have been proposed for power quality modification. One of the methods by which power quality problems might be addressed is to apply power electronic devices in the form of custom power devices. One of such devices is Dynamic Voltage Restorer (DVR) which is connected in series to distribution networks. At the same time, through injection of voltage to the network it is able to control voltage amplitude and phase. It is adopted lend to compensate for voltage sags through injecting series and synchronous three phase voltage. Consisted of three single phase inverters and a DC bus, it can protect susceptible loads against various types of voltage sags as well as other disturbances in the power supply. Moreover, it is capable of generating and absorbing active and reactive power. Therefore, in this paper, different structures of DVR have been investigated and eventually proposed a new structure for DVR based on Γ-Source asymmetric inverter. With the proposed structure, severe voltage sags can be retrieved 80- 90 percent. The simulation results that obtained by using MATLAB/Simulink indicate the properly functioning of proposed structure.
IRJET- A Implementation of High Speed On-Chip Monitoring Circuit by using SAR...IRJET Journal
This document describes the design and implementation of a high-speed on-chip monitoring circuit using a SAR-based comparator. It discusses a 10-bit pipelined analog-to-digital converter that uses a pipeline comparator architecture to achieve high speed and resolution. The design uses dynamic amplifiers in the multiplying digital-to-analog converters to enable high-speed operation even at low supply voltages. A 16-bit prototype achieves 160 MS/s conversion rate at 0.55V supply voltage. The document also reviews various comparator architectures and identifies current-mode algorithmic comparators as well as operating transistors in subthreshold region as promising approaches for achieving very low power consumption suitable for applications such as distributed sensor networks.
This document presents a study on using a multi-level inverter based DSTATCOM (distributed static synchronous compensator) and DVR (dynamic voltage restorer) with a neuro-fuzzy controller to improve power quality by mitigating voltage sags. It proposes a cascaded multilevel inverter topology with isolated DC energy storage and reduced switches. Simulation results show the MLI-based DSTATCOM and DVR can compensate voltage sags by injecting current and voltage respectively to regulate the bus voltage. The output with compensation has 1500V voltage compared to 1000V without compensation during a 500V sag.
Development of substations emulator for akure electric power distribution sys...Alexander Decker
This document describes the development of a substation emulator for the electric power distribution system in Akure, Nigeria. Key points:
1) Line diagrams of Akure's power distribution network were digitized, mapping the connections between injection stations and 11kV feeders serving substations. Geographic data on substations was also captured.
2) A distribution automation system was integrated using remote terminal units to monitor substation voltages and currents in real-time via GSM. Threshold alarms trigger status updates.
3) The digitized network and automation data were combined into an engineering software that provides a visual interface to monitor the dynamic behavior of Akure's entire power distribution network.
Dual technique of reconfiguration and capacitor placement for distribution sy...IJECEIAES
Radial Distribution System (RDS) suffer from high real power losses and lower bus voltages. Distribution System Reconfiguration (DSR) and Optimal Capacitor Placement (OCP) techniques are ones of the most economic and efficient approaches for loss reduction and voltage profile improvement while satisfy RDS constraints. The advantages of these two approaches can be concentrated using of both techniques together. In this study two techniques are used in different ways. First, the DSR technique is applied individually. Second, the dual technique has been adopted of DSR followed by OCP in order to identify the technique that provides the most effective performance. Three optimization algorithms have been used to obtain the optimal design in individual and dual technique. Two IEEE case studies (33bus, and 69 bus) used to check the effectiveness of proposed approaches. A Direct Backward Forward Sweep Method (DBFSM) has been used in order to calculate the total losses and voltage of each bus. Results show the capability of the proposed dual technique using Modified Biogeography Based Optimization (MBBO) algorithm to find the optimal solution for significant loss reduction and voltage profile enhancement. In addition, comparisons with literature works done to show the superiority of proposed algorithms in both techniques.
The paper presents a low Power consumption plays a vital role in the present day VLSI technology. Power consumption of an electronic device can be reduced by adopt changed design styles. Multipliers play a most important role in high concert systems. This project focus on a novel energy efficient technique called adiabatic logic which is based on energy renewal principle and power is compared by designing a multiplier. CMOS technology plays a main role in designing low power consuming devices, compared to different logic family CMOS has less power dissipation. Adiabatic logic method is assumed to be an attractive solution for low power electronic applications. By using Adiabatic techniques energy dissipation in PMOS network can be minimized and selection of energy stored at load capacitance can be recycled instead of dissipated as heat. Tanner EDA tools are used for simulation.
Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAsIOSR Journals
This document analyzes and compares different power gating techniques to reduce leakage current and ground bounce noise in FPGAs. It discusses stacking power gating, diode-based stacking power gating, and diode-based staggered phase damping techniques applied to a benchmark 74182 carry look ahead adder circuit implemented as a lookup table (LUT) in FPGAs. Simulation results show that the diode-based staggered phase damping technique provides up to 99% reduction in ground bounce noise and 75% reduction in leakage current. Performance analysis of the LUT implemented on different FPGAs also shows the diode-based staggered phase damping technique to be most effective at reducing leakage current and ground bounce noise.
A Novel Design of a Microstrip Microwave Power Amplifier for DCS Application ...IJECEIAES
This paper presents a 1.80GHz class-A Microwave power amplifier (PA). The proposed power amplifier is designed with single-stage architecture. This power amplifier consists of a bipolar transistor and improved by Collector-Feedback Biasing fed with a single power supply. The aim of this work is to improve the performance of this amplifier by using simple stubs with 50Ω microstrip transmissions lines. The proposed PA is investigated and optimized by utilizing Advanced Design System (ADS) software. The simulation results show that the amplifier achieves a high power gain of 13dB, output power rise up to 21dBm and good impedances matching ;For the input reflection coefficient (S11) is below than - 46.39dB. Regarding the output reflection coefficient (S22) is below than -29.898dB, with an overall size of about 93 x 59mm². By the end; we find that this power amplifier offers an excellent performance for DCS applications.
Steven Legacy finds a way to pass on the heir title to his sister Sophie before unexpectedly passing away. Sophie grows up and marries Shan Frio, with whom she has a son named Luke. Janny gives birth to Steven's son Owen before passing away. Ajay's ghost tries to convince the family that Owen should be heir instead of Sophie's children, but they refuse to accept his sexist views. The chapter ends with Sophie giving birth to her son Luke.
An ant works hard without supervision and is very productive. A lion notices this and thinks she could produce even more with oversight. He hires a cockroach supervisor who implements extensive paperwork and meetings. This decreases the ant's productivity. More managers are hired, further reducing productivity until an audit reveals the department is overstaffed. The ant is fired for a poor attitude. The fable warns about over-management decreasing efficiency.
PUSHKAR is a town near Ajmer,and is an important tourist destination,famous for Pushkar Lake and the 14th century Hindu temple to Brahma.
if you are palnning for a trip to pushkar please visit us at:
http://templeyatri.com/pushkar-ajmer-yatra/
Fixed-Outline 3-D IC Floor planning with TSV Co-PlacementIRJET Journal
This document describes a new digital input/output power configurable pad (CPAD) circuit for a wafer-scale prototyping platform. The CPAD can provide different standard voltage levels and includes a fast load regulation circuit merged with a high-speed digital I/O. It achieves good voltage regulation performance while offering configurable operation and low power consumption. The CPAD circuit is designed to meet the stringent area and power constraints required for integration into the wafer-scale prototyping platform, which contains over 1 million pads and aims to rapidly prototype electronic systems by interconnecting user integrated circuits deposited on its surface.
Printed Circuit Board Design Techniques for EMC Compliance_20240220_145105_00...AlanGustavo13
Key ways to ensure the purity of the power distribution system in a PCB design include:
1. Controlling the impedance and capacitive loading of each trace path to maintain signal integrity and minimize interference.
2. Maintaining the purity of the power and ground planes by preventing switching noise, externally induced RF fields, surge events, and other interference.
3. Using board materials with low dielectric constants to allow for faster signal propagation speeds and reduced capacitance in trace paths.
4. Minimizing crosstalk and interference through strategic design of signal and power paths.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
The document discusses the key aspects of power distribution network (PDN) design that a PCB designer can influence to ensure sufficient current and voltage are provided to all loads. The two main aspects are: 1) Ensuring sufficient copper between sources and loads by following IPC guidelines or using PDN analysis tools; 2) Optimizing capacitor placement, selection, and layer stackup placement according to guidelines. The document emphasizes that PDN design is less complicated for PCB designers than the overall system design if they focus on optimizing these two aspects within the board layout.
IRJET - Design and Analysis of a Comparator for ADC in Tanner EDAIRJET Journal
This document describes the design and analysis of comparators for use in flash analog-to-digital converters (ADCs). It discusses several comparator circuit designs including dynamic comparators, latch-track comparators, low voltage comparators, and high-speed comparators. The comparators are simulated in Cadence Virtuoso using a 180nm CMOS technology to compare their power, area, and delay characteristics for optimizing flash ADC design. Key goals in comparator design for flash ADCs include reducing power consumption, area overhead, and increasing conversion speed.
PowerReduction in Silicon Ips for Cross-IPInterconnections Using On-Chip Bias...IJTET Journal
In system-on-chip (SoC) integration, silicon intellectual properities (IPs) are blockages for long inter connection. With this stipulation,conventional plans are complled to place those repeaters that drive long inter connection and more power canbe used in ip.It permits the cross-IP interconnection to be steered over the IP utilizing,the Repeaters Implanted within the IP and also On-chip bias generation will be implanted.Design was improve power consumption Outcomes show that suggested style doesn’t just create the bottom plan with soc simpler,however will also improve the power consumption of the long interconnection circuits.
The document presents a machine learning approach to optimize power distribution networks (PDNs) for integrated circuits. It trains a model to quickly predict the total wire length from a given PDN configuration, in order to efficiently search for configurations that minimize routing overhead while meeting power integrity constraints. Experimental results on 28nm industrial designs show the model accurately predicts routing costs and the proposed framework effectively reduces routing overhead compared to previous approaches.
Power Integrity analysis is more important than ever. Product trends continue to demand reduced form factor, while requiring even more power to support our always-on, always-connected lives. See how you can design with confidence knowing your PDN is up to the task and keep your products humming smoothly.
What You Will Learn:
Design trends driving importance of PDN analysis
What are the differences between DC and AC power loss
Common PDN challenges such as power planes fusing, resonance, and voltage ripple and how to identify and solve them
How to identify and optimize decoupling capacitor count and placement
How a design-driven PDN approach can save you time, prevent errors, and keep your designs running smoothly
Presented as a on-demand webinar. FUll recording (with demo) available at:
https://resources.ema-eda.com/webinars/on-demand-webinar-learn-how-to-ensure-a-healthy-pcb-power-delivery-network-pdn
Inductively coupled distributed static compensator for power quality analysi...IJECEIAES
In this research paper, an inductively coupled distributed static compensator (IC-DSTATCOM) for three phase three wire (3P3W) electric power distribution system (EPDS) is proposed. The contraction of power quality (PQ) was marked as a perilous droop mode bump into direct coupled distributed static compensator (DC-DSTATCOM). To regain the PQ, inductive coupling transformer is assisted in conjunction with DC-DSTATCOM. The system equivalent circuit of IC-DSTATCOM is accomplished by take into account of impedance of both transformer and DC-DSTATCOM to reveal the filtering technique. The filtering icos∅ mechanism is performed by following the generalized mathematical approach using MATLAB/Simulink. A case education is reviewed in detail to illustrate the performance of both DC-DSTATCOM and IC-DSTATCOM. The IC-DSTATCOM is amplified healthier as compared to other in terms of harmonics shortening, good power factor, load balancing, and potential regulation. To examine the effectiveness, simulation outputs of the IC-DSTATCOM with different PQ parameter indices are presented by following the benchmark measure of IEEE-2030-7-2017 and IEC-61000-1 system code.
IRJET- Reliability Enhancement of Low-Power Sequential Circuits using Power G...IRJET Journal
This document discusses techniques to improve the reliability of low-power sequential circuits using power gating technology. It presents a study on how process, voltage, and temperature variations affect traditional transmission gate pulsed latch circuits. It proposes a new circuit architecture that uses a stack technique with header and footer switches to reduce power leakage during inactive modes. Simulation results show the proposed design has lower power consumption compared to traditional pulsed latch designs in different technologies. The analysis considers the effects on both the pulser and latch to evaluate reliability under variations, and power gating is shown to provide benefits.
Omg! The Best 278 Pcb Layout Design Specifications Ever!PaddyWang4
1. The document provides specifications for PCB layout and routing, including separating analog and digital circuits with separate power and ground planes, isolating high speed, medium speed, and low speed digital circuits, and placing decoupling capacitors close to ICs.
2. Key guidelines are to separate signals by classification, distance, layer, and shielding to reduce crosstalk and noise coupling. Sensitive high frequency lines should be routed away from noisy power lines.
3. For multilayer boards, adjacent layers should have orthogonal routing and ground planes should be layered closely between signal planes.
This document summarizes some key challenges for digital circuits related to process, voltage, and temperature variations. It discusses techniques to prevent latchup and electrostatic discharge issues in integrated circuits. It also describes simultaneous switching noise that can occur when large numbers of circuits switch simultaneously. The document proposes using adaptive body biasing techniques to compensate for PVT variations and control output slope under different conditions. Simulation results show this approach can adjust rising and falling times of an output buffer for different substrate bias voltage conditions.
Improvement of Transient Stability in Doubly Fed Induction Wind Generator usi...IRJET Journal
This document discusses improving transient stability in doubly fed induction wind generators using a bridge-type fault current limiter (BFCL). It first provides background on doubly fed induction generators and introduces the BFCL. It then describes modeling the generator, controllers, BFCL, and compares the BFCL to a series dynamic braking resistor for limiting fault current. Simulation results are presented and show the BFCL more effectively improves transient stability during symmetrical and asymmetrical faults compared to the resistor. The conclusion is that the BFCL is very efficient at improving transient stability in doubly fed induction generator-based wind farms to meet grid code requirements, and performs better than the resistor except for cost.
Life Cycle of Big Data Analysis by using MapReduce AlgorithmIRJET Journal
This document discusses improving transient stability in doubly fed induction wind generators using a bridge-type fault current limiter (BFCL). It first provides background on doubly fed induction generators and introduces the BFCL. It then describes modeling the wind turbine, doubly fed induction generator, rotor and grid side controllers. Operation and control of the BFCL is explained and compared to a series dynamic braking resistor (SDBR) approach. Simulation results show the BFCL more effectively improves transient stability during faults compared to the SDBR. The document concludes the BFCL is very efficient at improving transient stability in doubly fed induction generator-based variable speed wind turbines to meet grid code requirements, and is more effective than SDBR except for potential
Reconfiguration and Capacitor Placement in Najaf Distribution Networks Sector...IRJET Journal
This document discusses reconfiguring distribution networks and optimally placing capacitors in Najaf, Iraq's distribution systems to improve performance. It provides background on distribution system design using software like CYM_Dist to minimize losses through reconfiguration and reactive power support. The document outlines the proposed methodology, which includes load allocation, network reconfiguration to reduce losses while respecting constraints, and identifying optimal capacitor placement and sizing. It reviews relevant literature on techniques like sensitivity analysis and heuristic optimization for reconfiguration and capacitor placement. The methodology is then applied to the 11kV Al Jamiea distribution system in Najaf as a case study.
A 60 GHz CMOS Power Amplifier for Wireless CommunicationsIJECEIAES
This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dBm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm 2 .
IRJET- A Novel High Speed Power Efficient Double Tail Comparator in 180nm...IRJET Journal
This document presents a novel double tail comparator design that aims to improve speed and power efficiency over existing comparator designs. It first discusses conventional comparator designs and their limitations at lower voltages. It then introduces a new 16 transistor double tail comparator configuration that includes control transistors, intermediate transistors, and NMOS switches to reduce power and delay. Simulation results show the transient response and estimate the power and delay of the new design, demonstrating performance improvements over conventional designs. The design was laid out using the Cadence Virtuoso tool.
IRJET- Reduction of Power, Leakage and Area of a Standard Cell Asics using Th...IRJET Journal
This document describes a new approach to reduce power, leakage, and area in standard cell ASICs using threshold logic gates and power gating techniques. Threshold logic gates are designed that behave as multi-input, single-output flip-flops computing a threshold function. Pulsed inputs of varying width are provided. Power gating techniques like sleep mode and MTCMOS are used to reduce leakage and dynamic power. Simulation results show the proposed hybrid circuit of conventional and threshold logic gates with power gating achieves 73% power reduction compared to conventional designs.
This document provides a user manual for the Π-FP software, which simulates power integrity in integrated circuit floorplans. It describes how Π-FP models on-chip power grids, distributed current sources, transmission lines, and capacitance. Key aspects include simulating symmetric two-layer on-chip grids, distributing current sources and capacitance uniformly across blocks, and solving equations to calculate voltage changes along transmission line elements. Example simulations demonstrate how Π-FP can analyze power noise within chips and across multiple connected chips, packages, and boards.
Implementation and analysis of power reduction in 2 to 4 decoder design using...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Evolving Lifecycles with High Resolution Site Characterization (HRSC) and 3-D...Joshua Orris
The incorporation of a 3DCSM and completion of HRSC provided a tool for enhanced, data-driven, decisions to support a change in remediation closure strategies. Currently, an approved pilot study has been obtained to shut-down the remediation systems (ISCO, P&T) and conduct a hydraulic study under non-pumping conditions. A separate micro-biological bench scale treatability study was competed that yielded positive results for an emerging innovative technology. As a result, a field pilot study has commenced with results expected in nine-twelve months. With the results of the hydraulic study, field pilot studies and an updated risk assessment leading site monitoring optimization cost lifecycle savings upwards of $15MM towards an alternatively evolved best available technology remediation closure strategy.
Improving the viability of probiotics by encapsulation methods for developmen...Open Access Research Paper
The popularity of functional foods among scientists and common people has been increasing day by day. Awareness and modernization make the consumer think better regarding food and nutrition. Now a day’s individual knows very well about the relation between food consumption and disease prevalence. Humans have a diversity of microbes in the gut that together form the gut microflora. Probiotics are the health-promoting live microbial cells improve host health through gut and brain connection and fighting against harmful bacteria. Bifidobacterium and Lactobacillus are the two bacterial genera which are considered to be probiotic. These good bacteria are facing challenges of viability. There are so many factors such as sensitivity to heat, pH, acidity, osmotic effect, mechanical shear, chemical components, freezing and storage time as well which affects the viability of probiotics in the dairy food matrix as well as in the gut. Multiple efforts have been done in the past and ongoing in present for these beneficial microbial population stability until their destination in the gut. One of a useful technique known as microencapsulation makes the probiotic effective in the diversified conditions and maintain these microbe’s community to the optimum level for achieving targeted benefits. Dairy products are found to be an ideal vehicle for probiotic incorporation. It has been seen that the encapsulated microbial cells show higher viability than the free cells in different processing and storage conditions as well as against bile salts in the gut. They make the food functional when incorporated, without affecting the product sensory characteristics.
Presented by The Global Peatlands Assessment: Mapping, Policy, and Action at GLF Peatlands 2024 - The Global Peatlands Assessment: Mapping, Policy, and Action
Kinetic studies on malachite green dye adsorption from aqueous solutions by A...Open Access Research Paper
Water polluted by dyestuffs compounds is a global threat to health and the environment; accordingly, we prepared a green novel sorbent chemical and Physical system from an algae, chitosan and chitosan nanoparticle and impregnated with algae with chitosan nanocomposite for the sorption of Malachite green dye from water. The algae with chitosan nanocomposite by a simple method and used as a recyclable and effective adsorbent for the removal of malachite green dye from aqueous solutions. Algae, chitosan, chitosan nanoparticle and algae with chitosan nanocomposite were characterized using different physicochemical methods. The functional groups and chemical compounds found in algae, chitosan, chitosan algae, chitosan nanoparticle, and chitosan nanoparticle with algae were identified using FTIR, SEM, and TGADTA/DTG techniques. The optimal adsorption conditions, different dosages, pH and Temperature the amount of algae with chitosan nanocomposite were determined. At optimized conditions and the batch equilibrium studies more than 99% of the dye was removed. The adsorption process data matched well kinetics showed that the reaction order for dye varied with pseudo-first order and pseudo-second order. Furthermore, the maximum adsorption capacity of the algae with chitosan nanocomposite toward malachite green dye reached as high as 15.5mg/g, respectively. Finally, multiple times reusing of algae with chitosan nanocomposite and removing dye from a real wastewater has made it a promising and attractive option for further practical applications.
ENVIRONMENT~ Renewable Energy Sources and their future prospects.tiwarimanvi3129
This presentation is for us to know that how our Environment need Attention for protection of our natural resources which are depleted day by day that's why we need to take time and shift our attention to renewable energy sources instead of non-renewable sources which are better and Eco-friendly for our environment. these renewable energy sources are so helpful for our planet and for every living organism which depends on environment.
Climate Change All over the World .pptxsairaanwer024
Climate change refers to significant and lasting changes in the average weather patterns over periods ranging from decades to millions of years. It encompasses both global warming driven by human emissions of greenhouse gases and the resulting large-scale shifts in weather patterns. While climate change is a natural phenomenon, human activities, particularly since the Industrial Revolution, have accelerated its pace and intensity
Optimizing Post Remediation Groundwater Performance with Enhanced Microbiolog...Joshua Orris
Results of geophysics and pneumatic injection pilot tests during 2003 – 2007 yielded significant positive results for injection delivery design and contaminant mass treatment, resulting in permanent shut-down of an existing groundwater Pump & Treat system.
Accessible source areas were subsequently removed (2011) by soil excavation and treated with the placement of Emulsified Vegetable Oil EVO and zero-valent iron ZVI to accelerate treatment of impacted groundwater in overburden and weathered fractured bedrock. Post pilot test and post remediation groundwater monitoring has included analyses of CVOCs, organic fatty acids, dissolved gases and QuantArray® -Chlor to quantify key microorganisms (e.g., Dehalococcoides, Dehalobacter, etc.) and functional genes (e.g., vinyl chloride reductase, methane monooxygenase, etc.) to assess potential for reductive dechlorination and aerobic cometabolism of CVOCs.
In 2022, the first commercial application of MetaArray™ was performed at the site. MetaArray™ utilizes statistical analysis, such as principal component analysis and multivariate analysis to provide evidence that reductive dechlorination is active or even that it is slowing. This creates actionable data allowing users to save money by making important site management decisions earlier.
The results of the MetaArray™ analysis’ support vector machine (SVM) identified groundwater monitoring wells with a 80% confidence that were characterized as either Limited for Reductive Decholorination or had a High Reductive Reduction Dechlorination potential. The results of MetaArray™ will be used to further optimize the site’s post remediation monitoring program for monitored natural attenuation.
Epcon is One of the World's leading Manufacturing Companies.EpconLP
Epcon is One of the World's leading Manufacturing Companies. With over 4000 installations worldwide, EPCON has been pioneering new techniques since 1977 that have become industry standards now. Founded in 1977, Epcon has grown from a one-man operation to a global leader in developing and manufacturing innovative air pollution control technology and industrial heating equipment.
Recycling and Disposal on SWM Raymond Einyu pptxRayLetai1
Increasing urbanization, rural–urban migration, rising standards of living, and rapid development associated with population growth have resulted in increased solid waste generation by industrial, domestic and other activities in Nairobi City. It has been noted in other contexts too that increasing population, changing consumption patterns, economic development, changing income, urbanization and industrialization all contribute to the increased generation of waste.
With the increasing urban population in Kenya, which is estimated to be growing at a rate higher than that of the country’s general population, waste generation and management is already a major challenge. The industrialization and urbanization process in the country, dominated by one major city – Nairobi, which has around four times the population of the next largest urban centre (Mombasa) – has witnessed an exponential increase in the generation of solid waste. It is projected that by 2030, about 50 per cent of the Kenyan population will be urban.
Aim:
A healthy, safe, secure and sustainable solid waste management system fit for a world – class city.
Improve and protect the public health of Nairobi residents and visitors.
Ecological health, diversity and productivity and maximize resource recovery through the participatory approach.
Goals:
Build awareness and capacity for source separation as essential components of sustainable waste management.
Build new environmentally sound infrastructure and systems for safe disposal of residual waste and replacing current dumpsites which should be commissioned.
Current solid waste management situation:
The status.
Solid waste generation rate is at 2240 tones / day
collection efficiently is at about 50%.
Actors i.e. city authorities, CBO’s , private firms and self-disposal
Current SWM Situation in Nairobi City:
Solid waste generation – collection – dumping
Good Practices:
• Separation – recycling – marketing.
• Open dumpsite dandora dump site through public education on source separation of waste, of which the situation can be reversed.
• Nairobi is one of the C40 cities in this respect , various actors in the solid waste management space have adopted a variety of technologies to reduce short lived climate pollutants including source separation , recycling , marketing of the recycled products.
• Through the network, it should expect to benefit from expertise of the different actors in the network in terms of applicable technologies and practices in reducing the short-lived climate pollutants.
Good practices:
Despite the dismal collection of solid waste in Nairobi city, there are practices and activities of informal actors (CBOs, CBO-SACCOs and yard shop operators) and other formal industrial actors on solid waste collection, recycling and waste reduction.
Practices and activities of these actor groups are viewed as innovations with the potential to change the way solid waste is handled.
CHALLENGES:
• Resource Allocation.
Microbial characterisation and identification, and potability of River Kuywa ...Open Access Research Paper
Water contamination is one of the major causes of water borne diseases worldwide. In Kenya, approximately 43% of people lack access to potable water due to human contamination. River Kuywa water is currently experiencing contamination due to human activities. Its water is widely used for domestic, agricultural, industrial and recreational purposes. This study aimed at characterizing bacteria and fungi in river Kuywa water. Water samples were randomly collected from four sites of the river: site A (Matisi), site B (Ngwelo), site C (Nzoia water pump) and site D (Chalicha), during the dry season (January-March 2018) and wet season (April-July 2018) and were transported to Maseno University Microbiology and plant pathology laboratory for analysis. The characterization and identification of bacteria and fungi were carried out using standard microbiological techniques. Nine bacterial genera and three fungi were identified from Kuywa river water. Clostridium spp., Staphylococcus spp., Enterobacter spp., Streptococcus spp., E. coli, Klebsiella spp., Shigella spp., Proteus spp. and Salmonella spp. Fungi were Fusarium oxysporum, Aspergillus flavus complex and Penicillium species. Wet season recorded highest bacterial and fungal counts (6.61-7.66 and 3.83-6.75cfu/ml) respectively. The results indicated that the river Kuywa water is polluted and therefore unsafe for human consumption before treatment. It is therefore recommended that the communities to ensure that they boil water especially for drinking.