This document discusses evaluating a UCIe-based multi-die system-on-chip (SoC) using system modeling to meet timing and power constraints. It provides an overview of UCIe and how it can be used to connect multiple dies. It then describes assembling a system model in VisualSim Architect using UCIe components to analyze configurations and optimize latency, bandwidth, and power. Examples of multi-media and automotive applications using UCIe-based chiplet designs are also presented.
PCIe Gen 3.0 Presentation @ 4th FPGA CampFPGA Central
PCIe Gen3 presentation by PLDA at 4th FPGA Camp in Santa Clara, CA. For more details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.com
PCIe Gen 3.0 Presentation @ 4th FPGA CampFPGA Central
PCIe Gen3 presentation by PLDA at 4th FPGA Camp in Santa Clara, CA. For more details visit http://www.fpgacentral.com/fpgacamp or http://www.fpgacentral.com
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick44CON
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick.
Hardware hacks tend to focus on low-speed (jtag, uart) and external (network, usb) interfaces, and PCI Express is typically neither. After a crash course in PCIe Architecture, we’ll demonstrate a handful of hacks showing how pull PCIe outside of your system case and add PCIe slots to systems without them, including embedded platforms. We’ll top it off with a demonstration of SLOTSCREAMER, an inexpensive device that’s part of the NSA Playset which we’ve configured to access memory and IO, cross-platform and transparent to the OS - all by design with no 0-day needed. The open hardware and software framework that we will release will expand your Playset with the ability to tinker with DMA attacks to read memory, bypass software and hardware security measures, and directly attack other hardware devices in the system.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Madhu Rangarajan will provide an overview of Networking trends they are seeing in Cloud, various network topologies and tradeoffs, and trends in the acceleration of packet processing workloads. They will also talk about some of the work going on in Intel to address these trends, including FPGAs in the datacenter.
During the CXL Forum at OCP Global Summit 23, Rick Kutcipal and Sreeni Bagalkote of Broadcom presented their PCIe/CXL Roadmap and announced their Atlas 4 CXL switch.
Shared Memory Centric Computing with CXL & OMIAllan Cantle
Discusses how CXL can be better utilized as a separate Fabric Cache domain to a processors own Local Cache Domain. This is done by leveraging a Shared Memory Centric architectures that utilize both the Open Memory Interface OMI, and Compute eXpress Link, CXL, for the memory ports.
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick44CON
44CON 2014 - Stupid PCIe Tricks, Joe Fitzpatrick.
Hardware hacks tend to focus on low-speed (jtag, uart) and external (network, usb) interfaces, and PCI Express is typically neither. After a crash course in PCIe Architecture, we’ll demonstrate a handful of hacks showing how pull PCIe outside of your system case and add PCIe slots to systems without them, including embedded platforms. We’ll top it off with a demonstration of SLOTSCREAMER, an inexpensive device that’s part of the NSA Playset which we’ve configured to access memory and IO, cross-platform and transparent to the OS - all by design with no 0-day needed. The open hardware and software framework that we will release will expand your Playset with the ability to tinker with DMA attacks to read memory, bypass software and hardware security measures, and directly attack other hardware devices in the system.
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
Madhu Rangarajan will provide an overview of Networking trends they are seeing in Cloud, various network topologies and tradeoffs, and trends in the acceleration of packet processing workloads. They will also talk about some of the work going on in Intel to address these trends, including FPGAs in the datacenter.
HPC and cloud distributed computing, as a journeyPeter Clapham
Introducing an internal cloud brings new paradigms, tools and infrastructure management. When placed alongside traditional HPC the new opportunities are significant But getting to the new world with micro-services, autoscaling and autodialing is a journey that cannot be achieved in a single step.
ROLE OF DIGITAL SIMULATION IN CONFIGURING NETWORK PARAMETERSDeepak Shankar
Selecting the right Ethernet standard and configuring all the network devices in the embedded systems accurately is an extremely hard and rigorous job. The configuration depends on the topology, workloads of the connected devices, processing overhead at the switches, and the external interfaces. Network calculus, mathematical models and analytical techniques provide worst case execution time (WCET), but their probability of activity is extremely wide. This leads to overdesign which leads to higher costs, power consumption, weight, and size. Simulating the network is the best way to measure the throughput of the entire system. Digital system simulation provides better latency and throughput accuracy, but the accuracy is still limited because it does not consider the latency associated with the network OS, cybersecurity processing and scheduling. In many cases, these factors can reduce the throughput by 20-40%.
In this paper, we will present our research on modeling the entire Ethernet network, including the workloads, network flow control, scheduling, switch hardware, and software. To substantially increase the coverage and compare topologies, we have developed a set of benchmarks that provides coverage for different combination of deterministic, rate-constrained, and best effort traffic. During the presentation, we will cover the benchmarks, the list of attributes required to accurately model the traffic, nodes, switches, and the scheduler settings. We will also look at the statistics and reports required to make the configuration decision. In addition, we will discuss how the model must be constructed to study the impact of future requirements, failures, network intrusions, and security detection schemes.
Key Takeaways:
1. Learn how to efficiently use network simulation to design Ethernet systems
2. Develop a reusable benchmark and associated statistics to test different configurations
3. The role and impact of the CDT slots, guard band, send slope, idle slope, shuffle scheduling, flow control and virtual channels
OpenPOWER Acceleration of HPCC SystemsHPCC Systems
JT Kellington, IBM and Allan Cantle, Nallatech present at the 2015 HPCC Systems Engineering Summit Community Day about porting HPCC Systems to the POWER8-based ppc64el architecture.
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
The charter of the ODSA (Open Domain Specification Architecture) Workgroup is to define an open specification that enables building of Domain Specific Accelerator silicon using best-of-breed components from the industry made available as chiplet dies that can be integrated together as Lego blocks on an organic substrate packaging layer. The resulting multi-chip module (MCM) silicon can be produced at significantly lower development and manufacturing costs, and will deliver much needed performance per watt and performance per dollar efficiencies in networking, security, machine learning and other applications. The ODSA Workgroup also intends to deliver implementations of the specification as board-level prototypes, RTL code and libraries.
Radisys' CTO, Andrew Alleman, was one of the featured speakers at the OCP Telco Engineering Workshop during the 2017 Big Communications Event. Andrew discussed carrier-grade open rack architecture (CG-OpenRack-19), the future of open hardware standards and commercial products in the OCP pipeline during his presentation.
Ron Swartzentruber's (Senior Principal Engineer, Silicon Development at Netronome) presentation from IEEE SOCC 2016 "SoC Solutions Enabling Server-Based Networking" from September 8, 2016.
There is a huge amount of data out there and a great deal of power and insight that we can gain from it — if we can just bring it all into focus and make it more manageable. Many industrial organizations are accomplishing this by building sophisticated HMI, SCADA, and MES projects with the Ignition Perspective Module.
Build the network of the future on your terms todayDell World
Is your enterprise network capable of handling the demand of today's mobile enterprise? The network you put in place yesterday may be struggling to support applications like unified communications and video while maintaining high standards for security compliance. Learn how Dell is designing the campus network of the future and how you can take advantage of this next generation architecture with improved management and performance. We will discuss how you can make the transition to the network of the future—on your terms and at the pace you choose—with minimal disruption.
Using Kubernetes to make cellular data plans cheaper for 50M usersMirantis
Use case of Kubernetes based NFV infrastructure used in production to run an open source evolved packet core. Presented by Facebook Connectivity and Mirantis at KubeCon + CloudNativeCon Europe 2020.
How to achieve 95%+ Accurate power measurement during architecture exploration? Deepak Shankar
During the conceptualization and architectural exploration phases, it is crucial to assess the power budget.
Would you like to accurately measure the:
1. Power consumed for a proposed embedded software or firmware?
2. Savings of a Power Management Algorithm prior to development?
3. Power impact of hardware configuration change?
4. Trade-off between Power and Performance?
5. Temperature, heat, peak power and cumulative power?
Mirabilis_Design AMD Versal System-Level IP LibraryDeepak Shankar
Mirabilis Design provides the VisualSim Versal Library that enable System Architect and Algorithm Designers to quickly map the signal processing algorithms onto the Versal FPGA and define the Fabric based on the performance. The Versal IP support all the heterogeneous resource.
Get ready to dive into the exciting world of IoT data processing! 🌐📊
Join us for a thought-provoking webinar on "Processing: Turning IoT Data into Intelligence" hosted by industry visionary Deepak Shankar, founder of Mirabilis Design. Discover how to harness the potential of IoT devices by strategically choosing processors that optimize power, performance, and space.
In this engaging session, you'll explore key insights:
✅ Impact of processor architecture on Power-Performance-Area optimization
✅ Enabling AI and ML algorithms through precise compute and storage requirements
✅ Future trends in IoT hardware innovation
✅ Strategies for extending battery life and cost prediction through system design
Don't miss the chance to learn how to leverage a single IoT Edge processor for multiple applications and much more. This is your opportunity to gain a competitive edge in the evolving IoT landscape.
In Electronic System design, modeling abstraction is a powerful technique that involves creating simplified representations of complex electronic systems.
VisualSim Architect allows designers to create more manageable, modular, scalable, and robust electronic systems that meet the requirements of real-world applications. By leveraging abstraction, designers can focus on the critical aspects of a system's functionality, behavior, and interface, and effectively communicate design concepts and make informed decisions.
Accelerated development in Automotive E/E Systems using VisualSim ArchitectDeepak Shankar
The recent trends and developments in the automotive sector towards fully autonomous diving system and vehicle to vehicle (V2V) communication would mean a drastic increase in the number of sensors, increased number of ECUs, increased concern for safety and security. This calls for the need to perform thorough evaluations on the target system architecture, at all levels - Hardware, Software and Network. During this webinar, we show how we evaluate each of these aspects of the Automotive E/E system and take a closer look at the performance, power and functional correctness of each of the auto subsystems. We will also inject faults into the demo model, which will tell us how the automotive system would perform under failure.
The webinar also showcases various Use case examples, which includes - comparison of TSN Standards, modelling of various topology, task graph modelling, glimpses into TC10 sleep-wakeup standard and integrated software.
Compare Performance-power of Arm Cortex vs RISC-V for AI applications_oct_2021Deepak Shankar
Abstract: In the Webinar, we will show you how to construct, simulate, analyze, validate, optimize an architecture model using pre-built components. We will compare micro and application benchmarks on system SoC models containing clusters of ARM Cortex A53, SiFive u74, ARM Cortex A77, and other vendor cores. The system will be built around custom switches, Ingress/Egress buffers, credit flow control, AI accelerators, NoC and AMBA AXI buses with multi-level caches, DDR4 DRAM and DMA. The evaluation and optimization criteria will be task latency, dCache hit-ratio, power consumed/task and memory bandwidth. The parameters to be modified are bus topology, cache size, processor clock speed, custom arbiters, task thread allocation and changing the processor pipeline.
Selection of cores is a combination of financial and technical bias. Technical comparison of processor cores requires the understanding of the workload, task partitioning and cache-memory structure. A core must be evaluated in the context of the target application. To evaluate these selections, architecture simulation software must be fortified with a library of Intellectual property for power and timing accurate processor cores, simulator at 100 million events per second, peripherals, and all possible traffic distributions
Key Takeaways:
1. Validating architecture models using mathematical calculus and hardware traces
2. Construct custom policies, arbitrations and configure processor cores
3. Select the right combination of statistics to detect bottlenecks and optimize the architecture
4. Identify the right use of stochastic, transaction, cycle-accurate and traces to construct the model
Speaker Bio:
Alex Su is a FPGA solution architect at E-Elements Technology, Hsinchu, Taiwan. He has been an FPGA Solution Architect and Xilinx FPGA Trainer for a number of years, supporting companies, research centers and universities in China and Taiwan. Prior to that, Mr Su has worked at ARM Ltd for 5 years in technical support of Arm CPU and System IP. Alex has also been engaged with a variety of FPGA-based Hardware Emulation System and over ten years in ASIC/SoC design and verification engineer.
Deepak Shankar is the Founder of Mirabilis Design and has been involved in the architecture exploration of over 250 SoC and processors. Mr. Shankar started Mirabilis Design because of a vacuum in the systems engineering and modeling space with the focus shifting to network design and early software development. Deepak has published over 50 articles and presented at over 30 conferences in EDA, semiconductors and embedded computing. Mr. Shankar has an MBA from UC Berkeley, MS in from Clemson University and BS from Coimbatore Institute of Technology, both in Electronics and Communication.
Energy efficient AI workload partitioning on multi-core systemsDeepak Shankar
o create an AI system, the semiconductor, software, and systems team need to work together. Multi-core systems can provide extremely low latency and higher throughput at lower power consumption. But concurrent access to shared resources by multiple of AI workloads running on different cores can create higher worst-case execution time (WCET) and causes multiple system failures. Architecture exploration can be used to efficiently balance the compute, communication, synchronization, and storage. In this Webinar, we will be using Workloads from automotive, and data centers to demonstrate the methodology.
VisualSim Architect enables designers to assemble architecture models that extend from the smallest IoT to full automotive, and Radar systems to Data Centers. These models will include any combination of software, processors, ECU, RTOS and networks. Using this platform, software designer can explore the partitioning of the AI tasks (software or model) on to cores based on the latency, bandwidth, and power constraints. Within the IoT, the processor, A/D, Bluetooth and software can be modeled while an automotive design will require the network, ECU and firmware. Both have a unique mechanism to define the traffic, test scenarios and AI workloads. Hardware engineers can select cores, cores per cluster, cache hierarchy, memory controller, accelerators, and the interface topology. Software engineers can tune the partitioning, synchronization overhead, memory access schedules and scheduling.
Capacity Planning and Power Management of Data Centers. Deepak Shankar
Key Points discussed in this webinar are:
1.How dynamic simulation can replace traditional network simulations that are slow and lack configuration and visibility to analyze performance.
2.How to avoid over or under design, cost increases, and delays.
3.How an architectural model can be used to test the capacity and power requirements of your data center or your server.
Contact us at info@mirabilisdesign.com for any queries.
Analytical, prototyping, model-based systems engineering and custom discrete-event model development of automotive networks are inaccurate, expensive, and takes too long to do detailed routing analysis, Quality-of-Service (QoS) trade-off, and bandwidth exploration. To capture the nuances of QoS, scheduling, buffer management, and network topologies, these solutions require a considerable amount of time, costs, and customization. To achieve the reliability of wiring harness, the latency and bandwidth measurements of automotive networks must be accurate, tested for failure conditions, and simulated for security breaches, traffic spikes, and translations.
In the design of electronics and semiconductors, challenges are compounded by the integration of AI, multi-core, real-time software, network, connectivity, diagnostics, and security. Performance limits, battery life, and cost are adoption barriers. It is extremely important to have tools and processes that deliver efficiency throughout the design cycle.
Continuous verification from planning to development addresses the multi-discipline needs of hardware, software, and networks. This unique approach accelerates the design phase, defines the test efforts, and finds defects during specification. Architecture modeling is required to meet timing deadlines, generate the lowest power consumption, and attain the highest Quality-of-Service. optimize the electronic design system and designing of custom components.
Using ai for optimal time sensitive networking in avionicsDeepak Shankar
The IEEE 802.1 Time-Sensitive Networking is a standard technology to provide deterministic
routing or transmission of packets on standard Ethernet. By reserving resources for critical traffic,
and applying various queuing and shaping techniques, TSN achieves zero congestion loss for
critical data traffic. This, in turn, allows TSN to guarantee a worst-case end-to-end latency for
critical data. TSN also provides ultra-reliability for data traffic via a data packet level reliability
mechanism as well as protection against bandwidth violation, malfunctioning, malicious attacks,
etc. TSN includes reliable time synchronization, a profile of IEEE 1588, which provides the basis
for many other TSN functions.
Task allocation on many core-multi processor distributed systemDeepak Shankar
Migration of software from a single to multi-core, single to multi-thread, and integrated into a distributed system requires a knowledge of the system and scheduling algorithms. The system consists of a combination of hardware, RTOS, network, and traffic profiles. Of the 100+ popular scheduling algorithms, the majority use First Come-First Server with priority and preemption, Weight Round Robin, and Slot-based. The task allocation must take into consideration a number of factors including the hardware configuration, the RTOS scheduling, task dependency, parallel partitioning, shared resources, and memory access. Additionally, embedded system architectures always have the possibility of using custom hardware to implement tasks that may be associated with Artificial Intelligence, diagnostic or image processing.
In this Webinar, we will show you how to conduct trade-offs using a system model of the tasks and the target resources. You will learn to make decisions based on the hardware and network statistics. The statistics will assist in identifying deadlocks, bottlenecks, possible failures and hardware requirements. To estimate the best task allocation and partitioning, a discrete-event simulation with both time- and quantity-shared resource modeling is essential. The software must be defined as a UML or a task graph.
Web: www.mirabilisdesign.com
Webinar Youtube Link: https://youtu.be/ZrV39SYTWSc
Introduction to Architecture Exploration of Semiconductor, Embedded Systems, ...Deepak Shankar
- Identify design challenges, trade-offs, and exploration.
- Construct an architecture model using data available in documents, spreadsheets, existing code, datasheets, and future concepts.
- Analyze the model to determine the cause of a bottleneck or performance degradation
Develop High-bandwidth/low latency electronic systems for AI/ML applicationDeepak Shankar
the architecture exploration required to accurately size and implement AI/ML platforms for a wide-range of applications in automotive, radar and high-performance computing.
Webinar on Latency and throughput computation of automotive EE networkDeepak Shankar
This solution enables Architects to conduct trade-off on early planning, system sizing and network topology planning. This is part one in a three series that covers systems engineering exploration of Automotive EE Systems. technologies studied in this session include FlexRay, CAN, CAn_FD, TSN. Ethernet, ECU, Brake System, power Supply electronics, Li-Ion Batteries, ADAS and AUTOSAR.
This slides show how to utilize real-world applications to teach early architecture exploration of electronics, embedded systems, software/firmware and semiconductor using visualsim.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Automobile Management System Project Report.pdfKamal Acharya
The proposed project is developed to manage the automobile in the automobile dealer company. The main module in this project is login, automobile management, customer management, sales, complaints and reports. The first module is the login. The automobile showroom owner should login to the project for usage. The username and password are verified and if it is correct, next form opens. If the username and password are not correct, it shows the error message.
When a customer search for a automobile, if the automobile is available, they will be taken to a page that shows the details of the automobile including automobile name, automobile ID, quantity, price etc. “Automobile Management System” is useful for maintaining automobiles, customers effectively and hence helps for establishing good relation between customer and automobile organization. It contains various customized modules for effectively maintaining automobiles and stock information accurately and safely.
When the automobile is sold to the customer, stock will be reduced automatically. When a new purchase is made, stock will be increased automatically. While selecting automobiles for sale, the proposed software will automatically check for total number of available stock of that particular item, if the total stock of that particular item is less than 5, software will notify the user to purchase the particular item.
Also when the user tries to sale items which are not in stock, the system will prompt the user that the stock is not enough. Customers of this system can search for a automobile; can purchase a automobile easily by selecting fast. On the other hand the stock of automobiles can be maintained perfectly by the automobile shop manager overcoming the drawbacks of existing system.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
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Quality defects in TMT Bars, Possible causes and Potential Solutions.PrashantGoswami42
Maintaining high-quality standards in the production of TMT bars is crucial for ensuring structural integrity in construction. Addressing common defects through careful monitoring, standardized processes, and advanced technology can significantly improve the quality of TMT bars. Continuous training and adherence to quality control measures will also play a pivotal role in minimizing these defects.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
For more technical information, visit our website https://intellaparts.com
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
2. Logistics of the Webinar
2
All attendees will be placed on mute
To ask a question, click on Cloud Chat sign and type the
question. Folks are standing by to answer your questions.
There will also be a time at the end for Q&A
3. Agenda
Overview of UCIe™ — Universal Chiplet Interconnect Express™
Introduction to system modeling with UCIe and other Intellectual Properties
Assembling System models using UCIe protocol
Examples of SoC architectures using UCIe
Use Case
Mirabilis Design and VisualSim Architect
5. Background on die-to-die Interconnect
•Packing large number of functions at different clock rate onto a monolithic die is not scalable
•Solution: Integrate multiple dies into a single package – Chiplets
•Chiplet Challenge:
• Die-to-die communication is very slow and consumes too much power
• No single standard available to handle the routing, signalling and multiple clock domains
• Cache coherency across dies
• Support for multiple protocols
•Exploration:
• Need a mechanism to predict the expected latency and power consumption
• Test feasibility of different configurations and assign compute resources on individual dies
• Study the impact of failures or extreme latency
• Explore different scheduling and Quality-of-Service algorithms
6. Universal Chiplet Interconnect Express or
UCIe is the Future
•Customizable, package-level integration of chiplets
• Combines best-in-class die-to-die interconnect and protocol connections from an interoperable, multi-vendor ecosystem
• open industry standard interconnect
•Offers high-bandwidth, low-latency, power-efficient, and cost-effective on-package connectivity
•Implement compute in an advanced process node to deliver power-efficient performance at higher cost
with memory and I/O controller reused from earlier design in an established (n-1 or n-2) process node
•Future design will incorporate interaction between AI engines on different dies connected and require
deterministic latency
•Optimal design requires accurate assignment of resource pooling, resource sharing and messaging passing
•UCIe theoretical bandwidth is 4x bandwidth of PCIe 6.0 (Tbps range)
•Actual bandwidth depends on burst data available, buffer size for the Tx and replay buffer
8. How UCIe Works?
Multiple layers separate out the interconnect tasks
Physical layer is responsible for the electrical signaling,
clocking, link training and sideband
Die-to-Die adapter provides the link state management
and parameter negotiation for the chiplets. It optionally
guarantees reliable delivery of data through CRC and link
level retry mechanism.
◦ When multiple protocols are supported, it defines the
underlying arbitration mechanism.
The FLIT (flow control unit) defines the underlying transfer
mechanism when the adapter is responsible for reliable
transfer
9. UCIe Packaging
Two package types - standard and advanced.
◦ Standard has 16 lanes
◦ Advanced has 64 lanes
To increase bandwidth, support for multi-module
For 2 modules
◦ Standard has 32 lanes
◦ Advanced has 128 lanes
◦ Each will send different bytes of data
Increase in number of lanes as module count
increases
Multiple PHY logic provides for greater data transfer
with better scheduling
10. Transition to UCIe
CXL
2.0
PCIe Gen 6
interface
PCIe Gen 6
interface
Strea
ming
Typical SoC – monolithic approach Next Gen SoC – Use Chiplets in modular approach
11. Commonality with PCIe 6.0
•UCIe protocol emulates PCIe for chiplets
•UCIe transfers packets in FLITs
• PCIe 6.0 uses fixed value of 256 bytes
• UCIe FLIT Size is variable based on the sender and receiver protocol
•Credit based flow control mechanism
•Packets use ACK or NAK to confirm good reception
• Selective and Standard ACK options
•Advanced port status and error checking
• CRC checksum
•Bandwidth depends on the number of lanes
• Standard vs Advanced package
• Multi-Module option
13. Multi-Media Application –
UCIe Template provided by Intel
CPU – High
Performance
cores
CPU – Low
Power cores
Audio/Video
Encoder/Decoder
I/O Tile
M
E
M
M
E
M
M
E
M
PCIe 6.0 PCIe 6.0
P
C
I
e
6
.
0
C
X
L
3
.
0
UCIe
Retimer
Off-Package
Interconnect
NVMe SSD
chiplet
UCIe
Retimer
C
X
L
3
.
0
How much should the
retimer timeout be set to?
Do we need a multi module setup?
How much
should the
transfer rate
between UCIe
links be set to?
4 GTs or 8 GTs
… or 32 GTs?
Start with a System Block Diagram
15. Stats
Advanced package, 4 module, 32 GT/s config Standard package, Single module, 4 GT/s config
~300x latency
difference can be
observed. However, for
non-time critical
applications, Standard
UCIe package option
looks attractive
Study the statistics to decide on the best configuration
17. Example 1 – Multi-Media applications
CPU – High
Performance
cores
CPU – Low
Power cores
Audio/Video
Encoder/Decoder
I/O Tile
M
E
M
M
E
M
M
E
M
PCIe 6.0 PCIe 6.0
P
C
I
e
6
.
0
C
X
L
3
.
0
Retimer Off-Package Interconnect
18. Example 2 :
Automotive Autonomous Driving
UCIe
AI Engine Tiles
Warp
Scheduler
PE
PE
PE
PE
Local Mem
GPU
Analog Chiplet
ADC DAC
PLL
ADC DAC
PLL
Processor subsystem
Core L1
B
u
s
SLC
19. Example 3 : Cache Coherency using UCIe
UCIe
SERDES
32nm
GPU
7nm
RISC-V Cores
5nm
ARM Cores
10nm
DSP
10nm
SLC chiplet
22nm
LPDDR5
28nm
C
a
c
h
e
C
a
c
h
e
C
a
c
h
e
C
a
c
h
e
20. Design Challenges in Implementing UCIe
•Huge memory transaction blocks a high priority control access
• For time critical application, these situations are not desirable
• Example : Automotive communication system
•Multiple chiplets can be connected easily and efficiently
• Resource sizing per chiplets needs to be correct to maximize bandwidth usage
• Example applications : Data Center and AI Accelerators
•Migrating from monolithic die to Chiplet in smartphones is efficient
• Limited memory needs to be partitioned for different dies to access with minimal contention
• Example: Apple M1 Ultra uses Chiplets to double the performance
21. Performance challenges
•User defines CXL stacks with two protocols sharing the physical link.
•Arbiter across the Die-to-Die adapter must send Flits alternatively between the 2 protocols.
• If one of the Protocol layers doesn’t have data to transmit, then instead of payload, “NOP” frames are
inserted. If one of the Protocol stacks is idle for most of the time, then bandwidth could essentially be wasted
on the “NOP” frames.
•Increasing the number of modules for either the standard or advanced package provides more
bandwidth.
• But is that extra bandwidth needed for the application?
•What happens if multiple chiplets in your design require the data stored at the same address location
which is in another chiplet?
• Consider the impact of cache coherency
•Can peak throughput be guaranteed for your application in a shared resource environment?
• AI Engine distributed across multiple dies
23. Autonomous driving
UCIe
AI Engine Tiles
Warp
Scheduler
PE
PE
PE
PE
Local Mem
GPU
Memory chiplet
ADC
DDR5
Processor subsystem
Core L1
B
u
s
SLC
• Optimal
mesh size
(mxn) ?
• Best sample
size (16
bytes vs 32
bytes etc) ?
Use a single protocol
stack or multi protocol
stack?
Do we need PCIe
gen6 or still use
gen5 for meeting
application
requirements?
25. Statistics for Multi-Die SoC
• Note the AI Engine
latency spikes
• For multi protocol,
half bandwidth for
each protocol.
• Older gen protocols
are mixed with PCIe 6,
• Lower FLIT size
increases latency.
26. Comparing Different Configurations using
UCIe Interface
All Die Adapters use PCIe 6.0
Die Adapters use PCIe 6.0 and
Streaming Protocols (AXI)
Lower latency when using PCIe 6.0
28. About Mirabilis Design
Engineering Solutions focused on innovation in electronics
Based in Silicon Valley, USA
Development and support centers in US, India, Japan, China and Czech
60 large corporations, research centers and 73 universities as customers
Enabled 250 products in semiconductors, automotive, defense and space
VisualSim Architect is the system simulation and IP for hardware, software and networking
29. Mirabilis Design – Milestones
VisualSim Aerospace
Simulator of the Year
Hardware
Modeling
2003
Company
Incorporated
2005
Modeling Services
1st Customer
2008
Stochastic Modeling
Innovation Award
2010
Integration API
10th customer
2011
Network Modeling
University Program
2013
2015
2018
Best ESL at DAC
2nd at Arm TechCon
2019
VisualSim Automotive
Europe operations
2020
Failure Analysis
Created Asia Team
2021
Best Embedded Systems
Presentation Award – DAC
2021
SysML API
Requirements
2018
New
VisualSim
2022
Best in Show
Embedded World
2023
Communication System
Designer
2022
System Verilog and
UPF/CPF Link
30. VisualSim Architect
Cloud and
Desktop
Multi-simulation
engine- Digital,
Untimed &
Continuous
Library of Systems,
Networks, Semi,
FPGA & Software
Generate statistics,
documentation &
traces
Algorithms
Protocol
AI Insight
Performance
Power
Functional
Stochastic
Scripting
Sim API
Performance
Latency, Throughput, Buffer occupancy
Power
Instant, Average, Cumulative, Heat, Temperature
Battery and power generation sizing
Functionality
Correctness, efficiency and Quality-of-Service
Failure Analysis and Functional Safety
Generate errors and test for compliance
Software Evaluation
Test quality of C++ and impact on system performance
System-level Modeling and Simulation Software
that integrates requirements, exploration & verification
31. Over 500 Systems-Level IP Components
Comprehensive implementation-accurate Library
Traffic
• Distribution
• Sequence
• Trace file
• Instruction
profile
Power
• State power table
• Power management
• Energy harvesters
• Battery
• RegEx operators
SoC Buses
• AMBA and Corelink
• AHB, APB, AXI, ACE,
CHI, CMN600
• Network-on-Chip
• TileLink
System Bus
• PCI / PCI-
X / PCIe
• Rapid IO
• AFDX
• OpenVPX
• VME
• SPI 3.0
• 1553B
ARM
• M-, R-, 7TDMI
• A8, A53, A55, A72, A76,
A77, Neoverse
Custom
Creator
• Script language
• 600 RegEx fn
• Task graph
• Tracer
• C/C++/Java
• Python
Stochastic
• FIFO/LIFO Queue
• Time Queue
• Quantity Queue
• System Resource
• Schedulers
• Cyber Security
Memory
• Memory Controller
• DDR DRAM 2,3,4, 5
• LPDDR 2, 3, 4
• HBM, HMC
• SDR, QDR, RDRAM
Networking
• Ethernet & GiE
• Audio-Video Bridging
• 802.11 and Bluetooth
• 5G
• Spacewire
• CAN-FD
• TTEthernet
• FlexRay
• TSN & IEEE802.1Q
• ARINC 664/AFDX
Interfaces
• Virtual
Channel
• DMA
• Crossbar
• Serial
Switch
• Bridge
Algorithms
• Signal Processing
• Analog
• Antenna
RTOS
• Template
• ARINC 653
• AUTOSAR
Storage
• Flash & NVMe
• Storage Array
• Disk and SATA
• Fibre Channel
• FireWire
Software
• GEM5
• Software
code
integration
• Instruction
trace
• Statistical
software
model
• Task graph
RTL-Like
• Clock, Wire-Delay
• Registers, Latches
• Flip-flop
• ALU and FSM
• Mux, DeMux
• Lookup table
Processors
• GPU, DSP, mP and mC
• RISC-V
• SiFive u74
• Nvidia- Drive-PX
• PowerPC
• X86- Intel and AMD
• DSP- TI and ADI
• MIPS, Tensilica, SH
Reports
• Timing and Buffer
• Throughput/Util
• Ave/peak power
• Statistics
FPGA
• Xilinx- Zynq, Virtex,
Kintex
• Intel-Stratix, Arria
• Microsemi-
Smartfusion
• Programmable logic
template
• Interface traffic
generator
