The quad flat pack no lead or quad flat non-leaded (QFN) is one of the fastest growing package types in the electronics industry today. While the advantages of QFNs are well documented, concerns arise with its reliability and manufacturability. Acceptance of this package, especially in long-life, severe-environment, high-reliability applications, is currently limited. One of the most common drivers for reliability failures is inappropriate adoption of new technologies, such as the case with QFN. In this presentation, we will review and discuss QFN related reliability concerns and challenges, and propose Physics-of-Failure (PoF) based approaches to allow the confident introduction of QFN components into electronics products.
Temperature Cycling and Fatigue in ElectronicsCheryl Tulkoff
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.
CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies.
-1st level interconnects connect the die to a substrate.
-This substrate can be underfilled so there are both global and local CTE mismatches to consider.
-2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a “board level” CTE mismatch.
-Several stress and strain mitigation techniques exist including the use of conformal coating.
The purpose of this presentation is to show that accelerated testing can be successfully used to predict solder joint and plated through hole (PTH) fatigue behavior.
There is a strong interest in understanding the surface mount
assembly requirements of QFN (Quad Flat No-Lead) type
packages due to their rapid industry acceptance.
For more details visit us at Solder.net
Temperature Cycling and Fatigue in ElectronicsCheryl Tulkoff
The majority of electronic failures occur due to thermally induced stresses and strains caused by excessive differences in coefficients of thermal expansion (CTE) across materials.
CTE mismatches occur in both 1st and 2nd level interconnects in electronics assemblies.
-1st level interconnects connect the die to a substrate.
-This substrate can be underfilled so there are both global and local CTE mismatches to consider.
-2nd level interconnects connect the substrate, or package, to the printed circuit board (PCB). This would be considered a “board level” CTE mismatch.
-Several stress and strain mitigation techniques exist including the use of conformal coating.
The purpose of this presentation is to show that accelerated testing can be successfully used to predict solder joint and plated through hole (PTH) fatigue behavior.
There is a strong interest in understanding the surface mount
assembly requirements of QFN (Quad Flat No-Lead) type
packages due to their rapid industry acceptance.
For more details visit us at Solder.net
Test Plan Development using Physics of Failure: The DfR Solutions ApproachCheryl Tulkoff
oProduct test plans are critical to the success of a new product or technology
oStressful enough to identify defects
oShow correlation to a realistic environment
oPoF Knowledge can be used to develop test plans and profiles that can be correlated to the field.
oChange control processes and testing should not be overlooked (reliability engineer needs to stay involved in sustaining).
oOn-going reliability testing can be a useful (but admittedly imperfect) tool.
oPoF Modeling is an excellent tool to help tailor & optimize physical testing plans
Ideal 3D Stacked Die Test - IEEE Semiconductor Wafer Test Workshop SWTW 2013Ira Feldman
My presentation from IEEE SWTW 2013 - For a full description please see my blog:
http://hightechbizdev.com/2013/06/10/ira-feldman-high-technology-business-development-ieee-semiconductor-wafer-test-workshop-2013/
Epitaxy Growth Equipment for More Than Moore Devices Technology and Market Tr...Yole Developpement
Driven by microLED displays and power devices, epitaxy equipment shipment volumes will multiply more than threefold over the next five years.
More info on: https://www.i-micronews.com/products/epitaxy-growth-equipment-for-more-than-moore-devices-technology-and-market-trends-2020/
Practical EMC and EMI Control for Engineers and TechniciansLiving Online
This workshop focuses on the issues of interest to you if you are working in design, operation or maintenance of analog or digital systems involving sensors, data acquisition, process control, cables, signal processing, programmable logic controllers, power distribution, high speed logic etc. The circuit board layout section concentrates on design and layout of circuits and components on a printed circuit board. The overall focus is on useful design and systems issues; not about regulations and standards. The idea is that you will take this material back with you to your work and apply the key principles immediately to your design and troubleshooting challenges.
WHO SHOULD ATTEND?
Electrical and electronic engineers and technicians
Engineers and technicians involved in the design and manufacture of electrical and electronic equipment which produce electromagnetic disturbances and may be susceptible to electromagnetic interference
Engineers and technicians involved with the maintenance and service of electrical and electronic equipment
Instrumentation and control engineers and technicians
Those that need to ensure that goods conform to the required standards
Those involved in the marketing and sale of goods that need to comply with the required standards
MORE INFORMATION: http://www.idc-online.com/content/practical-emc-and-emi-control-engineers-and-technicians-2
Film Properties of ALD SiNx Deposited by Trisilylamine and N2 PlasmaBeneq
Presented by Dr. Markus Bosund
Silicon nitride is a widely used material in semiconductor applications‚ such as gate dielectrics‚ III/V surface passivation and etch stop layer.
PEALD SiNx films have been previously grown using aminosilanes like BTBAS with N2 plasma [1]. These processes generally have a relatively low growth rate of 0.15 - 0.21 Å/cycle and high film quality can only be reached at above 300 °C deposition temperatures. Trisilylamine (TSA) has been previously combined with N2/H2 plasma at 300–400 °C [2]‚ NH3 plasma at 50–400 °C [3] and N2 plasma at 250 – 350 °C [4] to grow PEALD SiNx films. However‚ in these works the low temperature range has remained either inaccessible or uncharted.
In this work we explored the PEALD TSA-N2 plasma process with a wide deposition temperature range from 50 to 350 °C. Focus was given to the electrical and optical properties of the films. A Beneq TFS 200 capacitively coupled hot wall plasma ALD reactor was used at direct plasma mode. It was found that reactor temperature‚ and plasma power and time had the highest impact on the film properties. Film deposition was observed at temperatures as low as 50 °C. Metal insulator semiconductor (MIS) structures were used to determine the breakdown field and leakage current at different temperatures. Films were dipped in 1 % HF solution for etch rate determination.
Roll-to-Roll ALD Coatings for Battery Cell Interfaces at Production ScaleBeneq
ALD/AVS 2022
Presented by D.Sc. Andrew Cook
ALD is an enabling technology for future batteries. ALD technology introduction has been hindered by lack of production scale equipment, but now Beneq R2R ALD technology offers a straightforward scale-up path to mass-production. Beneq has a long experience with R2R ALD on other application areas, and is now applying that know-how to offer R2R ALD solutions for battery manufacturing.
The Effect of Coating and Potting on the Reliability of QFN DevicesCheryl Tulkoff
The lack of a compliant lead structure makes QFN devices more susceptible to PCB warpage related failures:
oMechanical properties of the potting material
oGlass transition temperature (Tg)
oModulus should be specified above and below the Tg
oCTE should be specified above and below the Tg
The design of the housing:
oMay provide a surface to which the potting material can pull against when shrinking causing PCB warpage
oShould be designed to provide as close to a hydrostatic pressure as possible (equal pressure on all sides)
RF GaN Market: Applications, Players, Technology and Substrates 2019 report b...Yole Developpement
GaN RF market growth is fed by military and 5G wireless infrastructure applications.
More information on https://www.i-micronews.com/products/rf-gan-market-applications-players-technology-and-substrates-2019/
Pad Cratering: Prevention, Mitigation and Detection StrategiesCheryl Tulkoff
Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities.
During this tutorial, you'll learn about the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.
Prognostics and Health Management (PHM) is being widely applied in many industrial systems to ensure high system availability over their life cycle. This web seminar will present key steps of PHM: data processing, feature extraction, fault diagnostics, and failure prognostics. The fundamental algorithms, models and techniques for each step will be discussed. Time domain, frequency domain and time frequency data analysis are introduced, and the corresponding feature extraction technologies presented. Mode-based and data-driven-based approaches are described in fault diagnostics and failure prognostics.
Test Plan Development using Physics of Failure: The DfR Solutions ApproachCheryl Tulkoff
oProduct test plans are critical to the success of a new product or technology
oStressful enough to identify defects
oShow correlation to a realistic environment
oPoF Knowledge can be used to develop test plans and profiles that can be correlated to the field.
oChange control processes and testing should not be overlooked (reliability engineer needs to stay involved in sustaining).
oOn-going reliability testing can be a useful (but admittedly imperfect) tool.
oPoF Modeling is an excellent tool to help tailor & optimize physical testing plans
Ideal 3D Stacked Die Test - IEEE Semiconductor Wafer Test Workshop SWTW 2013Ira Feldman
My presentation from IEEE SWTW 2013 - For a full description please see my blog:
http://hightechbizdev.com/2013/06/10/ira-feldman-high-technology-business-development-ieee-semiconductor-wafer-test-workshop-2013/
Epitaxy Growth Equipment for More Than Moore Devices Technology and Market Tr...Yole Developpement
Driven by microLED displays and power devices, epitaxy equipment shipment volumes will multiply more than threefold over the next five years.
More info on: https://www.i-micronews.com/products/epitaxy-growth-equipment-for-more-than-moore-devices-technology-and-market-trends-2020/
Practical EMC and EMI Control for Engineers and TechniciansLiving Online
This workshop focuses on the issues of interest to you if you are working in design, operation or maintenance of analog or digital systems involving sensors, data acquisition, process control, cables, signal processing, programmable logic controllers, power distribution, high speed logic etc. The circuit board layout section concentrates on design and layout of circuits and components on a printed circuit board. The overall focus is on useful design and systems issues; not about regulations and standards. The idea is that you will take this material back with you to your work and apply the key principles immediately to your design and troubleshooting challenges.
WHO SHOULD ATTEND?
Electrical and electronic engineers and technicians
Engineers and technicians involved in the design and manufacture of electrical and electronic equipment which produce electromagnetic disturbances and may be susceptible to electromagnetic interference
Engineers and technicians involved with the maintenance and service of electrical and electronic equipment
Instrumentation and control engineers and technicians
Those that need to ensure that goods conform to the required standards
Those involved in the marketing and sale of goods that need to comply with the required standards
MORE INFORMATION: http://www.idc-online.com/content/practical-emc-and-emi-control-engineers-and-technicians-2
Film Properties of ALD SiNx Deposited by Trisilylamine and N2 PlasmaBeneq
Presented by Dr. Markus Bosund
Silicon nitride is a widely used material in semiconductor applications‚ such as gate dielectrics‚ III/V surface passivation and etch stop layer.
PEALD SiNx films have been previously grown using aminosilanes like BTBAS with N2 plasma [1]. These processes generally have a relatively low growth rate of 0.15 - 0.21 Å/cycle and high film quality can only be reached at above 300 °C deposition temperatures. Trisilylamine (TSA) has been previously combined with N2/H2 plasma at 300–400 °C [2]‚ NH3 plasma at 50–400 °C [3] and N2 plasma at 250 – 350 °C [4] to grow PEALD SiNx films. However‚ in these works the low temperature range has remained either inaccessible or uncharted.
In this work we explored the PEALD TSA-N2 plasma process with a wide deposition temperature range from 50 to 350 °C. Focus was given to the electrical and optical properties of the films. A Beneq TFS 200 capacitively coupled hot wall plasma ALD reactor was used at direct plasma mode. It was found that reactor temperature‚ and plasma power and time had the highest impact on the film properties. Film deposition was observed at temperatures as low as 50 °C. Metal insulator semiconductor (MIS) structures were used to determine the breakdown field and leakage current at different temperatures. Films were dipped in 1 % HF solution for etch rate determination.
Roll-to-Roll ALD Coatings for Battery Cell Interfaces at Production ScaleBeneq
ALD/AVS 2022
Presented by D.Sc. Andrew Cook
ALD is an enabling technology for future batteries. ALD technology introduction has been hindered by lack of production scale equipment, but now Beneq R2R ALD technology offers a straightforward scale-up path to mass-production. Beneq has a long experience with R2R ALD on other application areas, and is now applying that know-how to offer R2R ALD solutions for battery manufacturing.
The Effect of Coating and Potting on the Reliability of QFN DevicesCheryl Tulkoff
The lack of a compliant lead structure makes QFN devices more susceptible to PCB warpage related failures:
oMechanical properties of the potting material
oGlass transition temperature (Tg)
oModulus should be specified above and below the Tg
oCTE should be specified above and below the Tg
The design of the housing:
oMay provide a surface to which the potting material can pull against when shrinking causing PCB warpage
oShould be designed to provide as close to a hydrostatic pressure as possible (equal pressure on all sides)
RF GaN Market: Applications, Players, Technology and Substrates 2019 report b...Yole Developpement
GaN RF market growth is fed by military and 5G wireless infrastructure applications.
More information on https://www.i-micronews.com/products/rf-gan-market-applications-players-technology-and-substrates-2019/
Pad Cratering: Prevention, Mitigation and Detection StrategiesCheryl Tulkoff
Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities.
During this tutorial, you'll learn about the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable.
Prognostics and Health Management (PHM) is being widely applied in many industrial systems to ensure high system availability over their life cycle. This web seminar will present key steps of PHM: data processing, feature extraction, fault diagnostics, and failure prognostics. The fundamental algorithms, models and techniques for each step will be discussed. Time domain, frequency domain and time frequency data analysis are introduced, and the corresponding feature extraction technologies presented. Mode-based and data-driven-based approaches are described in fault diagnostics and failure prognostics.
Brochure on our CEBIT sensor family, all part of TETRADYN\'s superior offering, outpacing what DHS and TSA are doing, outperforming what BAE, SAIC, ARA, Lockheed, Smiths and others are selling at 10x the cost.
This report presents an in-depth analysis about the promising technology LTE taking into account not only technology aspects but also business aspects. In detail, it points out the key drivers that are continuously changing the Telecom market and analyzes LTE and its evolution, LTE Advanced, as technological response to the emerging market needs. In addition, it provides an overview of current trends in spectrum allocation, global status of the LTE ecosystem and worldwide initiatives to date. Finally, it explores LTE business case implications for incumbent and greenfield mobile operators through an accurate scenario and sensitivity analysis.
If you want to know more about it, please visit http://payment.witech.it/report.php
TowerLabs: Accelerating Adoption of Green Building Technologies for CondosToronto 2030 District
Jamie James, Founder of TowerLabs @ MaRS showcases some of their research and the technology they are incubating to accelerate the uptake of cleantech in the condo sector.
On Duty Cycle Concept in Reliability - Definitions, Pitfalls, and Clarifications
By Frank Sun, Ph.D.
Product Reliability Engineering
HGST, a Western Digital company
For ASQ Reliability Division Webinar
August 14, 2014
Objectives
To provide an introduction to the statistical analysis of
failure time data
To discuss the impact of data censoring on data analysis
To demonstrate software tools for reliability data analysis
Organization
Reliability definition
Characteristics of reliability data
Statistical analysis of censored reliability data
Objectives
To understand Weibull distribution
To be able to use Weibull plot for failure time analysis and
diagnosis
To be able to use software to do data analysis
Organization
Distribution model
Parameter estimation
Regression analysis
With the increase in global competition, more and more costumers consider reliability as one of their primary deciding factors, when purchasing new products. Several companies have invested in developing their own Design for Reliability (DFR) processes and roadmaps in order to be able to meet those requirements and compete in today’s market. This presentation will describe the DFR roadmap and how to effectively use it to ensure the success of the reliability program by focusing on the following DFR elements.
Improved QFN Reliability Process by John Ganjei. John will talk about the improvements in the reliability process in this webinar.
It is free to attend - see www.reliabilitycalendar.org/webinars/ to register for upcoming events.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
Key Trends Shaping the Future of Infrastructure.pdfCheryl Hung
Keynote at DIGIT West Expo, Glasgow on 29 May 2024.
Cheryl Hung, ochery.com
Sr Director, Infrastructure Ecosystem, Arm.
The key trends across hardware, cloud and open-source; exploring how these areas are likely to mature and develop over the short and long-term, and then considering how organisations can position themselves to adapt and thrive.
The Art of the Pitch: WordPress Relationships and SalesLaura Byrne
Clients don’t know what they don’t know. What web solutions are right for them? How does WordPress come into the picture? How do you make sure you understand scope and timeline? What do you do if sometime changes?
All these questions and more will be explored as we talk about matching clients’ needs with what your agency offers without pulling teeth or pulling your hair out. Practical tips, and strategies for successful relationship building that leads to closing the deal.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
LF Energy Webinar: Electrical Grid Modelling and Simulation Through PowSyBl -...DanBrown980551
Do you want to learn how to model and simulate an electrical network from scratch in under an hour?
Then welcome to this PowSyBl workshop, hosted by Rte, the French Transmission System Operator (TSO)!
During the webinar, you will discover the PowSyBl ecosystem as well as handle and study an electrical network through an interactive Python notebook.
PowSyBl is an open source project hosted by LF Energy, which offers a comprehensive set of features for electrical grid modelling and simulation. Among other advanced features, PowSyBl provides:
- A fully editable and extendable library for grid component modelling;
- Visualization tools to display your network;
- Grid simulation tools, such as power flows, security analyses (with or without remedial actions) and sensitivity analyses;
The framework is mostly written in Java, with a Python binding so that Python developers can access PowSyBl functionalities as well.
What you will learn during the webinar:
- For beginners: discover PowSyBl's functionalities through a quick general presentation and the notebook, without needing any expert coding skills;
- For advanced developers: master the skills to efficiently apply PowSyBl functionalities to your real-world scenarios.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
Let's dive deeper into the world of ODC! Ricardo Alves (OutSystems) will join us to tell all about the new Data Fabric. After that, Sezen de Bruijn (OutSystems) will get into the details on how to best design a sturdy architecture within ODC.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
2. ASQ Reliability Division
English Webinar Series
One of the monthly webinars
on topics of interest to
reliability engineers.
To view recorded webinar (available to ASQ Reliability
Division members only) visit asq.org/reliability
To sign up for the free and available to anyone live
webinars visit reliabilitycalendar.org and select English
Webinars to find links to register for upcoming events
http://reliabilitycalendar.org/The_Reli
ability_Calendar/Webinars_‐
_English/Webinars_‐_English.html
3. Manufacturing and Reliability
Challenges With QFN (Quad Flat
No Leads)
Cheryl Tulkoff ASQ Reliability Society Webinar March 10, 2011
1
4. Instructor Biography
o Cheryl Tulkoff has over 17 years of experience in electronics manufacturing
with an emphasis on failure analysis and reliability. She has worked throughout
the electronics manufacturing life cycle beginning with semiconductor fabrication
processes, into printed circuit board fabrication and assembly, through
functional and reliability testing, and culminating in the analysis and evaluation
of field returns. She has also managed no clean and RoHS-compliant conversion
programs and has developed and managed comprehensive reliability
programs.
o Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia
Tech. She is a published author, experienced public speaker and trainer and a
Senior member of both ASQ and IEEE. She holds leadership positions in the IEEE
Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR
(Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE
ASTR workshop for four years and is also an ASQ Certified Reliability
Engineer.
o She has a strong passion for pre-college STEM (Science, Technology,
Engineering, and Math) outreach and volunteers with several organizations that
specialize in encouraging pre-college students to pursue careers in these fields.
2
5. DfR Solutions works with companies and individuals throughout the life cycle
of a product, lending a guiding hand on quality, reliability and durability
(QRD) issues that allows your staff to focus on creativity and ideas.
Our expertise in the emerging science of Electrical and Electronics Reliability
Physics provides crucial insights and solutions early in product design,
development and test throughout manufacturing, and even into the field.
3
6. Who is DfR Solutions?
o We use Physics-of-Failure
(PoF) and Best Practices
expertise to provide knowledge-
based strategic quality and
reliability solutions to the
electronics industry
o Technology Insertion
o Design
o Manufacturing and Supplier Selection
o Product Validation and Accelerated Testing
o Root-Cause Failure Analysis & Forensics Engineering
o Unique combination of expert consultants and state-of-the-art laboratory
facilities
4
7. DfR Clients
Military / Avionics / Space Server / Telecom Industrial / Power
o Rockwell Collins o Lucent Technologies Schlumberger
o DRS o Sun Microsystems Copeland
o Honeywell o Cisco Systems Tennant
o Applied Data Systems o Artesyn Communications Rosemount
o Mercury Computers o Corvis Communications Branson
o Digital Receiver Technology o Huawei (China) Computer Process Controls
o Hamilton Sundstrand o Airgo Networks ASCO Power
o Kato Engineering o Verigy ASCO Valve
o Thales Communications o Antares ATT Astec
o L-3 Communications o Enterasys Liebert
o Innovative Concepts o True Position Avansys
o Sandia National Labs o HiFN Tyco Electronics
o Crane (Eldec) o Cedar Point Rainbird
o ViaSat o Optics1 MicroMotion
o Eaton o Tropos Networks Siemens
Barco
Automotive / Commercial Vehicle Consumer / Appliance Calex
o General Motors o Fujitsu (Japan) Western Geco (Norway)
o Caterpillar o Dell Computers General Electric
o Panasonic Automotive o Samsung (Korea) Ingersoll Rand
o Hella Automotive o LG Electronics (Korea) Fusion UV
o LG Electronics o Tubitak Mam (Turkey) Numatics
o Tyco Electronics o Insinkerator Durotech
o TRW o White Rodgers Danaher Motion
o MicroHeat o Emerson Appliance Controls TallyGencom
o Therm-O-Disc Vision Research
Medical o NMB Technologies Olympus NDT
o Biotronik o Shure
o Philips Medical o Handi-Quilt Components
o Abbott Laboratories o Xerox Fairchild Semiconductor
o Tecan Systems Maxtek
o Neuropace Portables Samsung ElectroMechanics (Korea)
o Inter-Metro o RSA Security Pulse
o Welch Allyn o Handheld Teradyne
o Guidant / Boston Scientific o Kyocera Amphenol
o Beckman Coulter o LG Electronics AVX
o Applied Biosystems Anadigics
o Cardinal Health Contract Manufacturers Kemet
o Medtronic o Daeduck (Korea) NIC
o Cardiac Science o Gold Circuit Electronics (Taiwan) Graftech
o Engent International Rectifier
o EIT
5
8. Selected Publications
o Epidemiological Study of SnAgCu Solder: Benchmarking Results from Accelerated Life Testing
o What I Don„t Know That I Don„t Know: Things to Worry About with the Pb-Free Transition
o Long-term Reliability of Pb-free Electronics
o Robustness of Ceramic Capacitors Assembled with Pb-Free Solder
o Failure Mechanisms in LED and Laser Diodes
o Microstructure and Damage Evolution in Pb-Free Solder Joints
o Improved Methodologies for Identifying Root-Cause of Printed Board Failures
o Reliability of Pressure Sensitive Adhesive Tapes for Heat Sink Attachment
o Failure Mechanisms in Electronic Products at High Altitudes
o Determining the Lifetime of Conductive Adhesive / Solder Plated Interconnections
o Issues in Long-Term Storage of Plastic Encapsulated Microcircuits
o Effect of PWB Plating on the Microstructure and Reliability of SnAgCu Solder Joints
o A Demonstration of Virtual Qualification for the Design of Electronic Hardware
o Solder Failure Mechanisms in Single-Sided Insertion-Mount Printed Wiring Boards
o Finite Element Modeling of Printed Circuit Boards for Structural Analysis
6
9. DfR Resources and Equipment
Electrical Material Analysis
o Oscilloscopes o X-ray
o Digital o Acoustic Microscopy
o Analog o Infrared Camera
o Curve Tracers o Metallographic Preparation
o Digital
o Stereoscope
o Analog
o Optical Microscope
o Partial Discharge Detector
o Scanning Electron Microscope
o Capacitance Meters
o Energy Dispersive Spectroscopy
o Low Resistance Meters
o Ion Chromatography
o High Resistance Meters
o FTIR (Solid / Film / Liquid)
o High Voltage Power Supplies (Hi-Pot)
o Thermomechanical Analyzer
o SQUID Microscopy
Testing
o Xray Diffraction
o HALT
o Focused Ion Beam Imaging
o Temperature Cycling
o XPS
o Thermal Shock
o Temperature/Humidity
Other
o Vibration
o Circuit Simulation
o Mechanical Shock / Drop Tower
o Finite Element Analysis (FEA)
o Mixed Flowing Gas
o Computational Fluid Dynamics
o Salt Spray
o Reliability Prediction (Physics of Failure)
o Capacitor Testing (Ripple Current)
7
10. Knowledge and Education (Website)
o Let your staff learn
all day / every day
E-LEARNING
o Scholarly articles
o Technical white papers
o Case studies
o Reliability calculators
o Online presentations
8
8
11. QFN as a ‘Next Generation’ Technology
o What is „Next Generation‟ Technology?
o Materials or designs currently
being used, but not widely adopted
(especially among hi-rel manufacturers)
o Carbon nanotubes are not
„Next Generation‟
o Not used in electronic applications
o Ball grid array is not
„Next Generation‟
o Widely adopted
9
9
12. Introduction (cont.)
o Why is knowing about „Next
Generation‟ Technologies important?
o These are the technologies that you
or your supply chain will use to
improve your product
o Cheaper, Faster, Stronger,
„Environmentally-Friendly‟, etc.
o And sooner then you think!
10
10
13. Reliability and Next Generation Technologies
o One of the most common drivers for failure is
inappropriate adoption of new technologies
o The path from consumer (high volume, short lifetime) to high rel is
not always clear
o Obtaining relevant information
can be difficult
o Information is often segmented
o Focus on opportunity, not risks
o Can be especially true for
component packaging
o BGA (Ball Grid Array), flip chip, QFN (Quad Flat No Lead)
11
11
14. Component Packaging
o Most of us have little influence over component packaging
o Most devices offer only one or two packaging styles
o Why should you care?
o Poor understanding of component qualification procedures
o Who tests what and why?
12
12
15. Component Testing
o Reliability testing performed by component manufacturers
is driven by JEDEC
o JESD22 series (A & B)
o Focus is almost entirely on die, packaging, and 1st level
interconnections (wire bond, solder bump, etc.)
o Only focus on 2nd level interconnects (solder joints) is
JESD22-B113 Cyclic Bend Test
o Driven by cell phone industry
o They have little interest in thermal cycling or vibration!
13
13
16. 2nd Level Interconnect Reliability
o IPC has attempted to rectify this through
IPC-9701
o Two problems
o Adopted by OEMs; not by component manufacturers
o Application specific; you have to tell them the application
(your responsibility, not theirs)
o The result
o An increasing incidence of solder wearout in next generation
component packaging
14
14
17. Solder Wearout in Next Generation Packaging
Performance Needs
o Higher frequencies and data transfer rates
o Lower resistance-capacitance (RC) constants
o Higher densities
o More inside less plastic
o Lower voltage, but higher current
o Joule heating is I2R
o Has resulted in less robust package designs
15
15
18. Solder Wearout (cont.)
o Elimination of leaded devices
o Provides lower resistance-capacitance (RC) and higher package
densities
o Reduces compliance
Cycles to failure QFP: >10,000 BGA: 3,000 to 8,000
-40 to 125C
CSP / Flip Chip: <1,000 QFN: 1,000 to 3,000
16
16
19. Solder Wearout (cont.)
o Design change: More silicon, less plastic
o Increases mismatch in coefficient of thermal expansion
(CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR QFN TYPE PACKAGES,
Ahmer Syed and WonJoon Kang, Amkor Technology.
17
17
20. Solder Wearout (cont.)
o Hotter devices
o Increases change in temperature (DT)
10000
Characteristic Life (Cycles to Failure)
9000
tf = DTn 8000
7000
6000
n = 2 (SnPb) 5000
n = 2.3 (SnNiCu) 4000
n = 2.7 (SnAgCu) 3000
2000
1000
0
0 50 100 150 200
o
Change in Temperature ( C)
18
18
21. Industry Response to SJ Wearout?
o JEDEC
o Specification body for component manufacturers
o JEDEC JESD47
o Guidelines for new component qualification
o Requires 2300 cycles of 0 to 100C
o Testing is often done on thin boards
o IPC
o Specification body for electronic OEMs
o IPC 9701
o Recommends 6000 cycles of 0 to 100C
o Test boards should be similar thickness as
actual design
19
19
22. BIG PROBLEM
o JEDEC requirements are 60% less than IPC
o Testing on a thin board can extend lifetimes by 2X to 4X
o What does this mean?
o The components you buy may only survive
500 cycles of 0 to 100C
o What must you do?
o Components at risk must be subjected to PoF-based (Physics of
Failure) reliability analysis
20
20
23. Quad Flat Pack No Leads or
Quad Flat No Leads
(QFN)
21
21
24. QFN: What is it?
o Quad Flat Pack No Lead or Quad Flat Non-Leaded
o „The poor man‟s ball grid array‟
o Also known as
o Leadframe Chip Scale Package (LF-CSP)
o MicroLeadFrame (MLF)
o Others (MLP, LPCC, QLP, HVQFN, etc.)
o Overmolded leadframe with bond pads exposed on the bottom and
arranged along
the periphery of the package
o Developed in the early to
mid-1990‟s by Motorola,
Toshiba, Amkor, etc.
o Standardized by JEDEC/EIAJ in
late-1990‟s
o Fastest growing package type
22
22
25. QFN Advantages: Size and Cost
o Smaller, lighter and thinner than comparable leaded
packages
o Allows for greater functionality per volume
o Reduces cost
o Component manufacturers: More ICs per frame
o OEMs: Reduced board size
o Attempts to limit the footprint of lower I/O devices have
previously been stymied for cost reasons
o BGA materials and process too expensive
23
23
26. Advantages: Manufacturability
o Small package without placement and solder printing
constraints of fine pitch leaded devices
o No special handling/trays to avoid bent or non planar pins
o Easier to place correctly on PCB pads than fine pitch QFPs,
TSOPs, etc.
o Larger pad geometry makes for simpler solder paste printing
o Less prone to bridging defects when proper pad design and
stencil apertures are used.
o Reduced popcorning moisture sensitivity issues – smaller
package
24
24
27. Advantages: Thermal Performance
o More direct thermal path with larger area
o Die Die Attach Thermal Pad
Solder Board Bond Pad
o qJa for the QFN is about half of a
leaded counterpart (as per JESD-51)
o Allows for 2X increase in power dissipation
25
25
28. Advantages: Inductance
o At higher operating frequencies, inductance of the gold
wire and long lead-frame traces will affect performance
o Inductance of QFN is half its leaded counterpart because
it eliminates gullwing leads and shortens wire lengths
Popular for
RF Designs
http://ap.pennnet.com/display_article/153955/36/ARTCL/none/none/1/The-back-end-process:-Step-9-QFN-Singulation/
26
26
29. QFN: Why Not?
o QFN is a „next generation‟ technology for non-consumer
electronic OEMs due to concerns with
o Manufacturability
o Compatibility with other OEM processes
o Reliability
o Acceptance of this package, especially in long-life, severe
environment, high-rel applications, is currently limited as a
result
27
27
30. QFN Manufacturability: Bond Pads
o Non Solder Mask Defined Pads Preferred (NSMD)
o Copper etch process has tighter process control than solder mask process
o Makes for more consistent, strong solder joints since solder bonds to both tops and sides of pads
o Use solder mask defined pads (SMD) with care
o Can be used to avoid bridging between pads, especially between thermal and signal pads.
o Pads can grow in size quite a bit based on PCB mfg capabilities
o Can lose solder volume and standoff height through vias in thermal pads
o May need to tent, plug, or cap vias to keep sufficient paste volume
o Reduced standoff weight reduces cleanability and pathways for flux outgassing
o Increased potential for contamination related failures
o Tenting and plugging vias is often not well controlled and can lead to placement and chemical
entrapment issues
o Exercise care with devices placed on opposing side of QFN
o Can create placement issues if solder “bumps” are created in vias
o Can create solder short conditions on the opposing device
o Capping is a more robust, more expensive process that eliminates these concerns
28
28
32. Bond Pads (cont.)
o Extend bond pad 0.2 – 0.3 mm beyond
package footprint
o May or may not solder to cut edge
o Allows for better visual inspection
o Really need X-ray for best results
o Allows for verification of bridging,
adequate solder coverage and
void percentage
o Note: Lacking in good criteria
for acceptable voiding
30
30
33. Manufacturability: Stencil Design
o Stencil thickness and aperture design can be crucial for
manufacturability
o Excessive amount of paste can induce
float, lifting the QFN off the board
o Excessive voiding can also be induced
through inappropriate stencil design
o Follow manufacturer‟s guidelines
o Goal is 2-3 mils of solder thickness
o Rules of thumb (thermal pad)
o Ratio of aperture/pad ~0.5:1
o Consider multiple, smaller apertures
(avoid large bricks of solder paste)
o Reduces propensity for solder balling
31
31
34. Manufacturability: Stencil Design
Datasheet says solder paste coverage should be 40-80%
Drawing supplied in same datasheet is for 26% coverage
32
32
35. Manufacturability: Reflow & Moisture
o QFN solder joints are more susceptible to dimensional changes
o Case Study: Military supplier experienced solder separation under QFN
o QFN supplier admitted that the package was more susceptible to moisture
absorption that initially expected
o Resulted in transient swelling during reflow soldering
o Induced vertical lift, causing solder separation
o Was not popcorning
o No evidence of cracking or delamination in component package
33
33
36. Corrective Actions: Manufacturing
Verify good MSL handling/procedures
Spec and confirm - Reflow
o
Room temperature to preheat (max 2-3 C/sec)
Preheat to at least 150oC
Preheat to maximum temperature (max 4-5oC/sec)
o
Cooling (max 2-3 C/sec)
In conflict with profile from J-STD-020C (6oC/sec)
Make sure assembly is less than 60oC before cleaning
34
34
39. Manufacturability: QFN Joint Inspection
Convex or absence of fillet highly likely
•Etching of leadframe can prevent
pad from reaching edge of package
•Edge of bond pad is not plated for
solderability
37
37
40. Manufacturability: QFN Joint Inspection
o A large convex fillet is often an indication of issues
o Poor wetting under the QFN
o Tilting due to excessive solder paste under the thermal pad
o Elevated solder surface tension, from insufficient solder paste
under the thermal pad, pulling the package down
38
38
41. Manufacturability: Rework
o Can be difficult to replace a package and get adequate
soldering of thermal / internal pads.
o Mini-stencils, preforms, or rebump techniques can be used to get
sufficient solder volume
o Not directly accessible with soldering iron and wire
o Portable preheaters used in conjunction with soldering iron can
simplify small scale repair processes
o Close proximity with capacitors often requires adjacent
components to be resoldered / replaced as well
39
39
42. Manufacturability: Board Flexure
o Area array devices are known to have board flexure
limitations
o For SAC attachment, maximum microstrain can be as low as
500 ue
o QFN has an even lower level of compliance
o Limited quantifiable knowledge in this area
o Must be conservative during board build
o IPC is working on a specification similar to BGAs
40
40
43. Pad Cratering
Cracking initiating within the laminate during a dynamic mechanical event
In circuit testing (ICT), board depanelization, connector insertion, shock and
vibration, etc.
G. Shade, Intel (2006)
41 41
41
44. Pad Cratering
Intel (2006)
o Drivers
o Finer pitch components
o More brittle laminates
o Stiffer solders (SAC vs. SnPb)
o Presence of a large heat sink
o Difficult to detect using
standard procedures
o X-ray, dye-n-pry, ball shear, and
ball pull
42 42
42
45. Solutions to Pad Cratering
o Board Redesign
o Solder mask defined vs. non-solder mask defined
o Limitations on board flexure
o 750 to 500 microstrain, Component dependent
o More compliant solder
o SAC305 is relatively rigid, SAC105 and SNC are possible
alternatives
o New acceptance criteria for laminate materials
o Intel-led industry effort
o Attempting to characterize laminate material using high-speed
ball pull and shear testing, Results inconclusive to-date
o Alternative approach
o Require reporting of fracture toughness and elastic modulus
43 43
43
46. Reliability: Thermal Cycling
o Order of magnitude reduction in time to
failure from QFP
o 3X reduction from BGA QFP: >10,000
o Driven by die / package ratio
o 40% die; tf = 8K cycles (-40 / 125C)
o 75% die; tf = 800 cycles (-40 / 125C)
o Driven by size and I/O#
BGA: 3,000 to 8,000
o 44 I/O; tf = 1500 cycles (-40 / 125C)
o 56 I/O; tf = 1000 cycles (-40 / 125C)
o Very dependent upon solder bond with
thermal pad
QFN: 1,000 to 3,000
44
44
47. Thermal Cycling: Conformal Coating
o Care must be taken when using conformal coating over QFN
o Coating can infiltrate under the QFN
o Small standoff height allows coating to cause lift
o Hamilton Sundstrand found a significant reduction in time to failure (-
55 / 125C)
o Uncoated: 2000 to 2500 cycles
o Coated: 300 to 700 cycles
o Also driven by solder joint
sensitivity to tensile stresses
o Damage evolution is far
higher than for shear stresses
Wrightson, SMTA Pan Pac 2007
45
45
48. Reliability: Bend Cycling
o Low degree of compliance
and large footprint can
also result in issues during
cyclic flexure events
o Example: IR tested a
5 x 6mm QFN to
JEDEC JESD22-B113
o Very low beta (~1)
o Suggests brittle fracture, possible along the interface
46
46
49. Reliability: Dendritic Growth / Electrochemical Migration
o Large area, multi-I/O and low standoff can trap flux
under the QFN
o Processes using no-clean flux should be requalified
o Particular configuration could result in weak organic acid
concentrations above maximum (150 – 200 ug/in2)
o Those processes not using no-clean flux will likely
experience dendritic growth without modification of
cleaning process
o Changes in water temperature
o Changes in saponifier
o Changes to impingement jets
47
47
50. Dendritic Growth (cont.)
o The electric field strength between adjacent conductors is a strong
driver for dendritic growth
o Voltage / distance
o Digital technology typically has a maximum field strength of
0.5 V/mil
o TSSOP80 with 3.3VDC power and 16 mil pitch
o Previous generation analog / power technology had a maximum field
strength of 1.6 V/mil
o SOT23 with 50VDC power and 50 mil pitch
o Introduction of QFN has resulted in electric fields as high as
3.5 V/mil
o 24VDC and 16 mil pitch
48
48
51. Dendritic Growth (cont.)
o Component manufacturers are increasingly aware of this
issue and separate power and ground
o Linear Technologies (left) has strong separation power and
ground
o Intersil (right) has power and ground on adjacent pins
49
49
52. Electro-Chemical Migration: Details
elapsed time
o Insidious failure mechanism 12 sec.
o Self-healing: leads to large number
of no-trouble-found (NTF)
o Can occur at nominal voltages (5 V)
and room conditions (25C, 60%RH)
o Due to the presence of contaminants
on the surface of the board
o Strongest drivers are halides (chlorides and bromides)
o Weak organic acids (WOAs) and polyglycols can also lead to drops in the
surface insulation resistance
o Primarily controlled through controls on cleanliness
o Minimal differentiation between existing Pb-free solders, SAC and SnCu,
and SnPb
o Other Pb-free alloys may be more susceptible (e.g., SnZn)
50 50
50
54. QFN: Risk Mitigation
o Assess manufacturability
o DOE on stencil design
o Degree of reflow profiling
o Control of board flexure
o Dual row QFN is especially difficult
o Cleanliness is critical
o Assess reliability
o Ownership of 2nd level interconnect
is often lacking
o Extrapolate to needed field reliability
o Some companies have reballed QFN
to deal with concerns
52
52
56. Disclaimer & Confidentiality
o ANALYSIS INFORMATION
This report may include results obtained through analysis performed by DfR Solutions‟
Sherlock software. This comprehensive tool is capable of identifying design flaws and
predicting product performance. For more information, please contact
DfRSales@dfrsolutions.com.
o DISCLAIMER
DfR represents that a reasonable effort has been made to ensure the accuracy and
reliability of the information within this report. However, DfR Solutions makes no
warranty, both express and implied, concerning the content of this report, including, but
not limited to the existence of any latent or patent defects, merchantability, and/or
fitness for a particular use. DfR will not be liable for loss of use, revenue, profit, or any
special, incidental, or consequential damages arising out of, connected with, or
resulting from, the information presented within this report.
o CONFIDENTIALITY
The information contained in this document is considered to be proprietary to DfR
Solutions and the appropriate recipient. Dissemination of this information, in whole or
in part, without the prior written authorization of DfR Solutions, is strictly prohibited.
From all of us at DfR Solutions, we would like to thank you for choosing us as your
partner in quality and reliability assurance. We encourage you to visit our website for
information on a wide variety of topics.
Best Regards,
Dr. Craig Hillman, CEO
54