CMOS differential pairs are used for finding the difference between two voltage signal.But if not properly implemented then it will also cause amplification of common voltage.As well as to work as differential pair voltage should also be in proper range so that it should operate in steady state i.e. as amplifier.

1. Presented by
SHANTANU(ee1200232)
Basic Differential Pair
(Qualitative analysis)
Date 08/03/2016 Reference : Design of Analog CMOS Integrated Circuits by Behzad Razavi

2. Electronic device used to amplify the difference between two signal and
suppress common voltage (if any) between two i.e. V0 = A(V2 -V1)
However if signal have different common level or if parameters of transistor used
are different then output gets modified to
V0 = A2V2-A1V1 = Ad(V1 + V2)/2 + Ac(V2-V1)
Most widely used building block in analog integrated circuit as it is main
component of opamp
Can also be operated as single input differential output , single input single
output , double input single output
Differential Pair
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3. Coupling between wires having analog and digital signal(clock)
respectively
Noise Corrupted biasing voltage
Why Differential Pair
08/03/2016
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4. Sensitivity towards the CM level of input signal
For lower CM level the circuit may turn off for smaller values of
V1/V2
Change in CM level of signal changes bias currents as well as
transconductance(gm) and hence gain of circuit
Differential pair operation
3

5. Thus Its important to make sure that output should have minimum
dependence on input CM level
Ensures that sum of two currents remains same independent of CM level
Cont…
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6. Disadvantages
 Increased area : Circuit occupies twice as much area as single ended
operation
 Increased cost, power consumption
However practically it has been observed that numerous advantages of
differential operation overweigh its cons.
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7. The main advantage of using MOSFETs for a differential pair
compared to BJTs is the nearly infinite input impedance, while
the disadvantage is generally lower differential gain
BJT Vs MOSFET Differential Pair
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8. Study of variation of output w.r.t. input signal
Qualitative analysis
1 2 1 2
2 1 2
1 2 1 2
2 1 2
1 2 1 2
1 2 1
1
,
2
,
2 2
3
,
in in
D ss DD DD SS D
in in
ss ss
D DD D
in in
D ss DD DD SS D
Case V V M off M on
I I V V and V V I R
Case V V M onM on
I I
I V V V R
Case V V M on M off
I I V V and V V I R
  
   
  
   
  
   
7

9. From the previous slide we can see the output voltages are well
defined within limit as well independent of input CM level
Small signal gain is maximum at Vin1 =Vin2 i.e. circuit becomes more
non linear as input voltage swing increases.
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10. As we know adding current source to common emitter node suppress the
effect of variation in CM level on operation of M1,M2 and output level
But for proper operation of device it have certain limit
Current through M3 should be constant
Case 1- When Vin is low => No current in circuit
Case 2- When Vin > Vgs1 + (Vgs3 - Vth)
Case 3- When Vin > VDD – RD(ISS/2) + Vth
CM level variation
9