This document provides an overview of VLSI design for a course. It discusses topics including CMOS transistors and logic gates, VLSI levels of abstraction, the VLSI design process, design styles like full custom and ASIC, and trends like Moore's Law. The roadmap outlines topics to be covered like CMOS processing, combinational and sequential circuit design, and a design project to complete a chip. Course objectives are listed relating to VLSI analysis, layout design, and system design skills.

1. Lecture 1 Introduction to VLSI Design Pradondet Nilagupta [email_address] Department of Computer Engineering Kasetsart University

13. June 9, 2009 204424 Digital Design Automation Silicon Manufacturing Alternatives Standard Components Application Specific ICs Fixed Application Application by Programming Semi Custom Silicon Compilation Full Custom Logic Families Hardware Programming (MASK) Software Programming TTL CMOS PLA ROM Microprocessor EPROM,EEPROM PLD

14. VLSI Technology - CMOS Transistors June 9, 2009 204424 Digital Design Automation 2002: L=130nm 2003: L=90nm 2005: L=65nm? Key feature: transistor length L

17. CMOS Inverter Operation June 9, 2009 204424 Digital Design Automation

18. CMOS Logic Example - What’s This? June 9, 2009 204424 Digital Design Automation P Transistors on when gate “L” N Transistors on when gate “H”

19. VLSI Levels of Abstraction June 9, 2009 204424 Digital Design Automation Specification (what the chip does, inputs/outputs) Architecture major resources, connections Register-Transfer logic blocks, FSMs, connections Circuit transistors, parasitics, connections Layout mask layers, polygons Logic gates, flip-flops, latches, connections

30. Microprocessor Trends (Intel) June 9, 2009 204424 Digital Design Automation Source: http://www.intel.com/pressroom/kits/quickreffam.htm

31. Microprocessor Trends June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4 G4

32. Microprocessor Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Sources: http://www.intel.com/pressroom/kits/quickreffam.htm, www.geek.com Alpha (R.I.P) P4N G4 P4

33. DRAM Memory Trends (Log Scale) June 9, 2009 204424 Digital Design Automation Source: Textbook, Industry Reports

34. Processor Performance Trends June 9, 2009 204424 Digital Design Automation Source: Hennesy & Patterson Computer Architecture: A Quantitative Approach, 3rd Ed. , Morgan-Kaufmann, 2002. Vax 11/780

37. Technology Directions: SIA Roadmap June 9, 2009 204424 Digital Design Automation

42. These trends have brought many changes and new challenges to circuit design. June 9, 2009 204424 Digital Design Automation

47. Interconnect Delay June 9, 2009 204424 Digital Design Automation 0.65 1989 0.5 1992 0.35 1995 0.25 1998 0.18 2001 0.13 2004 0.1 2007 0 5 10 15 20 25 30 35 40 Gate delay Interconnect delay Source: SIA Roadmap 1997

48. Gallery - Early Processors June 9, 2009 204424 Digital Design Automation Mos Technology 6502 Intel 4004 First µP - 2300 xtors L=10µm

50. Gallery - Current Processors June 9, 2009 204424 Digital Design Automation PowerPC 7400 (G4) 6.5M transistors / 450MHz / 8-10W L=0.15µm Pentium® III 28M transistors / 733MHz-1Gz / 13-26W L=0.25µm shrunk to L=0.18µm

51. Gallery - Current Processors June 9, 2009 204424 Digital Design Automation Pentium® 4 42M transistors / 1.3-1.8GHz / 49-55W L=0.18µm Pentium® 4 “Northwood” 55M transistors / 2-2.5GHz L=0.13µm

54. Gallery - Current FPGA June 9, 2009 204424 Digital Design Automation Xilinx Virtex FPGA

55. Gallery - Graphics Processor June 9, 2009 204424 Digital Design Automation nVidia GeForce4 57M transistors / 300MHz / ??W L=0.15µm

58. Die Photo - 2001 Design Project June 9, 2009 204424 Digital Design Automation Chip Design by Ed Thomas Photo courtesy Ron Feiller, Agere