This document discusses FET biasing circuits. It explains that FETs are voltage controlled devices and describes Shockley's equation and the relationships between input and output quantities for different FET types. It then discusses three biasing circuits - fixed bias, self bias, and voltage divider bias. For each circuit, it shows the calculations to determine the quiescent gate-source voltage VGSQ, drain current IDQ, and drain-source voltage VDSQ. It also includes an example problem demonstrating how to calculate these values for a given circuit and plot the load line.

1. R.M.K. COLLEGE OF ENGINEERING
AND TECHNOLOGY
FET BIASING
Dr.N.G.Praveena
Associate Professor/ECE

2. FET BIASING
 Voltage controlled device
 General relationships that can be applied to the dc
analysis of all FET amplifiers are
IG ≈ 0A and ID = IS
 For JFETs and depletion – type MOSFET and MESFET ,
Shockley’s equation is applied to relate the input and
output quantities
ID = IDSS ( 𝟏 −
𝑽𝑮𝑺
𝑽𝑷
)𝟐
 For enhancement-type MOSFETs and MOSFETs
ID = 𝒌𝒏 ( 𝑽𝑮𝑺 − 𝑽𝑷)𝟐
 Different biasing circuit of FET are
Fixed Bias
Self Bias
Voltage Divider Bias

3. FIXED BIAS
 For dc analysis
ac input signal = 0
C1 and C2 – open circuit (∵f = 0)
𝑰𝑮 ≈ 0A , 𝑽𝑹𝑮 = 𝑰𝑮 𝑹𝑮 = 0 V

4. TO FIND 𝐕𝐆𝐒
Apply KVL to the input circuit,
– 𝐕𝐆𝐆 − 𝐕𝐆𝐒 =0
𝐕𝐆𝐒 = – 𝐕𝐆𝐆 ------(1)
Since VGG is a fixed dc supply , the voltage VGS is fixed
in magnitude. So it is called fixed bias circuit
TO FIND 𝐈𝐃
The drain current 𝐈𝐃 is given
𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 −
𝐕𝐆𝐒
𝐕𝐏
)𝟐
Sub (1),
𝐈𝐃𝐐 = 𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 +
𝐕𝐆𝐆
𝐕𝐏
)𝟐

5.  To FIND VDS
Apply KVL to output loop between D-S,
VDD = IDRD + VDS
Rearrange the above equation to get VDS
VDSQ = VDS = VDD - IDRD -------(2)
 Main drawback of
fixed bias circuit is
that it requires
two power supplies.

6. DC LOAD LINE AND Q POINT
 Sub VDS = 0 in (2)
ID = VDD/ RD
 Sub ID = 0 in (2)
VDS = VDD
VDS = VDD - IDRD ---- (2)
VDD = - IDRD
(0, VDD/ RD)
(VDD ,0) VDS
ID

7. SELF BIAS
 Eliminates the need for two dc supplies.
 For dc analysis
ac input signal = 0
C1 and C2 – open circuit (∵f = 0)
𝑰𝑮 ≈ 0A , 𝑽𝑹𝑮 = 𝑰𝑮 𝑹𝑮 = 0 V

8. TO FIND VGS
Apply KVL to the input circuit,
0 = VGS + ISRS
VGS = - IDRS ---(1) (∴ID=IS )
TO FIND 𝐈𝐃
The drain current 𝐈𝐃 is given by
𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 −
𝐕𝐆𝐒
𝐕𝐏
)𝟐
Sub (1),
𝐈𝐃𝐐 = 𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 +
IDRS
𝐕𝐏
)𝟐

9.  To FIND VDS
Apply KVL to output loop between D-S,
VDD = IDRD + VDS + IDRS
Rearrange the above equation to get VDS
VDS = VDD - IDRD – IDRS
VDSQ = VDS = VDD – ID (RD + RS)

10. VOLTAGE DIVIDER BIAS
 For dc analysis
ac input signal = 0
C1 and C2 – open circuit (∵f = 0)
𝑰𝑮 ≈ 0A , 𝑽𝑹𝑮 = 𝑰𝑮 𝑹𝑮 = 0 V
VG= VDD

11. TO FIND VGS
Apply KVL to the input circuit,
VG = VGS + ISRS
VGS = VG – IDRS ---(1) (∴ID=IS )
TO FIND 𝐈𝐃
The drain current 𝐈𝐃 is given by
𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 −
𝐕𝐆𝐒
𝐕𝐏
)𝟐
Sub (1),
𝐈𝐃𝐐 = 𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 −
VG−IDRS
𝐕𝐏
)𝟐

12.  To FIND VDS
Apply KVL to output loop between D-S,
VDD = IDRD + VDS + IDRS
Rearrange the above equation to get VDS
VDS = VDD - IDRD – IDRS
VDSQ = VDS = VDD – ID (RD + RS)

13. Problems
For the circuit shown in the figure calculate VGSQ ,
IDQ and VDSQ and draw dc load line.
Given data:
VDD = 8V
RD = 1kΩ
VGG = 2V
RG = 1MΩ
IDSS = 10mA
VP = - 4V

14. TO FIND 𝐕𝐆𝐒
Apply KVL to the input circuit,
– 𝐕𝐆𝐆 − 𝐕𝐆𝐒 =0
𝐕𝐆𝐒 = – 𝐕𝐆𝐆 = -2V
TO FIND 𝐈𝐃
The drain current ID is given by
𝐈𝐃 = 𝐈𝐃𝐒𝐒(𝟏 −
𝐕𝐆𝐒
𝐕𝐏
)𝟐
𝐈𝐃𝑸 = 𝐈𝐃 = 2.5mA
To FIND VDS
Apply KVL to output loop between D-S,
VDD = IDRD + VDS -------(1)
VDSQ = VDD – IDQRD
= 5.5V

15. Apply KVL to output loop between D-S,
VDD = IDRD + VDS
When ID = 0 then
VDSQ = VDD – (0A) RD
= 8V
WhenVDS = 0 then
ID =
VDD
RD
= 8mA
(0, VDD/ RD)
(VDD ,0) VDS
ID