The document discusses place, route and back annotation in FPGA design. It explains that place and route involves placing logic elements and interconnecting them on the FPGA grid. Back annotation translates the physical design information after place and route back to the logical design, allowing timing simulation. Manual placement and routing as well as directed routing are also covered.

1. MISRIMAL NAVAJEE MUNOTH JAIN
ENGINEERING COLLEGE
VLSI LAB MANUAL
ECE: VII SEMESTER (2006-2010)
By
V.Thilakrathi(Lect/ECE)

2.  STUDY OF XC3S400 – XILINX SPARTAN 3 FPGA
 FPGA DESIGN FLOW
 STUDY OF SIMULATION USING XILINX ISE-9.1.i
 STUDY OF SYNTHESIS USING XILINX ISE 9.1i
 STUDY OF SCHEMATIC ENTRY USING XILINX ISE 9.1i
 PLACE, ROUTE AND BACK ANNOTATION IN FIELD PROGRAMMABLE GATE
ARRAY (FPGA)
 SIMULATION AND IMPLEMENTATION OF LOGIC GATES
 SIMULATION AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER
 SIMULATION AND IMPLEMENTATION OF HALF SUBTRACTOR AND FULL
SUBTRACTOR
 SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER
 SIMULATION AND IMPLEMENTATION OF PARALLEL SUBTRACTOR
 SIMULATION AND IMPLEMENTATION OF CARRY LOOK-AHEAD ADDER
 SIMULATION AND IMPLEMENTATION OF CMOS GATES
 SIMULATION AND IMPLEMENTATION OF PARALLEL ADDER AND
SUBTRACTOR
 SIMULATION AND IMPLEMENTATION OF 8:3 ENCODER AND 3:8 DECODER
 SIMULATION AND IMPLEMENTATION OF 1:8 DEMULTIPLEXER AND 4:1
MULTIPLEXER
 SIMULATION AND IMPLEMENTATION OF 8 BIT MULTIPLEXER
 SIMULATION AND IMPLEMENTATION OF FLIP FLOPS

3.  SIMULATION AND IMPLEMENTATION OF SYNCHRONOUS UP DOWN
COUNTER
 SIMULATION AND IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER
 SIMULATION AND IMPLEMENTATION OF SERIAL ADDER
 SIMULATION AND IMPLEMENTATION OF TRAFFIC LIGHT CONTROLLER

4. STUDY OF XC3S400 – XILINX SPARTAN 3 FPGA
AIM:
To study XC3S400 – XILINX Spartan 3 Field Programmable Gate Array (FPGA)
INTRODUCTION:
A field programmable gate array (FPGA) is a semiconductor device containing
programmable logic components called “configurable logic blocks” and programmable
interconnects. Logic blocks can be programmed to perform the logic functioning ranging from
basic gates to more complex logic function. In most FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops or more complete blocks of memory.
A hierarchy of programmable interconnects allows logic blocks to be interconnected as
needed by the system engineer (designer). These can be programmed by the designer, after
FPGA is manufactured, to implement any logical function – hence the name “FIELD
PROGRAMMABLE”.
FPGA DESIGN AND PROGRAMMING
To define the behavior of the FPGA the user provides a hardware description language
(HDL) or a schematic design. Common HDLs are VHDL and Verilog. Then, using an electronic
design automation tool, a technology netlist is generated. This can be then fitted to the actual
FPGA architecture using a process called place-and-route. The user will validate the map, place
and route results via timing analysis, simulation and other verification methodologies. Once the
design and validation process is complete, the bit file is generated is used to configure the
FPGA.

5. XILINX XC3S400 – SPARTAN 3 FPGA
It is specifically designed as very low cost, high performance logic solution for high
volume, consumer-oriented applications.
ARCHITECTURE OF XC3S400
This consists of 5 fundamental programmable functionable elements
1. Configurable logic blocks (CLB) contain RAM based look-up-tables (LUTs) to implement
logic and storage elements that can be used as flip flops or latches. CLBs can be
programmed to perform a wide variety of logical functions as well as to store data.
2. I/O Blocks (IOBs) control the flow of data between the I/O pin and the internal logic of
the device. Each IOB supports bidirectional data flow plus 2-state operations. Double
Data rate (DDR) registers are included. The digitally controlled impedance (DCI) feature
provides automatic on-chip terminations, simplifying board designs.
3. Block RAM provides data storage in the form of 18-10 bit dual port blocks
4. Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the products
5. Digital clock manager (DCM) blocks provide self calibrating, fully digital solution for
distributing, delaying, multiplying, dividing and phase shifting clock signals.
These elements are organized as shown in the diagram. A ring of IOBs surrounds
a regular array of CLBs. It has 4 RAM columns. Each column is made up of several 18kbit
RAM blocks; each block is associated with a delicate multiplier. The DCMs are positioned
at the ends of the outer block RAM columns.
XC3S400 consists of rich network of traces and switches that interconnect all
functional elements, transmitting signals among them. Each functional element has an
associated switch matrix that permits multiple connections as routing.
RESULT:
Thus XC3S400 – XILINX SPARTAN 3 field programmable gate array (FPGA) was studied.

6. FPGA DESIGN FLOW
AIM:
To study FPGA design flow using XILINX ISE – 9.1 i
INTRODUCTION:
The integrated software environment (ISE) is the Xilinx design software that allows to
take the design from design entry through Xilinx device programming. The ISE design flow
comprises the following steps, design entry, design synthesis, design implementation, and Xilinx
device programming. Design verification which includes both function verification and timing
verification, takes place at different points during the design flow.
DESIGN ENTRY:
Design entry is the first step in the ISE design flow. During design entry, sources files are
created based on the design objectives. The top-level design file can be created using a
Hardware Description Language (HDL), such as VHDL, Verilog or using a schematic.
SYNTHESIS:
After design entry and optional simulation, the synthesis step is run. During this step,
VHDL, verilog, or mixed language designs become netlist files that are accepted as input to the
implementation step.
IMPLEMENTATION:
After synthesis, the design implementation is executed, which converts the logical
design into a physical file format that can be downloaded to the selected target device. From
project Navigator, the implementation process can be run in one step, or each of the
implementation processes can be run separately.
BACK ANNOTATION:
Back annotation is the translation of a routed or fitted design to a timing simulation
netlist.
VERIFICATION:

7. The functionality of the design can be verified at several points is the design flow. The
simulator software can be used to verify the functionality and timing of the design or a portion
of the design. The simulator interprets VHDL or verilog code into circuit functionality and
displays logical results of the described HDL to determine correct circuit operation. Simulation
allows to create and verify complex functions in a relatively small amount of time. The in-circuit
verification can also be run after programming the device.
DEVICE CONFIGURATION:
After generating a programming file, the target device is configured. During
configuration files are generated and the programming files are downloaded from a host
computer to a Xilinx device.
RESULT
Thus the FPGA design flow was studied using Xilinx ISE – 9.1i.
STUDY OF SIMULATION USING XILINX ISE-9.1.i

8. AIM:
To study the simulation of a digital circuit using Xilinx ISE 9.1.i
INTRODUCTION:
During HDL simulation, the simulator software verified the functionality, the timing of
the design or portion of the design. The simulator interprets VHDL or Verilog code into circuit
functionality and displays the logical result of the desired HDL to determine correct circuit
operation. Simulation allows to create and verify complex functions in a relatively small amount
of time.
Simulation takes place at several points in the design flow. It is one of the first steps
after design entry and one of the last steps after implementation. As part of verifying the end
functionality and performance of the design.
Simulation is an iterative process, which may require repeating until both design
functionality and performance timing is met. For a typical design, simulation libraries
1. Compilation of the simulation libraries
2. Creation of the designs test bench
3. Functional simulation
4. Implementation of the design and creation of the timing simulation netlist
5. Timing simulation
SIMULATION LIBRARIES
Most designs are built with gentle code, so device specific components are not
necessary. However in certain cases if may be required or beneficial to use device specification
components in the code to achieve the desired circuit implementation and results when the
component is instantiated in the design, the simulator must reference a library that describes
the functionality of the component to ensure proper simulation, XILINX provides simulation
libraries for simulation primitives.
UNISIM library for functional simulation of XILINX primitives
XILINX core library for functional simulation of linx primitives
SIMPRIM lib for timing simulation of XILINX primitives
TEST BENCH

9. To simulate your design you need both the design under test (DUT) or unit under test
(UUT) and the stimulus provided by the test bench. A test bench is HDL code that allows to
provide a documental, repeatable set of stimuli that is portable across different simulator. A
test bench can be as simple as a file with clock and input data or a more complicated file that
includes error checking, file input and output and conditional testing. The test bench can be
created using either of the following methods.
(i) TEXT EDITOR
This is the recommended method for verifying complex designs. It allows to use all
the features available in the HDL language and gives you flexibility in verifying
design. Although this method may be more challenging in that one must create this
code, the advantage is that it may produce more precise & accurate results than
using the bench waveform editor.
(ii) XILINX TEST BENCH WAVEFORM EDITOR
This is the recommended method for verifying less complicated simulation tasks,
and is recommended if the designer is new to HDL simulation. It allows to graphically
enter the test bench to drive the stimulus to the design. The same test bench can be
used for both functions and timing simulation
FUNCTIONAL SIMULATION
After the simulation libraries & create the test bench & design code are compiled, one
can perform functional simulation on the design. Functional simulation is an iterative process,
which may require multiple simulations to achieve the desired end functionality of the design.
Result :
Thus the Simulation using XILINX ISE-9.1.i was studied.
STUDY OF SYNTHESIS USING XILINX ISE 9.1i
AIM:
To study the synthesis of a digital circuit using XILINX ISE 9.1i.

10. INTRODUCTION:
After design entry and optional simulation is done, the synthesis of the design is run.
The ISE software include XILINX synthesis technology (XST), which synthesis VHDL or verilog or
mixed language designs to create X-link specific netlist files known as NGC files. XST places the
NGC files in the projector and file is accepted as input to translate step of the implement design
process.
XST INPUT AND OUTPUT FILES:
XST supports extensive VHDL and verilog subsets from the following standards VHDL:
IEEE 1076-1987, IEEE 1076-1993, including IEEE standards and synopsis. Verilog: IEEE
1364-1995, IEEE 1364-2001.
A) XILINX CONSTRAINT FILE (XCF):
XCF in which you can specify synthesis, timing and specific implementation constraints
that can be propagated to the NGC.
B) CORE FILES:
These files can be in either NGC or EDIF format. XST does not modify coves. It uses them
to inform area and timing optimization.
In addition to NGC files, XST also generates the following files or outputs.
SYNTHESIS REPORT:
This report contains the result from the synthesis run, including area and timing
estimation.
1) RTC SCHEMATIC:
This is the schematic representation of the pre-optimized design shown at the
RTL. This representation is in terms of generic symbols such as address, multiples, counters,
AND and OR gates.
2) TECHNOLOGY SCHEMATIC:
This is a schematic representation of an NGC file shown in terms of logic
elements. Optimized to the target architecture or technology. It is generated after the
optimization and technology.
3) HDL PASSING:

11. During HDL passing, XST checks whether the HDL code is corrected and reports
any syntax errors.
4) HDL SYNTHESIS:
During HDL synthesis, XST analysis the HDL code and attempts to infer specific
design building blocks or macros for which it can create efficient technology implementations.
To reduce the amount of inferred macros XST performs a resource showing check. This actually
leads to a reduction of the area as well as an increase in the clock frequency.
5) LOW LEVEL OPTIMIZATION:
During low level optimization XST transforms inferred macros and general glue
logic into a technology specific implementation.
RESULT:
Thus the synthesis of digital circuit was studied using XILINX ISE 9.1i.
STUDY OF SCHEMATIC ENTRY USING XILINX ISE 9.1i
AIM:
To study the schematic entry of a digital circuit using XILINX ISE9.1i.
INTRODUCTION:

12. Schematics are used for top level or lower level design files. It allows to have a visual
representation of the design.
TOP LEVEL SCHEMATIC:
Schematics are used in the top level and low level modules are created using any of the
following source types. To instantiate a lower level module in the top level design and the
schematic symbol is instantiated.
LOWER LEVEL SCHEMATIC:
Schematics can be used to define the lower level modules of the design. If the top level
design is schematic symbol is created and it is instantiated in the top level. If the top level
design file is an HDL file a template is created.
All schematics are ultimately converted either VHDL or verilog structural netlist before
being passed.
SCHEMATIC DESIGN METHODS:
When using a schematic the top level design either of the following method is used to
describe the lower level modules.
i) TOP-DOWN SCHEMATIC DESIGN METHOD:
Using this method a top level block diagram description of the design is created using a
schematic. Then each symbol pushed down and its behavior is defined using HDL or schematic
file.
1) SCHEMATIC:
The schematic contains input markers that correspond to the pins in the block symbol
created. The schematic is built by adding symbols ad described in adding a symbol.
2) VHDL (OR) VERILOG:
The template contains HDC port descriptions that correspond to the pins in the block
symbol created. The behavior of the module can be then added. The ISE language template
provides a convenient method to insert.
ii) BOTTON-UP SCHEMATIC DESIGN METHOD:

13. Using this method a top level schematic design is created and lower level functional
blocks is then created to instantiate.
RESULT:
Thus the schematic entry of a digital circuit was studied using XILINX ISE 9.1i.
PLACE, ROUTE AND BACK ANNOTATION IN FIELD PROGRAMMABLE GATE ARRAY
(FPGA)
AIM:
To study the place, route and back annotation in FPGA.
PLACE AND ROUTE:

14. Place and route is a stage in the design of FPGA during which logic elements are placed
and interconnected on the grid of the FPGA. As implied by the name, it is composed of two
steps, placement and routing. The first step, placement involves deciding where to place all
electronic component circuitry and logic element in a generally limited amount of space. This is
followed by routing, which decides the exact design of all the wires needed to connect the
placed components.
These processes are similar at a high level but the actual details are very different. With
large sizes of the modern designs, this operation is usually proportional by EDA tools.
MANUAL PLACING AND ROUTING:
The FPGA editor can be used to fine tune the design and impure the performance of the
place and route process, once can be manually swapped components and pins as well as route
and in route nets. When the design is manually changed in FPGA editor.
When a group of components requires specific placements, relationally placed macros
are used to define the relative placements.
DIRECTED ROUTING:
Directed routing allows the design to retain and timing for a small number of loads
intended sources. Although it is necessary to lock placement so that the appropriate routing
can be reproduced. The directed routing cannot be used as placement tool.
BACK ANNOTATION:
It is the translation of a router on fitted design to a timing simulation netlist.
Before timing simulation can occur the physical design information must be translated
and distributed back to the logical design.
NETGEN:
It is a command line program that distributes information about delays, set up and hold
timer, clock to out and pulse widths found in the physical NCD design file back to the logical
NGD file.

15. Netgen reads an NCD as input. The NCD file can have only design as a partially or fully
placed and normal routed design. An NGM file created MAD is optional source is input. Netgen
merges mapping information from the optional file with placement routing and timing
information from NCD file.
RESULT:
Thus the place, route and back annotation in Field Programmable Gate Array (FPGA) is
studied.