This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This lesson on System-on-Chip was given for the course "Advanced Platform Architectures and Mapping Methods for Embedded Applications" at the KU Leuven and is based on chapter 8 of 'A Practical Introduction to Hardware Software Codesign (Schaumont P.)'
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, First is Functional Testing, which undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response. It does not consider how the circuit is designed, but only that it gives the correct output during test and second one is Fault Modelling in whichto consider the possible Faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.The faults which are likely to occur on the wafer during the manufacture of the ICs, and compute the result on the circuit output(s) with or without each fault present. Each of the final series of tests is then designed to show that a particular fault is present or not.
FPGA are a special form of Programmable logic devices(PLDs) with higher densities as compared to custom ICs and capable of implementing functionality in a short period of time using computer aided design (CAD) software....by mathewsubin3388@gmail.com
This lesson on System-on-Chip was given for the course "Advanced Platform Architectures and Mapping Methods for Embedded Applications" at the KU Leuven and is based on chapter 8 of 'A Practical Introduction to Hardware Software Codesign (Schaumont P.)'
Low Power VLSI design architecture for EDA (Electronic Design Automation) and Modern Power Estimation, Reduction and Fixing technologies including clock gating and power gating
Routing in Integrated circuits is an important task which requires extreme care while placing the modules and circuits and connecting them with each other.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
In considering the techniques that may be used for digital circuit testing, two distinct philosophies may be found, First is Functional Testing, which undertake a series of functional tests and check for the correct (fault free) 0 or 1 output response. It does not consider how the circuit is designed, but only that it gives the correct output during test and second one is Fault Modelling in whichto consider the possible Faults that may occur within the circuit, and then to apply a series of tests which are specifically formulated to check whether each of these faults is present or not.The faults which are likely to occur on the wafer during the manufacture of the ICs, and compute the result on the circuit output(s) with or without each fault present. Each of the final series of tests is then designed to show that a particular fault is present or not.
Learn about the new 28-nm Stratix V FPGA family from Altera. Built for bandwidth, this family includes 28-Gbps transceivers, embedded HardCopy blocks, and variable-precision DSP blocks.
Semiconductor Hubs for Research & InnovationZinnov
The semiconductor industry has evolved significantly in the last 50 years. While in early 60s, US was the clear market leader, by the 90s the semiconductor industry in Taiwan, Singapore and Korea posed a competitive threat to that in the US. Recent times have witnessed other locations in China and India establish themselves firmly on the global semiconductor landscape.
For any innovation hub, the entire ecosystem has to be favorable for growth. This includes access to large skilled talent pool, strong university ecosystem, favorable government policies etc.
Various processor architectures are described in this presentation. It could be useful for people working for h/w selection and processor identification.
This is a presentation on FPGA from my 3rd year academics which was the field of my mini project/seminar in the same. Main emphasis is laid on the application of FPGA in DSP domain
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
ASIC Implementation of I2C Master bus controller with design of Firm IP core has been proposed in this paper. I2C is one the most prominent protocol used in on chip communication among sub-systems. The generic design of I2C master controller has ample of features to incorporate vast varieties of application and I2C standards. The generic design is slow, congested and require high power. It’s rare to utilize all the
features of generic design fully in a single particular application or system. Hence, a modified ASIC design
with specific less features but with better timing, low power requirement and less area overhead, has been
proposed in this paper. This design is specifically apt for digital systems which have serial bus interface
requirement for on board communication. Moreover, the Firm IP core of I2C Master Controller has been designed for ASIC, which makes the design highly portable on any ASIC chips or SOC designs. The firm IPs is best in terms of flexibility and more predictable than commonly found soft IPs. The entire custom ASIC implementation of proposed design has been done in Cadence Tool chain with 45nm technology using
standard cell library. A thorough comparison has been done between generic open sourced RTL design of I2C Controller obtained from Opencores.org and our proposed design.
Design and Development of Artix-7 FPGAbased Educational BoardIJERA Editor
This paper proposes a new approach that makes it possible for every student to perform experiments of developing and designing a board within limited time available for the course. An educational FPGA board and respective interface are also discussed. The board is a low-cost and high-performance Single Board Computer built around the Xilinx Artix-7 FPGA family XC7Z010 chip. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.
Blooms Taxonomy in Engineering EducationA B Shinde
The objective of this presentation is to create awareness among the aspirants regarding the Blooms Taxonomy, how it can be related to define Course objectives and outcomes as well as to assess the students level
This presentation covers the basic guidelines regarding how to face the interview including resume writing, aptitude test, group discussion and facing interview confidently...
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
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Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Water scarcity is the lack of fresh water resources to meet the standard water demand. There are two type of water scarcity. One is physical. The other is economic water scarcity.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
Cosmetic shop management system project report.pdf
Spartan-II FPGA (xc2s30)
1. SPARTAN-II FPGA
Mr. A. B. Shinde
Assistant Professor,
Department of Electronics Engg.
P.V.P.I.T., Budhgaon
2. INTRODUCTION
The Spartan®-II Field-Programmable Gate Array family gives users high
performance, abundant logic resources, and a rich feature set, all at an
exceptionally low price.
The six-member family offers densities ranging from 15,000 to 200,000
system gates, as shown in Table 1. System performance is supported up
to 200 MHz.
Features include block RAM (to 56K bits), distributed RAM (to 75,264
bits), 16 selectable I/O standards, and four DLLs. Fast, predictable
interconnect means that successive design iterations continue to meet
timing requirements.
The Spartan-II family is a superior alternative to mask-programmed
ASICs. The FPGA avoids the initial cost, lengthy development cycles,
and inherent risk of conventional ASICs.
Also, FPGA programmability permits design upgrades in the field with no
hardware replacement necessary (impossible with ASICs).
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
3. FEATURES
Second generation ASIC replacement technology
- Densities as high as 5,292 logic cells with up to 200,000 system
gates
- Streamlined features based on Virtex® FPGA architecture
- Unlimited reprogrammability
- Very low cost
- Cost-effective 0.18 micron process
System level features
- SelectRAM™ hierarchical memory:
· 16 bits/LUT distributed RAM
· Configurable 4K bit block RAM
· Fast interfaces to external RAM
- Fully PCI compliant
- Low-power segmented routing architecture
- Full readback ability for verification/observability
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
4. FEATURES
System level features
- Dedicated carry logic for high-speed arithmetic
- Efficient multiplier support
- Cascade chain for wide-input functions
- Abundant registers/latches with enable, set, reset
- Four dedicated DLLs for advanced clock control
- Four primary low-skew global clock distribution nets
- IEEE 1149.1 compatible boundary scan logic
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
5. FEATURES
Versatile I/O and packaging
- Pb-free package options
- Low-cost packages available in all densities
- Family footprint compatibility in common packages
- 16 high-performance interface standards
- Hot swap Compact PCI friendly
- Zero hold time simplifies system timing
• Core logic powered at 2.5V and I/Os powered at 1.5V,
2.5V, or 3.3V
• Fully supported by powerful Xilinx® ISE®
development system
- Fully automatic mapping, placement, and routing
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
6. SPARTAN-II FPGA FAMILY MEMBERS
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
7. GENERAL OVERVIEW OF PACKAGE
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
8. GENERAL OVERVIEW
The Spartan-II family of FPGAs
have a regular, flexible,
programmable architecture of
Configurable Logic Blocks (CLBs),
surrounded by a perimeter of
programmable Input/Output Blocks
(IOBs).
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
There are four Delay-Locked Loops
(DLLs), one at each corner of the
die.
Two columns of block RAM lie on
opposite sides of the die, between
the CLBs and the IOB columns.
These functional elements are
interconnected by a powerful
hierarchy of versatile routing
channels
10. INPUT/OUTPUT BLOCK
The Spartan-II FPGA IOB, as seen in Figure, features inputs and
outputs that support a wide variety of I/O signaling standards.
These high-speed inputs and outputs are capable of supporting various
state of the art memory and bus interfaces.
The three IOB registers function either as edge-triggered D-type flip-flops
or as level-sensitive latches.
Each IOB has a clock signal (CLK) shared by the three registers and
independent Clock Enable (CE) signals for each register.
In addition to the CLK and CE control signals, the three registers share
a Set/Reset (SR). For each register, this signal can be independently
configured as a synchronous Set, a synchronous Reset, an
asynchronous Preset, or an asynchronous Clear.
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
11. I/O BANKING
Some of the I/O standards described above
require VCCO and/or VREF voltages. These
voltages are externally connected to device pins
that serve groups of IOBs, called banks.
Consequently, restrictions exist about which I/O
standards can be combined within a given bank.
Eight I/O banks result from separating each edge
of the FPGA into two banks.
Each bank has multiple VCCO pins which must
be connected to the same voltage.
Voltage is determined by the output standards in
use.
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
12. CONFIGURABLE LOGIC BLOCK
The basic building block of the
Spartan-II FPGA CLB is the logic cell
(LC).
An LC includes a 4-input function
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
generator, carry logic, and storage
element.
Output from the function generator in
each LC drives the CLB output and the
D input of the flip-flop.
Each Spartan-II FPGA CLB contains
four LCs, organized in two similar
slices; a single slice is shown in
Figure.
In addition to the four basic LCs, the
Spartan-II FPGA CLB contains logic
that combines function generators to
provide functions of five or six inputs.
13. CONFIGURABLE LOGIC BLOCK
Look-Up Tables
Spartan-II FPGA function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function generator,
each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the
two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-
bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The
Spartan-II FPGA LUT can also provide a 16-bit shift register that is ideal
for capturing high-speed or burst-mode data. This mode can also be
used to store data in applications such as Digital Signal Processing.
Storage Elements
Storage elements in the Spartan-II FPGA slice can be configured
either as edge-triggered D-type flip-flops or as level-sensitive latches.
The D inputs can be driven either by function generators within the slice
or directly from slice inputs, bypassing the function generators. In
addition to Clock and Clock Enable signals, each slice has synchronous
set and reset signals (SR and BY). SR forces a storage element into the
initialization state specified for it in the configuration.
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
14. CONFIGURABLE LOGIC BLOCK
Additional Logic
The F5 multiplexer in each slice combines the function generator
outputs. This combination provides either a function generator that can
implement any 5-input function, a 4:1 multiplexer, or selected functions
of up to nine inputs.
Arithmetic Logic
Dedicated carry logic provides capability for high-speed
arithmetic functions. The Spartan-II FPGA CLB supports two separate
carry chains, one per slice. The height of the carry chains is two bits
per CLB. The arithmetic logic includes an XOR gate that allows a 1-bit
full adder to be implemented within an LC. In addition, a dedicated AND
gate improves the efficiency of multiplier implementation.
BUFTs
Each Spartan-II FPGA CLB contains two 3-state drivers (BUFTs)
that can drive on-chip busses. See "Dedicated Routing," page 12. Each
Spartan-II FPGA BUFT has an independent 3-state control pin and an
independent input pin.
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
15. BLOCK RAM
Spartan-II FPGAs incorporate
several large block RAM memories.
These complement the distributed
RAM Look-Up Tables (LUTs) that
provide shallow memory structures
implemented in CLBs.
Block RAM memory blocks are
organized in columns. All Spartan-II
devices contain two such columns,
one along each vertical edge. These
columns extend the full height of the
chip.
Each memory block is four CLBs
high, and consequently, a Spartan-II
device eight CLBs high will contain
two memory blocks per column, and
a total of four blocks.
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
16. PROGRAMMABLE ROUTING MATRIX
It is the longest delay path that limits the
speed of any worst-case design.
Consequently, the Spartan-II routing
architecture and its place-and-route software
were defined in a single optimization
process. This joint optimization minimizes
long-path delays, and consequently, yields
the best system performance.
The joint optimization also reduces design
compilation times because the architecture
is software-friendly. Design cycles are
correspondingly reduced due to shorter
design iteration times.
Local Routing
The local routing resources, as shown in Figure 6, provide the following
three types of connections: • Interconnections among the LUTs, flip-flops, and
General Routing Matrix (GRM)
• Internal CLB feedback paths that provide high-speed connections to LUTs within
the same CLB, chaining them together with minimal routing delay
• Direct paths that provide high-speed connections between horizontally adjacent
CLBs, eliminating the delay of the GRM
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
17. DELAY-LOCKED LOOP (DLL)
Associated with each global clock input buffer is a fully digital Delay-
Locked Loop (DLL) that can eliminate skew between the clock input
pad and internal clock-input pins throughout the device.
Each DLL can drive two global clock networks. The DLL monitors the
input clock and the distributed clock, and automatically adjusts a clock
delay element. Additional delay is introduced such that clock edges
reach internal flip-flops exactly one clock period after they arrive at the
input.
The DLL also provides advanced control of multiple clock domains. The
DLL provides four quadrature phases of the source clock, can double
the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. It has six
outputs.
The DLL also operates as a clock mirror. By driving the output from a
DLL off-chip and then back on again, the DLL can be used to deskew a
board level clock among multiple Spartan-II devices. I
Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
18. Mr. A. B. Shinde, Electronics Engineering,
P.V.P.I.T. Budhgaon
THANK YOU
shindesir.pvp@gmail.com