Anu Mehra Maam PPT - 1

1. POWER Introduction to Low Power VLSI Design Dr Anu Mehra

2. Where Does Power Go in CMOS?

4. Dynamic Power Charging and discharging of capacitors due to logic switching event

6. Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f 0 to1 or 1 to 0 Need to reduce C L , V dd , and f to reduce power. Not a function of transistor sizes! i VDD f 0 to1 or 1 to 0 is the frequency of transition Vin Vout C L Vdd

7. Half the energy stored in the Capacitor, the other half is lost !

8. Node Transition Activity and Power

10. Delay Formula C int =  C gin with   1 f = C ext /C gin - effective fanout C ext =fC gin R = R unit /W ; C int =WC unit t p 0 = 0.69 R unit C unit Let tp=0.69 Req(Cint+Cext) =0.69 ReqCint(1+Cext/Cint) =tp0(1+Cext/Cint) =tp0(1+f/  )

12. Delay as a function of V DD

15. Let for a reference device f=1

17. Transistor Sizing (3) F =1 2 5 10 20 V DD = f (f) E/E ref = f (f)

19. C sc is short circuit capacitance

21. Direct Path currents contd. Area of an equilateral triangle is 1/2base. perpendicular P=VI, E=Pt

22. f 0 to1 or 1 to 0 is switching frequency ts is 0 to 100% transition time tr(f) is 10 to 90% transition time

25. Short Circuit Currents

26. How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise , but can’t do this for cascade logic, so ... Input slope is fixed

28. Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

30. Dynamic Power -Glitches Glitches are caused by arrival time of two separate input signals. If a given input signal arrives first and causes the output to switch, later another input signal arrives and causes the output to switch back to original value. Undesired Power dissipation ! Glitches propagate thought the fanout gate and cause further unintended transitions

33. Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

34. Reverse-Biased Diode Leakage JS = 10-100 pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

35. Junction Leakage currents are caused by thermally generated carriers. Their value increases with increasing temperature. At 85 degrees Celsius, (upper bound for junction temperature) their value increases by 60 times over room temperature value.

36. Subthreshold Leakage Component

37. Sub threshold Leakage issues Closer V T is to 0 V, larger is the static power dissipation as I D becomes larger L is getting smaller as source and drain are getting closer Supply voltages are being scaled while keeping V T constant. This leads to increase in delay –see next slide. As Supply voltage goes down to 2V T,, performance goes down substantially. If V T is lowered, performance improves, sub threshold leakage becomes an issue i.e. Trade off between power and delay!

38. Delay as a function of V DD V T =0.5V

39. Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

41. Modification for Circuits with Reduced Swing

42. Power Equation Static power loss in pseudo nmos only half the time!

43. POWER DELAY TRADE OFF We want low power and small delay. Why not minimize the product? P avg is average Power consumed t p is average delay Only dominant term in Power Equation Assume Gate switches at maximum possible rate so rise and fall

45. Differentiating EDp w.r.t. V DD and putting the result equal to 0

46. V DD (V) V T =0.5V

51. Thank you ………….