This document contains VHDL code examples for common digital logic components such as adders, comparators, counters, decoders, and linear feedback shift registers (LFSRs). It provides the VHDL syntax for implementing these components using processes, if/else statements, and case statements. The document is intended as a reference for a digital systems design lab manual. It was prepared by an instructor at Padmabhooshan Vasantraodada Patil Institute of Technology.
This document discusses behavioral modeling in VHDL. It covers different VHDL design styles including behavioral, dataflow, and structural. Behavioral modeling uses sequential statements inside processes to model functionality. Key concepts covered include processes with and without sensitivity lists, concurrent vs sequential execution, if/case statements, loops, and wait statements. An example of a behavioral model for a full adder is presented using two processes.
The document is a lab file submitted by Sachin Singh that describes 13 programs implemented for an Introduction to Artificial Intelligence lab course. It includes the code and output for programs that perform tasks like finding consecutive prime numbers, solving the water jug problem, implementing tic-tac-toe, various graph search algorithms like BFS, DFS, A*, and solving problems like the 4 queens and hangman.
1. The agenda covers warm up activities, presentations on loops in C programming, videos on real-world applications, a game to simulate loops, practical work creating a small program in pairs using CodeBlocks, online self-learning on C programming, and a question and answer session.
2. Students will break into small groups to create a C program related to their capstone project, then discuss using loops in different programs for homework by creating an Office Mix video.
3. Resources include a video explaining for, while, and do-while loops and related reading materials.
1. The agenda covers warm up activities, presentations on loops in C programming, videos on real-world applications, a game to simulate loops, practical work creating a small program in pairs using CodeBlocks, online self-learning on C programming, and a question and answer session.
2. Students will break into small groups to create a C program related to their capstone project, then discuss using loops in different programs for homework by creating an Office Mix video.
3. Resources include a video explaining for, while, and do-while loops and related links for further reading.
32 bit ALU Chip Design using IBM 130nm process technologyBharat Biyani
- Implemented a 32 bit Arithmetic/Logic unit in VHDL using behavioral Modeling which involves all basic ALU operations including special functionality like binary-to-grey code conversion, parity check, sum of first N numbers. Simulation is performed in ModelSim IDE.
- Involved design using Cadence (Virtuoso Layout/Schematic) and Hspice simulation of standard library cell.
- Involved library characterization using NCX, RTL synthesis of VHDL code using Synopsys Design Vision, auto placement & routing using Encounter, static timing analysis using Synopsys Primetime.
The document discusses various techniques for process synchronization and solving the critical section problem in concurrent systems. It describes producer-consumer problems and solutions using shared memory. It covers issues like race conditions that can occur. Different algorithms for solving the critical section problem are presented, including Peterson's algorithm and the Bakery algorithm. The document also discusses synchronization hardware support and low-level synchronization tools like locks, test-and-set instructions, and semaphores.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) and RS-232 communication standards. It describes the voltage levels used, the need for a converter chip between UART and RS-232, synchronous vs asynchronous transmission, baud rates, frame formats, and provides VHDL code for a UART transmitter and receiver implementation including state machines and registers.
This document discusses behavioral modeling in VHDL. It covers different VHDL design styles including behavioral, dataflow, and structural. Behavioral modeling uses sequential statements inside processes to model functionality. Key concepts covered include processes with and without sensitivity lists, concurrent vs sequential execution, if/case statements, loops, and wait statements. An example of a behavioral model for a full adder is presented using two processes.
The document is a lab file submitted by Sachin Singh that describes 13 programs implemented for an Introduction to Artificial Intelligence lab course. It includes the code and output for programs that perform tasks like finding consecutive prime numbers, solving the water jug problem, implementing tic-tac-toe, various graph search algorithms like BFS, DFS, A*, and solving problems like the 4 queens and hangman.
1. The agenda covers warm up activities, presentations on loops in C programming, videos on real-world applications, a game to simulate loops, practical work creating a small program in pairs using CodeBlocks, online self-learning on C programming, and a question and answer session.
2. Students will break into small groups to create a C program related to their capstone project, then discuss using loops in different programs for homework by creating an Office Mix video.
3. Resources include a video explaining for, while, and do-while loops and related reading materials.
1. The agenda covers warm up activities, presentations on loops in C programming, videos on real-world applications, a game to simulate loops, practical work creating a small program in pairs using CodeBlocks, online self-learning on C programming, and a question and answer session.
2. Students will break into small groups to create a C program related to their capstone project, then discuss using loops in different programs for homework by creating an Office Mix video.
3. Resources include a video explaining for, while, and do-while loops and related links for further reading.
32 bit ALU Chip Design using IBM 130nm process technologyBharat Biyani
- Implemented a 32 bit Arithmetic/Logic unit in VHDL using behavioral Modeling which involves all basic ALU operations including special functionality like binary-to-grey code conversion, parity check, sum of first N numbers. Simulation is performed in ModelSim IDE.
- Involved design using Cadence (Virtuoso Layout/Schematic) and Hspice simulation of standard library cell.
- Involved library characterization using NCX, RTL synthesis of VHDL code using Synopsys Design Vision, auto placement & routing using Encounter, static timing analysis using Synopsys Primetime.
The document discusses various techniques for process synchronization and solving the critical section problem in concurrent systems. It describes producer-consumer problems and solutions using shared memory. It covers issues like race conditions that can occur. Different algorithms for solving the critical section problem are presented, including Peterson's algorithm and the Bakery algorithm. The document also discusses synchronization hardware support and low-level synchronization tools like locks, test-and-set instructions, and semaphores.
The document discusses UART (Universal Asynchronous Receiver/Transmitter) and RS-232 communication standards. It describes the voltage levels used, the need for a converter chip between UART and RS-232, synchronous vs asynchronous transmission, baud rates, frame formats, and provides VHDL code for a UART transmitter and receiver implementation including state machines and registers.
This document contains lecture slides for CSE110 Principles of Programming with Java. It discusses loops and conditional statements like break, continue, and nested loops. It then presents a case study on implementing Tic Tac Toe in Java, with pseudocode showing how to initialize the game board, take user and computer moves, check for a winner or tie, and reprint the board. The slides are attributed to instructor Javier Gonzalez-Sanchez and provide his contact information.
The document discusses mutating and testing tests. It introduces the concept of mutation analysis, where tests are evaluated by seeding real bugs into the code and checking if the tests detect these bugs. The document provides an example of applying mutation analysis to a factorial function code and test cases. It finds bugs in the test cases like weak oracles and missing test inputs. The document also compares the Pit mutation testing tool with the Descartes tool, finding Descartes generates fewer but coarser-grained mutants, making it more scalable for large projects.
The document discusses different types of loops in C++ including for, while, do-while, and nested loops. It provides examples and syntax for each loop type. Key points covered include using counters to control loop repetition, conditional expressions to control loop execution, and using break and continue statements to alter normal loop flow. Examples provided include printing patterns, calculating sums, and getting input from the user.
Building Real Time Systems on MongoDB Using the Oplog at StripeMongoDB
MongoDB's oplog is possibly its most underrated feature. The oplog is vital as the basis on which replication is built, but its value doesn't stop there. Unlike the MySQL binlog, which is poorly documented and not directly exposed to MySQL clients, the oplog is a well-documented, structured format for changes that is query-able through the same mechanisms as your data. This allows many types of powerful, application-driven streaming or transformation. At Stripe, we've used the MongoDB oplog to create PostgresSQL, HBase, and ElasticSearch mirrors of our data. We've built a simple real-time trigger mechanism for detecting new data. And we've even used it to recover data. In this talk, we'll show you how we use the MongoDB oplog, and how you can build powerful reactive streaming data applications on top of it.
Building complex async applications is really hard. Whether you use callbacks, Promises, or EventEmitters, Error objects should have a place in your utility belt. They are indispensable when it comes to managing work flows in a highly asynchronous environment.
This talk covers patterns for using JavaScript Error (with a capital E) objects to build resilient applications, and introduce some modules that can be used to build errors with an elegant history of stack traces even through multiple asynchronous operations. Try/catch, callbacks, and other error handling mechanisms will be examined, revealing some potential deficiencies in the JavaScript language for dealing with errors.
Video: https://www.youtube.com/watch?v=PyCHbi_EqPs
This document contains C# code for Project Euler problem #104, which involves finding the first Fibonacci number with pandigital endings. The code defines functions for checking if a number contains the digits 1-k, adding two Fibonacci numbers, and converting an integer to an array. The main method takes in inputs a, b, and k, initializes the Fibonacci sequence with a and b, and iterates through calculating subsequent numbers until it finds one with pandigital endings from 1 to k or reaches 1000000 terms without finding a solution.
The document describes implementing up, down, and up/down counters using Verilog code. It includes:
1) Code for a 4-bit up counter that counts from 0 to 15 when the clock signal changes.
2) Code for a 4-bit down counter that counts from 15 to 0 when the clock signal changes.
3) Code for a 4-bit up/down counter that counts up when the up signal is high and down when the down signal is high, controlled by the clock.
C++ code is fraught with perils and pitfalls. That's why a thorough and meticulous code review is very important. The purpose of this talk is to (hopefully) improve your ability to take on such a task. We'll take a look at some error patterns easily overlooked. In all honesty, many people just don't know about them. Meet a dangerous emplace_back, an unexpected integer overflow, a skipped memset, perils of noexcept functions, and so on.
Yuri is a C++ developer at PVS-Studio. Currently working on the core features of the C++ static analyser made by the company.
YouTube: https://youtu.be/f1_Iwh33f9I
This document describes a hardware design that includes components like a codec clock, PLL, and packet memory. It maps these components, describes signal connections between them, and includes processes for transferring data between the memory and codec. The design takes in audio data at 2.048 MHz, converts it to 75 MHz using a PLL, stores it in packet memory, and outputs it to a codec. It handles transferring 160 bytes per packet across two memory banks.
An Introduction to Test Driven Development with ReactFITC
The document provides an introduction to test-driven development (TDD) and testing with JavaScript and React. It discusses the benefits of TDD such as early bug detection, clear code, and living documentation. It also covers frustrations with TDD. The document demonstrates TDD by incrementally developing a calculator app through testing examples, showing the red-green-refactor process and handling invalid inputs. It emphasizes that TDD helps improve code quality and avoids bugs but is not a "silver bullet" solution.
The document discusses algorithms and their analysis. It begins by explaining that in the pre-computer era, the focus was on computability theory and determining what could be computed. In the post-computer era, with Turing machines establishing ultimate computability, the focus shifted to complexity theory and how efficiently problems could be solved. It then provides definitions of key terms like algorithms, asymptotic notation, running time analysis, and examples of proof by induction and analyzing the running time of insertion sort.
This document provides instructions and examples for programming an Arduino microcontroller to control LEDs and respond to input. It introduces Arduino programming basics like setup(), loop(), pinMode(), digitalWrite(), and delay(). It demonstrates traffic light programs using variables, conditional statements like if/else, and ASCII input/output. Tasks include modifying programs to use variables, add conditions, respond to key presses, and create a Christmas light program with multiple modes selected by the user. The document is a tutorial for learning Arduino programming concepts through example projects.
The document describes interfacing an FPGA to an LCD 16x2 display. It includes a block diagram, pin descriptions, timing diagrams, LCD initialization procedures from the datasheet, and VHDL code to implement the LCD controller on the FPGA. The VHDL code uses a state machine and ROM-based model with an 8-bit data line to generate the LCD initialization sequence and display text on the LCD. Behavioral and post-route simulations are shown to verify the design works as intended.
This document provides an introduction to communication systems. It discusses the basic blocks of a communication system including the information source, transmitter, channel, receiver and destination. It also describes different types of communication systems such as simplex, duplex and half-duplex. Modes of communication including broadcast and point-to-point are explained. The document then covers modulation techniques, the need for modulation, and classifications of analog and digital modulation. It introduces the sampling theorem and discusses aliasing. Finally, it discusses pulse amplitude modulation as a type of pulse analog modulation.
This document discusses the design philosophy of integrated circuits and biasing techniques. It begins with an overview of constraints in IC design such as minimizing resistors and replacing them with transistors. It then discusses current sources, current mirrors, and current steering circuits which are used to generate constant currents for biasing multiple amplifier stages. The document compares MOSFET and BJT transistors. It explains that current sources use a transistor connected as a diode to generate a constant current, and current mirrors replicate this current. Current steering circuits distribute current from current sources to multiple locations. The document concludes with a brief section on the high frequency response of IC amplifiers.
The document discusses MOSFETs (metal-oxide-semiconductor field-effect transistors). It provides information on:
1) The structure of MOSFETs including typical dimensions of the gate length and width. It operates by using a voltage applied to the gate to control the conductivity between the drain and source.
2) The operation of n-channel and p-channel MOSFETs. In an n-channel MOSFET, applying a positive voltage to the gate creates an n-type inversion channel between the source and drain allowing current to flow.
3) Biasing techniques for MOSFET amplifiers including fixing the gate voltage, connecting a resistor in the source,
This document discusses color image processing and provides details on color fundamentals, color models, and pseudocolor image processing techniques. It introduces color image processing, full-color versus pseudocolor processing, and several color models including RGB, CMY, and HSI. Pseudocolor processing techniques of intensity slicing and gray level to color transformation are explained, where grayscale values in an image are assigned colors based on intensity ranges or grayscale levels.
This document discusses edge detection and image segmentation techniques. It begins with an introduction to segmentation and its importance. It then discusses edge detection, including edge models like steps, ramps, and roofs. Common edge detection techniques are described, such as using derivatives and filters to detect discontinuities that indicate edges. Point, line, and edge detection are explained through the use of filters like Laplacian filters. Thresholding techniques are introduced as a way to segment images into different regions based on pixel intensity values.
This document discusses various spatial filters used for image processing, including smoothing and sharpening filters. Smoothing filters are used to reduce noise and blur images, with linear filters performing averaging and nonlinear filters using order statistics like the median. Sharpening filters aim to enhance edges and details by using derivatives, with first derivatives calculated via gradient magnitude and second derivatives using the Laplacian operator. Specific filters covered include averaging, median, Sobel, and unsharp masking.
This document discusses image enhancement techniques in the spatial domain. It begins by introducing intensity transformations and spatial filtering as the two principal categories of spatial domain processing. It then describes the basics of intensity transformations, including how they directly manipulate pixel values in an image. The document focuses on different types of basic intensity transformation functions such as image negation, log transformations, power law transformations, and piecewise linear transformations. It provides examples of how these transformations can be used to enhance images. Finally, it discusses histogram processing and how the histogram of an image provides information about the distribution of pixel intensities.
This document is a resume for Mr. A. B. C, who graduated with an Electronics Engineering degree from Shivaji University in Kolhapur, India. The resume lists his objectives, expertise in 5 areas, hobbies, 4 projects undertaken with short descriptions, educational qualifications, co-curricular activities, extra-curricular activities, and 3 achievements.
This document contains lecture slides for CSE110 Principles of Programming with Java. It discusses loops and conditional statements like break, continue, and nested loops. It then presents a case study on implementing Tic Tac Toe in Java, with pseudocode showing how to initialize the game board, take user and computer moves, check for a winner or tie, and reprint the board. The slides are attributed to instructor Javier Gonzalez-Sanchez and provide his contact information.
The document discusses mutating and testing tests. It introduces the concept of mutation analysis, where tests are evaluated by seeding real bugs into the code and checking if the tests detect these bugs. The document provides an example of applying mutation analysis to a factorial function code and test cases. It finds bugs in the test cases like weak oracles and missing test inputs. The document also compares the Pit mutation testing tool with the Descartes tool, finding Descartes generates fewer but coarser-grained mutants, making it more scalable for large projects.
The document discusses different types of loops in C++ including for, while, do-while, and nested loops. It provides examples and syntax for each loop type. Key points covered include using counters to control loop repetition, conditional expressions to control loop execution, and using break and continue statements to alter normal loop flow. Examples provided include printing patterns, calculating sums, and getting input from the user.
Building Real Time Systems on MongoDB Using the Oplog at StripeMongoDB
MongoDB's oplog is possibly its most underrated feature. The oplog is vital as the basis on which replication is built, but its value doesn't stop there. Unlike the MySQL binlog, which is poorly documented and not directly exposed to MySQL clients, the oplog is a well-documented, structured format for changes that is query-able through the same mechanisms as your data. This allows many types of powerful, application-driven streaming or transformation. At Stripe, we've used the MongoDB oplog to create PostgresSQL, HBase, and ElasticSearch mirrors of our data. We've built a simple real-time trigger mechanism for detecting new data. And we've even used it to recover data. In this talk, we'll show you how we use the MongoDB oplog, and how you can build powerful reactive streaming data applications on top of it.
Building complex async applications is really hard. Whether you use callbacks, Promises, or EventEmitters, Error objects should have a place in your utility belt. They are indispensable when it comes to managing work flows in a highly asynchronous environment.
This talk covers patterns for using JavaScript Error (with a capital E) objects to build resilient applications, and introduce some modules that can be used to build errors with an elegant history of stack traces even through multiple asynchronous operations. Try/catch, callbacks, and other error handling mechanisms will be examined, revealing some potential deficiencies in the JavaScript language for dealing with errors.
Video: https://www.youtube.com/watch?v=PyCHbi_EqPs
This document contains C# code for Project Euler problem #104, which involves finding the first Fibonacci number with pandigital endings. The code defines functions for checking if a number contains the digits 1-k, adding two Fibonacci numbers, and converting an integer to an array. The main method takes in inputs a, b, and k, initializes the Fibonacci sequence with a and b, and iterates through calculating subsequent numbers until it finds one with pandigital endings from 1 to k or reaches 1000000 terms without finding a solution.
The document describes implementing up, down, and up/down counters using Verilog code. It includes:
1) Code for a 4-bit up counter that counts from 0 to 15 when the clock signal changes.
2) Code for a 4-bit down counter that counts from 15 to 0 when the clock signal changes.
3) Code for a 4-bit up/down counter that counts up when the up signal is high and down when the down signal is high, controlled by the clock.
C++ code is fraught with perils and pitfalls. That's why a thorough and meticulous code review is very important. The purpose of this talk is to (hopefully) improve your ability to take on such a task. We'll take a look at some error patterns easily overlooked. In all honesty, many people just don't know about them. Meet a dangerous emplace_back, an unexpected integer overflow, a skipped memset, perils of noexcept functions, and so on.
Yuri is a C++ developer at PVS-Studio. Currently working on the core features of the C++ static analyser made by the company.
YouTube: https://youtu.be/f1_Iwh33f9I
This document describes a hardware design that includes components like a codec clock, PLL, and packet memory. It maps these components, describes signal connections between them, and includes processes for transferring data between the memory and codec. The design takes in audio data at 2.048 MHz, converts it to 75 MHz using a PLL, stores it in packet memory, and outputs it to a codec. It handles transferring 160 bytes per packet across two memory banks.
An Introduction to Test Driven Development with ReactFITC
The document provides an introduction to test-driven development (TDD) and testing with JavaScript and React. It discusses the benefits of TDD such as early bug detection, clear code, and living documentation. It also covers frustrations with TDD. The document demonstrates TDD by incrementally developing a calculator app through testing examples, showing the red-green-refactor process and handling invalid inputs. It emphasizes that TDD helps improve code quality and avoids bugs but is not a "silver bullet" solution.
The document discusses algorithms and their analysis. It begins by explaining that in the pre-computer era, the focus was on computability theory and determining what could be computed. In the post-computer era, with Turing machines establishing ultimate computability, the focus shifted to complexity theory and how efficiently problems could be solved. It then provides definitions of key terms like algorithms, asymptotic notation, running time analysis, and examples of proof by induction and analyzing the running time of insertion sort.
This document provides instructions and examples for programming an Arduino microcontroller to control LEDs and respond to input. It introduces Arduino programming basics like setup(), loop(), pinMode(), digitalWrite(), and delay(). It demonstrates traffic light programs using variables, conditional statements like if/else, and ASCII input/output. Tasks include modifying programs to use variables, add conditions, respond to key presses, and create a Christmas light program with multiple modes selected by the user. The document is a tutorial for learning Arduino programming concepts through example projects.
The document describes interfacing an FPGA to an LCD 16x2 display. It includes a block diagram, pin descriptions, timing diagrams, LCD initialization procedures from the datasheet, and VHDL code to implement the LCD controller on the FPGA. The VHDL code uses a state machine and ROM-based model with an 8-bit data line to generate the LCD initialization sequence and display text on the LCD. Behavioral and post-route simulations are shown to verify the design works as intended.
This document provides an introduction to communication systems. It discusses the basic blocks of a communication system including the information source, transmitter, channel, receiver and destination. It also describes different types of communication systems such as simplex, duplex and half-duplex. Modes of communication including broadcast and point-to-point are explained. The document then covers modulation techniques, the need for modulation, and classifications of analog and digital modulation. It introduces the sampling theorem and discusses aliasing. Finally, it discusses pulse amplitude modulation as a type of pulse analog modulation.
This document discusses the design philosophy of integrated circuits and biasing techniques. It begins with an overview of constraints in IC design such as minimizing resistors and replacing them with transistors. It then discusses current sources, current mirrors, and current steering circuits which are used to generate constant currents for biasing multiple amplifier stages. The document compares MOSFET and BJT transistors. It explains that current sources use a transistor connected as a diode to generate a constant current, and current mirrors replicate this current. Current steering circuits distribute current from current sources to multiple locations. The document concludes with a brief section on the high frequency response of IC amplifiers.
The document discusses MOSFETs (metal-oxide-semiconductor field-effect transistors). It provides information on:
1) The structure of MOSFETs including typical dimensions of the gate length and width. It operates by using a voltage applied to the gate to control the conductivity between the drain and source.
2) The operation of n-channel and p-channel MOSFETs. In an n-channel MOSFET, applying a positive voltage to the gate creates an n-type inversion channel between the source and drain allowing current to flow.
3) Biasing techniques for MOSFET amplifiers including fixing the gate voltage, connecting a resistor in the source,
This document discusses color image processing and provides details on color fundamentals, color models, and pseudocolor image processing techniques. It introduces color image processing, full-color versus pseudocolor processing, and several color models including RGB, CMY, and HSI. Pseudocolor processing techniques of intensity slicing and gray level to color transformation are explained, where grayscale values in an image are assigned colors based on intensity ranges or grayscale levels.
This document discusses edge detection and image segmentation techniques. It begins with an introduction to segmentation and its importance. It then discusses edge detection, including edge models like steps, ramps, and roofs. Common edge detection techniques are described, such as using derivatives and filters to detect discontinuities that indicate edges. Point, line, and edge detection are explained through the use of filters like Laplacian filters. Thresholding techniques are introduced as a way to segment images into different regions based on pixel intensity values.
This document discusses various spatial filters used for image processing, including smoothing and sharpening filters. Smoothing filters are used to reduce noise and blur images, with linear filters performing averaging and nonlinear filters using order statistics like the median. Sharpening filters aim to enhance edges and details by using derivatives, with first derivatives calculated via gradient magnitude and second derivatives using the Laplacian operator. Specific filters covered include averaging, median, Sobel, and unsharp masking.
This document discusses image enhancement techniques in the spatial domain. It begins by introducing intensity transformations and spatial filtering as the two principal categories of spatial domain processing. It then describes the basics of intensity transformations, including how they directly manipulate pixel values in an image. The document focuses on different types of basic intensity transformation functions such as image negation, log transformations, power law transformations, and piecewise linear transformations. It provides examples of how these transformations can be used to enhance images. Finally, it discusses histogram processing and how the histogram of an image provides information about the distribution of pixel intensities.
This document is a resume for Mr. A. B. C, who graduated with an Electronics Engineering degree from Shivaji University in Kolhapur, India. The resume lists his objectives, expertise in 5 areas, hobbies, 4 projects undertaken with short descriptions, educational qualifications, co-curricular activities, extra-curricular activities, and 3 achievements.
The document discusses the differences between a bio-data, resume, and CV and provides guidance on key components and formatting for an effective resume. It notes that a bio-data summarizes basic personal information, a resume summarizes skills and experience for a new job in 2 pages or less, and a CV provides more detailed experience and qualifications that can be multiple pages. The document then provides tips and examples for important resume sections like objectives, personal information, projects, qualifications, computer skills, activities, hobbies, and contact details.
The document discusses digital image processing. It begins by defining an image and describing how images are represented digitally. It then outlines the main steps in digital image processing, including acquisition, enhancement, restoration, segmentation, representation, and recognition. It also discusses the key components of an image processing system, including hardware, software, storage, displays, and networking. Finally, it provides examples of application areas for digital image processing such as medical imaging, satellite imaging, and industrial inspection.
Blooms Taxonomy in Engineering EducationA B Shinde
The document discusses Bloom's Taxonomy and its application in examination design. It explains how Bloom's Taxonomy can help classify learning objectives into cognitive, affective, and behavioral domains. It also describes how the revised taxonomy further divides the cognitive domain into six levels of complexity. The document provides examples of action verbs and sample questions that assess different levels of cognitive ability based on Bloom's Taxonomy, from lower order thinking skills to higher order skills. It emphasizes the importance of using Bloom's Taxonomy to ensure examination questions evaluate students' abilities at various levels of complexity.
This document provides a step-by-step demonstration of using the Xilinx ISE 7.1i Project Navigator software to design digital circuits. It shows how to create a new project, add VHDL files, check for syntax errors, synthesize the design, and simulate the circuit using a testbench. Specifically, it demonstrates creating a half adder circuit by developing the VHDL code, testbench, and viewing the simulated output waveforms. It then adds another VHDL file to implement a full adder and shows the synthesized logic gates. The document serves as a tutorial for using Xilinx's digital design software to design basic combinational logic circuits.
This document is a lab manual for a digital system design course. It contains documentation and code for various digital logic components including half adders, full adders, 4-bit and 16-bit magnitude comparators, up/down counters, decoders, and other basic building blocks. For each component, it provides entity diagrams, architecture diagrams, device utilization summaries from synthesis, and simulation waveforms. The manual was prepared by an instructor to provide materials and guidance for students in learning digital logic design.
This document discusses various VLSI testing techniques. It begins by explaining the need for testing circuits when they are first developed and manufactured to check that they meet specifications. The main testing approach is to apply test inputs and compare the outputs to expected patterns. It then describes different testing techniques for combinational and sequential circuits, including fault modeling, path sensitizing, scan path testing, built-in self-test (BIST), boundary scan testing, and signature analysis. Specific circuit examples are provided to illustrate scan path testing, BIST using linear feedback shift registers (LFSRs) and compressor circuits, and boundary scan testing.
The document provides guidance on selecting an engineering project for final or pre-final year students. It advises students to choose an improvement on an existing problem rather than an entirely new idea. It also stresses selecting a project the entire team is interested in and ensuring the budget, tools, and supervisor's consent are considered. Students are encouraged to focus on their interests, browse trending technologies, check feasibility, and identify challenges upfront to help complete their project successfully.
This presentation covers the basic guidelines regarding how to face the interview including resume writing, aptitude test, group discussion and facing interview confidently...
This document discusses semiconductors and their properties. It explains that semiconductors have electrical conductivity between conductors and insulators. Their valence and conduction bands are almost full and empty respectively, with a small energy gap that allows electrons to cross over with a smaller electric field compared to insulators. Common semiconductors like silicon and germanium form covalent bonds and have crystalline structures. Doping semiconductors with impurities can create an excess or shortage of electrons, making them either n-type or p-type semiconductors respectively.
1. The document discusses the V-I characteristics of a p-n junction diode and describes its behavior under zero external voltage, forward bias, and reverse bias.
2. Rectifiers are introduced as circuits that convert AC to DC. Half-wave and full-wave rectifiers are described, including their circuit arrangements and operations. Centre-tap and bridge configurations are covered for full-wave rectification.
3. Zener diodes are discussed as properly doped diodes with a sharp breakdown voltage. They are always connected in reverse bias and have a defined zener voltage.
The document provides an overview of basic electronics engineering concepts including:
1. The evolution of electronics from early experiments with vacuum tubes in the 1850s to the invention of the transistor in 1947 and integrated circuits in 1958.
2. Atomic structure including Bohr's atomic model, quantum numbers, and the periodic table which orders elements by atomic number and electron configuration.
3. How electrons behave in solids, forming energy bands, and the types of bonding that occur between atoms in solids including metallic, covalent and ionic bonding.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
International Conference on NLP, Artificial Intelligence, Machine Learning an...gerogepatton
International Conference on NLP, Artificial Intelligence, Machine Learning and Applications (NLAIM 2024) offers a premier global platform for exchanging insights and findings in the theory, methodology, and applications of NLP, Artificial Intelligence, Machine Learning, and their applications. The conference seeks substantial contributions across all key domains of NLP, Artificial Intelligence, Machine Learning, and their practical applications, aiming to foster both theoretical advancements and real-world implementations. With a focus on facilitating collaboration between researchers and practitioners from academia and industry, the conference serves as a nexus for sharing the latest developments in the field.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Understanding Inductive Bias in Machine LearningSUTEJAS
This presentation explores the concept of inductive bias in machine learning. It explains how algorithms come with built-in assumptions and preferences that guide the learning process. You'll learn about the different types of inductive bias and how they can impact the performance and generalizability of machine learning models.
The presentation also covers the positive and negative aspects of inductive bias, along with strategies for mitigating potential drawbacks. We'll explore examples of how bias manifests in algorithms like neural networks and decision trees.
By understanding inductive bias, you can gain valuable insights into how machine learning models work and make informed decisions when building and deploying them.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
Comparative analysis between traditional aquaponics and reconstructed aquapon...
VHDL Coding Syntax
1. ___________________________________________________________________________VHDL Syntax
1 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Dr. V. P. Shetkari Shikshan Mandal’s
Padmabhooshan Vasantraodada Patil Institute of Technology,
Budhgaon-416304
Digital System Design
LAB MANUAL
Prepared by
Mr. A. B. Shinde
Assiatant Profesor,
Electronics Engineering
abshinde.eln@pvpitsangli,edu.in
Department of Electronics Engineering
2013-14
2. ___________________________________________________________________________VHDL Syntax
2 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
ADDER / SUBTRACTOR
process (<input1>, <input2>)
begin
if <add_sub> = '1' then
<addsub_output> <= <input1> + <input2>;
else
<addsub_output> <= <input1> - <input2>;
end if;
end process;
Adder with carry in
<output> <= <input1> + <input2> + <one_bit_carry_in>;
Adder with carry out
<temp_value> <= <input1> + <input2>;
<output_sum> <= <temp_value>((<adder_width>-1) downto 0);
<carry_out> <= <temp_value>(<adder_width>);
Simple Adder
<output> <= <input1> + <input2>;
3. ___________________________________________________________________________VHDL Syntax
3 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
COMPARATOR
Equal
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> = <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Greater than
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> > <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Greater than or equal
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> >= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
4. ___________________________________________________________________________VHDL Syntax
4 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Less than
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> < <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Less than or equal
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> <= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
Not equal
process(<clock>,<reset>)
begin
if (<reset> = '1') then
<output> <= '0';
elsif (<clock>'event and <clock> ='1') then
if ( <input1> /= <input2> ) then
<output> <= '1';
else
<output> <= '0';
end if;
end if;
end process;
5. ___________________________________________________________________________VHDL Syntax
5 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Synchronous Multiplier
process (<clock>)
begin
if <clock>='1' and <clock>'event then
<output> <= <input1> * <input2>;
end if;
end process;
Asynchronous Multiplier
<output> <= <input1> * <input2>;
Subtractor
<output> <= <input1> - <input2>;
Logic gates
AND
<output> <= <input1> and <input2> and <input3>;
INVETER
<output> <= not <input1>;
NAND
<output> <= not (<input1> and <input2> and <input3>);
OR
<output> <= <input1> or <input2> or <input3>;
NOR
<output> <= not (<input1> or <input2> or <input3>);
XNOR
<output> <= not(<input1> xor <input2> xor <input3>);
XOR
<output> <= <input1> xor <input2> xor <input3>;
6. ___________________________________________________________________________VHDL Syntax
6 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Counters
Binary Down Counter
process (<clock>)
begin
if <clock>='1' and <clock>'event then
if <clock_enable>='1' then
<count> <= <count> - 1;
end if;
end if;
end process;
CE, Asynchronous active high Reset
process (<clock>, <reset>)
begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
<count> <= <count> - 1;
end if;
end if;
end process;
CE Asynchronous active low Reset
process (<clock>, <reset>)
begin
if <reset>='0' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
<count> <= <count> - 1;
end if;
end if;
end process;
7. ___________________________________________________________________________VHDL Syntax
7 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>, <reset>)
begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end process;
Simple Counter
process (<clock>)
begin
if <clock>='1' and <clock>'event then
<count> <= <count> - 1;
end if;
end process;
8. ___________________________________________________________________________VHDL Syntax
8 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Up Counters
process (<clock>)
begin
if <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
9. ___________________________________________________________________________VHDL Syntax
9 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='1' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<count> <= (others => '0');
elsif <clock>='1' and <clock>'event then
if <clock_enable>='1' then
if <load_enable>='1' then
<count> <= <input>;
else
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end if;
end if;
end process;
10. ___________________________________________________________________________VHDL Syntax
10 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>)
begin
if <clock>='1' and <clock>'event then
if <count_direction>='1' then
<count> <= <count> + 1;
else
<count> <= <count> - 1;
end if;
end if;
end process;
Gray Code Converter
<next_binary_count> <= <binary_count> + 1;
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<binary_count> <= (others => '0');
<gray_count> <= (others =>'0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<binary_count> <= <next_binary_count>;
<gray_count> <= (('0' & next_binary_count(<width-1> downto 1))
XOR <next_binary_count>);
end if;
end if;
end process;
11. ___________________________________________________________________________VHDL Syntax
11 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
LFSR
16 bit
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<reg_name> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<reg_name>(15 downto 1) <= <reg_name>(14 downto 0) ;
<reg_name>(0) <= not(<reg_name>(15) XOR <reg_name>(14) XOR
<reg_name>(13) XOR <reg_name>(4));
end if;
end if;
end process;
32 bit
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<reg_name> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<reg_name>(31 downto 1) <= <reg_name>(30 downto 0) ;
<reg_name>(0) <= not(<reg_name>(31) XOR <reg_name>(22) XOR
<reg_name>(2) XOR <reg_name>(1));
end if;
end if;
end process;
4 bit
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<reg_name> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<reg_name>(3 downto 1) <= <reg_name>(2 downto 0) ;
<reg_name>(0) <= not(<reg_name>(4) XOR <reg_name>(3));
end if;
end if;
end process;
12. ___________________________________________________________________________VHDL Syntax
12 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
8 bit
process(<clock>,<reset>)
begin
if ( <reset> = '1') then
<reg_name> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
if <clock_enable>='1' then
<reg_name>(7 downto 1) <= <reg_name>(6 downto 0) ;
<reg_name>(0) <= not(<reg_name>(7) XOR <reg_name>(6) XOR
<reg_name>(4));
end if;
end if;
end process;
Decoders
2:4
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= "0000";
elsif ( <clock>'event and <clock> ='1') then
case <input> is
when "00" => <output> <= "0001";
when "01" => <output> <= "0010";
when "10" => <output> <= "0100";
when "11" => <output> <= "1000";
when others => "0000";
end case;
end if;
end process;
13. ___________________________________________________________________________VHDL Syntax
13 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
3:8
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= "00000000";
elsif ( <clock>'event and <clock> ='1') then
case <input> is
when "000" => <output> <= "00000001";
when "001" => <output> <= "00000010";
when "010" => <output> <= "00000100";
when "011" => <output> <= "00001000";
when "100" => <output> <= "00010000";
when "101" => <output> <= "00100000";
when "110" => <output> <= "01000000";
when "111" => <output> <= "10000000";
when others => "00000000";
end case;
end if;
end process;
Encoders
2:4
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= "00";
elsif ( <clock>'event and <clock> ='1') then
case <input> is
when "0001" => <output> <= "00";
when "0010" => <output> <= "01";
when "0100" => <output> <= "10";
when "1000" => <output> <= "11";
when others => "00";
end case;
end if;
end process;
14. ___________________________________________________________________________VHDL Syntax
14 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
8:3
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= "000";
elsif ( <clock>'event and <clock> ='1') then
case <input> is
when "00000001" => <output> <= "000";
when "00000010" => <output> <= "001";
when "00000100" => <output> <= "010";
when "00001000" => <output> <= "011";
when "00010000" => <output> <= "100";
when "00100000" => <output> <= "101";
when "01000000" => <output> <= "110";
when "10000000" => <output> <= "111";
when others => "000";
end case;
end if;
end process;
D-FF
process (<clock>)
begin
if <clock>'event and <clock>='0' then
<output> <= <input>;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='0') then
<output> <= <input>;
end if;
end process;
15. ___________________________________________________________________________VHDL Syntax
15 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>, <reset>)
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='0') then
if <clock_enable> = '1' then
<output> <= <input>;
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<output> <= '0';
elsif (<clock>'event and <clock>='0') then
<output> <= <input>;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<output> <= '0';
elsif (<clock>'event and <clock>='0') then
if <clock_enable> = '1' then
<output> <= <input>;
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='0' then
if <reset>='1' then
<output> <= '0';
else
<output> <= <input>;
end if;
end if;
end process;
16. ___________________________________________________________________________VHDL Syntax
16 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>)
begin
if <clock>'event and <clock>='0' then
if <reset>='1' then
<output> <= '0';
elsif <clock_enable> ='1' then
<output> <= <input>;
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='0' then
if <reset>='0' then
<output> <= '0';
else
<output> <= <input>;
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='0' then
if <reset>='0' then
<output> <= '0';
elsif <clock_enable> ='1' then
<output> <= <input>;
end if;
end if;
end process;
T-FF
process (<clock>)
begin
if <clock>'event and <clock>='1' then
<output> <= not(<output>);
end if;
end process;
17. ___________________________________________________________________________VHDL Syntax
17 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>, <reset>)
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
<output> <= not(<output>);
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='1' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
if <clock_enable> = '1' then
<output> <= not(<output>);
end if;
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
<output> <= not(<output>);
end if;
end process;
process (<clock>, <reset>)
begin
if <reset>='0' then
<output> <= '0';
elsif (<clock>'event and <clock>='1') then
if <clock_enable> = '1' then
<output> <= not(<output>);
end if;
end if;
end process;
18. ___________________________________________________________________________VHDL Syntax
18 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>)
begin
if <clock>'event and <clock>='1' then
if <reset>='1' then
<output> <= '0';
else
<output> <= not(<output>);
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='1' then
if <reset>='1' then
<output> <= '0';
elsif <clock_enable> ='1' then
<output> <= not(<output>);
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='1' then
if <reset>='0' then
<output> <= '0';
else
<output> <= not(<output>);
end if;
end if;
end process;
process (<clock>)
begin
if <clock>'event and <clock>='1' then
if <reset>='0' then
<output> <= '0';
elsif <clock_enable> ='1' then
<output> <= not(<output>);
end if;
19. ___________________________________________________________________________VHDL Syntax
19 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
end if;
end process;
Logical Shifters
2bit
--use IEEE.numeric_std.all;
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
case <selector> is
when "00" => <output> <= <input> ;
when "01" => <output> <= <input> sll 1;
when "10" => <output> <= <input> sll 2;
when "11" => <output> <= <input> sll 3;
when others => <output> <= <input> ;
end case;
end if;
end process;
3 bit
--use IEEE.numeric_std.all;
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
case <selector> is
when "000" => <output> <= <input> ;
when "001" => <output> <= <input> sll 1;
when "010" => <output> <= <input> sll 2;
when "011" => <output> <= <input> sll 3;
when "100" => <output> <= <input> sll 4;
when "101" => <output> <= <input> sll 5;
when "110" => <output> <= <input> sll 6;
when "111" => <output> <= <input> sll 7;
when others => <output> <= <input> ;
end case;
end if;
end process;
20. ___________________________________________________________________________VHDL Syntax
20 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
4 bit
--use IEEE.numeric_std.all;
process(<clock>,<reset>,<input>)
begin
if ( <reset> = '1') then
<output> <= (others => '0');
elsif ( <clock>'event and <clock> ='1') then
case <selector> is
when "0000" => <output> <= <input> ;
when "0001" => <output> <= <input> sll 1;
when "0010" => <output> <= <input> sll 2;
when "0011" => <output> <= <input> sll 3;
when "0100" => <output> <= <input> sll 4;
when "0101" => <output> <= <input> sll 5;
when "0110" => <output> <= <input> sll 6;
when "0111" => <output> <= <input> sll 7;
when "1000" => <output> <= <input> sll 8;
when "1001" => <output> <= <input> sll 9;
when "1010" => <output> <= <input> sll 10;
when "1011" => <output> <= <input> sll 11;
when "1100" => <output> <= <input> sll 12;
when "1101" => <output> <= <input> sll 13;
when "1110" => <output> <= <input> sll 14;
when "1111" => <output> <= <input> sll 15;
when others => <output> <= <input> ;
end case;
end if;
end process;
HEX to SEVEN SEGMENT CONVERSION
-- HEX: in STD_LOGIC_VECTOR (3 downto 0);
-- LED: out STD_LOGIC_VECTOR (6 downto 0);
-- segment encoinputg
-- 0
-- 5 | | 1
-- --- <- 6
-- 4 | | 2
-- 3
21. ___________________________________________________________________________VHDL Syntax
21 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
with HEX SELect
LED<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
Barrel Shifter
-- 16-bit right shift barrel shifter
-- SEL: in STD_LOGIC_VECTOR(3 downto 0);
-- B_INPUT: in STD_LOGIC_VECTOR(15 downto 0);
-- B_OUTPUT: out STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal SEL_A, SEL_B: STD_LOGIC_VECTOR(1 downto 0);
signal C: STD_LOGIC_VECTOR(15 downto 0);
--**Insert the following after the 'begin' keyword**
SEL_A <= SEL(1 downto 0);
SEL_B <= SEL(3 downto 2);
process(SEL_A,B_INPUT)
begin
case SEL_A is
when "00" => --shift by 0
C <= B_INPUT;
when "01" => --shift by 1
C(15) <= B_INPUT(0);
22. ___________________________________________________________________________VHDL Syntax
22 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
C(14 downto 0) <= B_INPUT(15 downto 1);
when "10" => --shift by 2
C(15 downto 14) <= B_INPUT(1 downto 0);
C(13 downto 0) <= B_INPUT(15 downto 2);
when "11" => --shift by 3
C(15 downto 13) <= B_INPUT(2 downto 0);
C(12 downto 0) <= B_INPUT(15 downto 3);
when others =>
C <= B_INPUT;
end case;
end process;
process(SEL_B,C)
begin
case SEL_B is
when "00" => --shift by 0 more
B_OUTPUT <= C;
when "01" => --shift by 4 more
B_OUTPUT(15 downto 12) <= C(3 downto 0);
B_OUTPUT(11 downto 0) <= C(15 downto 4);
when "10" => --shift by 8 more
B_OUTPUT(15 downto 8) <= C(7 downto 0);
B_OUTPUT(7 downto 0) <= C(15 downto 8);
when "11" => --shift by 12 more
B_OUTPUT(15 downto 4) <= C(11 downto 0);
B_OUTPUT(3 downto 0) <= C(15 downto 12);
when others =>
B_OUTPUT <= C;
end case;
end process;
Debounce Circuit
-- Provides a one-shot pulse from a non-clock input, with reset
-- D_IN: in STD_LOGIC;
-- RESET: in STD_LOGIC;
-- clock: in STD_LOGIC;
-- Q_OUT: out STD_LOGIC);
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal Q1, Q2, Q3 : std_logic;
23. ___________________________________________________________________________VHDL Syntax
23 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
--**Insert the following after the 'begin' keyword**
process(clock, RESET)
begin
if (RESET = '1') then
Q1 <= '0';
Q2 <= '0';
Q3 <= '0';
elsif (<clock>'event and <clock> = '1') then
Q1 <= D_IN;
Q2 <= Q1;
Q3 <= Q2;
end if;
end process;
Q_OUT <= Q1 and Q2 and (not Q3);
Multiplexers
2:1
<output> <= <input1> WHEN <selector> ='1' ELSE
<input2>;
4:1
process (<selector>,<input1>,<input2>,<input3>,<input4>)
begin
case <selector> is
when "00" => <output> <= <input1>;
when "01" => <output> <= <input2>;
when "10" => <output> <= <input3>;
when "11" => <output> <= <input4>;
when others => <output> <= <input1>;
end case;
end process;
24. ___________________________________________________________________________VHDL Syntax
24 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
8:1
process(<selector>,<input1>,<input2>,<input3>,<input4>,<input5>,<input6>,<input7>,
<in put8>)
begin
case <selector> is
when "000" => <output> <= <input1>;
when "001" => <output> <= <input2>;
when "010" => <output> <= <input3>;
when "011" => <output> <= <input4>;
when "100" => <output> <= <input5>;
when "101" => <output> <= <input6>;
when "110" => <output> <= <input7>;
when "111" => <output> <= <input8>;
when others => <output> <= <input1>;
end case;
end process;
BLOCK RAM
Dual port
1 clock
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
end if;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;
25. ___________________________________________________________________________VHDL Syntax
25 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
1 clock
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<write_enable> = '1') then
<ram_name>(conv_integer(<write_address>)) <= <input_data>;
<ram_output> <= <ram_name>(conv_integer(<read_address>));
end if;
end if;
end process;
2 clocks
process (<clockA>)
begin
if (<clockA>'event and <clockA> = '1') then
if (<enableA> = '1') then
if (<write_enableA> = '1') then
<ram_name>(conv_integer(<addressA>)) <= <input_dataA>;
<ram_outputA> <= <ram_name>(conv_integer(<addressA>));
end if;
end if;
end if;
end process;
process (<clockB>)
begin
if (<clockB>'event and <clockB> = '1') then
if (<enableB> = '1') then
<ram_outputB> <= <ram_name>(conv_integer(<addressB>));
end if;
end if;
end process;
26. ___________________________________________________________________________VHDL Syntax
26 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Single Port RAM
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<ram_enable> = '1') then"
if (<write_enable> = '1') then
<ram_name>(conv_integer(<address>)) <= <input_data>;
else
<ram_output> <= <ram_name>(conv_integer(<address>));
end if;
end if;
end if;
end process;
Read first
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<ram_enable> = '1') then"
if (<write_enable> = '1') then
<ram_name>(conv_integer(<address>)) <= <input_data>;
<ram_output> <= <ram_name>(conv_integer(<address>));
end if;
end if;
end if;
end process;
write first
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<ram_enable> = '1') then"
if (<write_enable> = '1') then
<ram_name>(conv_integer(<address>)) <= <input_data>;
<ram_output> <= <input_data>;
else
<ram_output> <= <ram_name>(conv_integer(<address>));
end if;
end if;
end if;
end process;
27. ___________________________________________________________________________VHDL Syntax
27 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
DITRIBUTED RAM
Dual port, Asynch read
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<write_enable> = '1') then
<ram_name>(conv_integer(<write_address>)) <= <input_data>;
end if;
end if;
end process;
<ram_output> <= <ram_name>(conv_integer(<read_address>));
Single port, Asynch read
process (<clock>)
begin
if (<clock>'event and <clock> = '1') then
if (<write_enable> = '1') then
<ram_name>(conv_integer(<address>)) <= <input_data>;
end if;
end if;
end process;
<ram_output> <= <ram_name>(conv_integer(<address>));
SHIFT REGISTERS
Dynamic
process (<clock>,<reset>)
begin
if <clock>'event and <clock>='1' then
if <clock_enable> = '1' then
<reg_name> <= reg_name((<width>-2) downto 0) & <input>;
end if;
end if;
end process;
<output> <= <reg_name>(<index>);
28. ___________________________________________________________________________VHDL Syntax
28 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
PIPO
process (<clock>,<reset>)
begin
if <reset> ='1' then
<reg_name> <= (others => '0');
elsif <load_enable> = '1' then
<reg_name> <= <input>;
elsif <clock>'event and <clock>='1' then
if <clock_enable> = '1' then
<reg_name> <= reg_name((<width>-2) downto 0) & '0';
end if;
end if;
<output> <= <reg_name>;
end process;
PISO
process (<clock>,<reset>)
begin
if <reset> ='1' then
<reg_name> <= (others => '0');
elsif <load_enable> = '1' then
<reg_name> <= <input>;
elsif <clock>'event and <clock>='1' then
if <clock_enable> = '1' then
<reg_name> <= reg_name((<width>-2) downto 0) & '0';
end if;
end if;
<output> <= <reg_name>(<width> - 1);
end process;
SIPO
process (<clock>,<reset>)
begin
if <reset> ='1' then
<reg_name> <= (others => '0');
elsif <clock>'event and <clock>='1' then
if <clock_enable> = '1' then
<reg_name> <= reg_name((<width>-2) downto 0) & <input>;
end if;
end if;
<output> <= <reg_name>;
end process;
29. ___________________________________________________________________________VHDL Syntax
29 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
SISO
process (<clock>,<reset>)
begin
if <reset> ='1' then
<reg_name> <= (others => '0');
elsif <clock>'event and <clock>='1' then
if <clock_enable> = '1' then
<reg_name> <= reg_name((<width>-2) downto 0) & <input>;
end if;
end if;
<output> <= <reg_name>(<width> - 1);
end process;
CASE STATEMENT
case (<2-bit select>) is
when "000" =>
<statement>;
when "001" =>
<statement>;
when "010" =>
<statement>;
when others =>
<statement>;
end case;
IF-ELSIF-ELSE
if <condition> then
<statement>
elsif <condition> then
<statement>
else
<statement>
end if;
WITH _____ SELECT
with <choice_expression> select
<name> <= <expression> when <choices>,
<expression> when <choices>,
<expression> when others;
30. ___________________________________________________________________________VHDL Syntax
30 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
WHEN _ELSE
<name> <= <expression> when <condition> else
<expression> when <condition> else
<expression>;
Generate
Conditional
<LABEL_1>:
if <condition> generate
begin
<statement>;
end generate;
Multiple
<LABEL_1>:
for <name> in <lower_limit> to <upper_limit> generate
begin
<statement>;
<statement>;
end generate;
LOOP
For Loop
for <name> in <lower_limit> to <upper_limit> loop
<statement>;
<statement>;
end loop;
While Loop
while <condition> loop
<statement>;
<statement>;
end loop;
Process
Combinatorial
process (<all_input_signals_seperated_by_commas>)
begin
<statements>;
end process;
31. ___________________________________________________________________________VHDL Syntax
31 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>,<async_reset>)
begin
if <async_reset> = '1' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
if <sync_reset> = '1' then
<statements>;
else
<statements>;
end if;
end if;
end process;
process (<clock>,<async_reset>)
begin
if <async_reset> = '0' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
if <sync_reset> = '0' then
<statements>;
else
<statements>;
end if;
end if;
end process;
process (<clock>,<reset>)
begin
if <reset> = '1' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
<statements>;
end if;
end process;
32. ___________________________________________________________________________VHDL Syntax
32 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>,<reset>)
begin
if <reset> = '1' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
if <clock_enable> = '1' then
<statements>;
end if;
end if;
end process;
process (<clock>,<reset>)
begin
if <reset> = '0' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
<statements>;
end if;
end process;
process (<clock>,<reset>)
begin
if <reset> = '0' then
<statements>;
elsif (<clock>'event and <clock> = '1') then
if <clock_enable> = '1' then
<statements>;
end if;
end if;
end process;
process (<clock>)
begin
if (<clock>'event and <clock> = '1'>) then
if <reset> = '1' then
<statements>;
else
<statements>;
end if;
end if;
end process;
33. ___________________________________________________________________________VHDL Syntax
33 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
process (<clock>)
begin
if (<clock>'event and <clock> = '1'>) then
if <reset> = '0' then
<statements>;
else
<statements>;
end if;
end if;
end process;
Constant Declaration
constant <name>: <type> := <value>;
Signal Dec
signal <name>: <type> := <value>;
Signal Dec Multiple
signal <name>: std_logic:= '0';
signal <name>: std_logic_vector(15 downto 0):= x"0000";
signal <name>: std_logic_vector(1 downto 0):= "00";
signal <name>: std_logic_vector(2 downto 0):= "000";
signal <name>: std_logic_vector(31 downto 0):= x"00000000";
signal <name>: std_logic_vector(3 downto 0):= "0000";
Variable Dec
variable <name>: <type> := <value>;
Variable Dec Multiple
variable <name>: std_logic:= '0';
variable <name>: std_logic_vector(15 downto 0):= x"0000";
variable <name>: std_logic_vector(1 downto 0):= "00";
variable <name>: std_logic_vector(2 downto 0):= "000";
variable <name>: std_logic_vector(31 downto 0):= x"00000000";
variable <name>: std_logic_vector(3 downto 0):= "0000";
34. ___________________________________________________________________________VHDL Syntax
34 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
Mealy State Machine
-- This is a sample state machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
--Insert the following in the architecture before the begin keyword
--Use descriptive names for the states, like st1_reset, st2_search
type state_type is (st1_<name_state>, st2_<name_state>, ...);
signal state, next_state : state_type;
--Declare internal signals for all outputs of the state machine
signal <output>_i : std_logic; -- example output signal
--other outputs
--Insert the following in the architecture after the begin keyword
SYNC_PROC: process (CLOCK, RESET)
begin
if (<reset>='1') then
state <= st1_<name_state>;
<output> <= '0';
-- assign other outputs to reset value
elsif (<clock>'event and <clock> = '1') then
state <= next_state;
<output> <= <output>_i;
-- assign other outputs to internal signals
end if;
end process;
--MEALY State Machine - Outputs based on state and inputs
OUTPUT_DECODE: process (state, <input1>, <input2>, ...)
begin
--insert statements to decode internal output signals
--below is simple example
if (state = st3_<name> and <input1> = '1') then
<output>_i <= '1';
else
<output>_i <= '0';
end if;
end process;
35. ___________________________________________________________________________VHDL Syntax
35 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
--insert statements to decode next_state
--below is a simple example
case (state) is
when st1_<name> =>
if <input_1> = '1' then
next_state <= st2_<name>;
end if;
when st2_<name> =>
if <input_2> = '1' then
next_state <= st3_<name>;
end if;
when st3_<name> =>
next_state <= st1_<name>;
when others =>
next_state <= st1_<name>;
end case;
end process;
Moore State Machine
-- This is a sample state machine using enumerated types.
-- This will allow the synthesis tool to select the appropriate
-- encoding style and will make the code more readable.
--Insert the following in the architecture before the begin keyword
--Use descriptive names for the states, like st1_reset, st2_search
type state_type is (st1_<name_state>, st2_<name_state>, ...);
signal state, next_state : state_type;
--Declare internal signals for all outputs of the state machine
signal <output>_i : std_logic; -- example output signal
--other outputs
--Insert the following in the architecture after the begin keyword
SYNC_PROC: process (CLOCK, RESET)
begin
if (<reset>='1') then
state <= st1_<name_state>;
<output> <= '0';
36. ___________________________________________________________________________VHDL Syntax
36 Prepared by : Mr. A. B. Shinde, P.V.P.I.T., Budhgaon
-- assign other outputs to reset value
elsif (<clock>'event and <clock> = '1') then
state <= next_state;
<output> <= <output>_i;
-- assign other outputs to internal signals
end if;
end process;
--MOORE State Machine - Outputs based on state only
OUTPUT_DECODE: process (state)
begin
--insert statements to decode internal output signals
--below is simple example
if state = st3_<name> then
<output>_i <= '1';
else
<output>_i <= '0';
end if;
end process;
NEXT_STATE_DECODE: process (state, <input1>, <input2>, ...)
begin
--declare default state for next_state to avoid latches
next_state <= state; --default is to stay in current state
--insert statements to decode next_state
--below is a simple example
case (state) is
when st1_<name> =>
if <input_1> = '1' then
next_state <= st2_<name>;
end if;
when st2_<name> =>
if <input_2> = '1' then
next_state <= st3_<name>;
end if;
when st3_<name> =>
next_state <= st1_<name>;
when others =>
next_state <= st1_<name>;
end case;
end process;