This document discusses system-on-chip (SoC) concepts, design principles, an example multimedia system, and the SoC design flow. It describes how SoCs integrate CPU, memory and custom hardware onto a single chip to improve efficiency. Key principles include distributed and heterogeneous processing, communications through multiple bus segments, and hierarchical control. An example portable multimedia SoC is presented with dedicated signal processing, general purpose processing and optimal parallelism control. The SoC design flow involves specification, design, validation and production.
System-on-Chip Design Principles and Portable Multimedia Example
1. CHAPTER 8:
SYSTEM-ON-CHIP
Chris Desomer
Lars Jacobs
|H05B9| Advanced Platform Architectures and Mapping
Methods for Embedded Applications: Lecture
prof. dr. Ir. IngridVerbauwhede
2. Topics for today
• SoC Concept
• Design Principles in SoC Architecture
• Example: Portable Multimedia System
• SoC Design Flow
October 4, 2013 2
http://blog.thoughtpick.com/wp-content/uploads/2011/01/web_design_services.11-18.web_content.jpg
3. SoC CONCEPT
SoC Concept
Design Principles in SoCArchitecture
Example: Portable Multimedia System
SoC Design Flow
October 4, 2013 3
5. Advantages
• Specialization of the Platform
• High Processing Efficiency
• Lower Power Consumption
• Flexibility of the Platform
• Lower Design Cost
October 4, 2013 5
6. Hardware Components
• CPU
• Central Controller
• Local Instruction Memory
October 4, 2013 6
• Communication Bus
• Address Map
• Divided into Segments
• Bus Bridge
7. Hardware Components
• Bus Master
• BusArbiter needed
when Multiple Masters
October 4, 2013 7
• Custom Hardware
• Standard Peripheral on System Bus
• Attached to CPU through Local Bus
• Inside CPU
9. Design Principles
• Heterogeneous and Distributed Data Processing
• Heterogeneous and Distributed Communications
• Heterogeneous and Distributed Storage
• Hierarchical Control
October 4, 2013 10
10. Data Processing
• Data Processing Parallelism
• Word-Level Parallelism
• Instruction-Level Parallelism
• Task-Level Parallelism
• Domain-Specific Computing
October 4, 2013 11
11. Communications
• Central bus = bottleneck?!
• Solution: Multiple Bus Segments
• Own Function and Speed
• Connected through Bus Bridges
• ≠ types of interconnection mechanisms
October 4, 2013 12
12. BusTopologies
• Linear
• Bus Bridges
• Bus Arbitration needed
• Hierarchy
• Static Assignment
• Non–linear
• Bus Switches
• Limited Scalability
• Network On Chip
October 4, 2013 13
13. Storage
• ≠Types of Memories
• Registers
• DRAM
• SRAM
• NVROM
• NVRAM
October 4, 2013 14
14. Control
• SoC
• Outside = Single Logical Entity
• Inside = Many Hardware Modules in Parallel
• Challenge to Minimize Conflicts
• Task of the Designer
October 4, 2013 15
17. Design Principles
• Processing
• Hardwired Processing
• Signal Processing
• General-purpose Processing
• Communication
• Switchbox
• Additional Dedicated Interconnects (e.g. Bus between ARM and
Instruction Memory)
• Storage
• Off-chip SDRAM
• Dedicated Instruction Memories attached to DSP andARM
• Control
• Optimal Parallelism controled by ARM
October 4, 2013 18
21. References
•Schaumont, P. (2012) A Practical Introduction to
Hardware/Software Codesign. Springer
•Wikipedia, “System on a chip.”,
http://en.wikipedia.org/wiki/System_on_a_chip
•Samsung, “Exynos 5 Dual.”,
http://www.samsung.com/global/business/semiconduct
or/product/application/detail?productId=7668
October 4, 2013 22