MOSFETs

Mr. A. B. Shinde
FET
2
 Field Effect Transistor (FET)
• The conductivity (or resistivity) of the path between two contacts, the
source and the drain, is altered by the voltage applied to the gate.
– Device is also known as a voltage controlled resistor.

Mr. A. B. Shinde
MOSFETs
3
 A metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-
FET, or MOS FET) is a field-effect transistor where the voltage
determines the conductivity of the device.
 The ability to change conductivity with the amount of applied voltage can
be used for amplifying or switching electronic signals.
 MOSFETs are now even more common than BJTs (bipolar junction
transistors) in digital and analog circuits.

Mr. A. B. Shinde
FET
4
n-channel
Enhancement Mode
(nMOSFET)
p-channel
Enhancement Mode
(pMOSFET)
n-channel
Depletion Mode
(nMOSFET)
p-channel
Depletion Mode
(pMOSFET)

Mr. A. B. Shinde
MOSFET : Structure
5
Typically L = 0.03 μm to 1 μm, W = 0.05
μm to 100 μm, and the thickness of the
oxide layer (tox) is in the range of 1 to
10 nm.
perspective view;
Cross section.

Mr. A. B. Shinde
MOSFET : Operation
6
 Operation with Zero Gate Voltage:
• With zero voltage applied to the gate, two back-to-back diodes exist in
series between drain and source.
• n+ drain region and the p-type substrate,
• p-type substrate and the n+ source region.
• These back-to-back diodes prevent current conduction from drain to
source when a voltage VDS is applied.
• The path between drain and source has a very high resistance (of the
order of 1012 Ω).

Mr. A. B. Shinde
MOSFET : Operation
7
 Channel for Current Flow:
• Source & Drain are grounded and
applied a positive voltage to the
gate (VGS).
• VGS repells the free holes from the
region of the substrate under the
gate (the channel region).
• These holes are pushed downward
into the substrate, leaving behind a
carrier-depletion region.
• Positive VGS attracts electrons from
the n+ source and drain regions
into the channel region
• When a sufficient number of electrons
accumulate near the surface of the
substrate under the gate, an n region is
in effect created, connecting the source
and drain regions,

Mr. A. B. Shinde
MOSFET : Operation
8
 Channel for Current Flow:
• If a voltage is applied between
drain and source, current flows
through this induced n region.
• The induced n region thus forms a
channel for current flow from
drain to source
• This is called an n-channel
MOSFET or an NMOS transistor.
• The channel is created by inverting
the substrate surface from p type
to n type. Hence the induced
channel is also called an inversion
layer. Note: An n-channel MOSFET is formed in a p-type
substrate
The excess of VGS over Vt is termed the
effective voltage or the overdrive
voltage and is the quantity that
determines the charge in the channel.
Here, VGS −Vt ≡ VOV

Mr. A. B. Shinde
MOSFET
9
• Gate and Channel region of the MOSFET form a parallel-plate
capacitor, with the oxide layer acting as the capacitor dielectric.
• Positive gate voltage causes positive charge to accumulate on the top
plate of the capacitor (the gate electrode).
• Negative charge on the bottom plate is formed by the electrons in the
induced channel.
• This field controls the amount of charge in the channel hence it
determines the channel conductivity when a voltage VDS is applied.
• This is the origin of the name “field-effect transistor” (FET).

Mr. A. B. Shinde
MOSFET : Operation
10
Applying a Small VDS:
• The voltage VDS causes a
current iD to flow through the
induced n channel.
• Current is carried by free
electrons traveling from source
to drain
• An NMOS transistor with VGS >
Vt and with a small VDS applied.
The device acts as a resistance
whose value is determined by
VGS.
• Specifically, the channel
conductance is proportional to
VGS – Vt , and thus iD is
proportional to (VGS – Vt)VDS. depletion region is not
shown for simplicity.

Mr. A. B. Shinde
MOSFET : Operation
11
• Applying a Small VDS:
• The iD – VDS characteristics of
the MOSFET when the voltage
applied between drain and
source, vDS, is kept small.
• The device operates as a
linear resistance whose value
is controlled by VGS.

Mr. A. B. Shinde
MOSFET : Operation
12
Operation of the enhancement NMOS
transistor as VDS is increased. The induced
channel acquires a tapered shape, and its
resistance increases as vDS is increased.
Here, vGS is kept constant at a value > Vt ;
VGS = Vt +VOV .
The drain current iD Vs VDS for an
enhancement-type NMOS transistor
operated with
VGS = Vt +VOV .

Mr. A. B. Shinde
MOSFET : p-Channel
13
Physical structure of
the PMOS transistor

Mr. A. B. Shinde
FET
14
Circuit symbol
for the n-channel
enhancement-
type MOSFET
Modified symbol
n channel.
Simplified circuit
symbol

Mr. A. B. Shinde
MOSFET: ID-VDS Characteristics
15

Mr. A. B. Shinde
MOSFET: ID-VDS Characteristics
16
The iD −vDS characteristics
for an enhancement-type
NMOS transistor

Mr. A. B. Shinde
Biasing in MOS Amplifier Circuits
18
• An essential step in the design of a MOSFET amplifier circuit is the
establishment of an appropriate dc operating point for the transistor.
• This step is also known as biasing or bias design.
• An appropriate dc operating point or bias point is characterized by a
stable and predictable dc drain current ID and by a dc drain-to-source
voltage VDS that ensures operation in the saturation region for all
expected input-signal levels.
• Types of Biasing:
– Biasing by Fixing VGS
– Biasing by Fixing VG and Connecting a Resistance in the Source
– Biasing Using a Drain-to-Gate Feedback Resistor
– Biasing Using a Constant-Current Source

Mr. A. B. Shinde
19
 Biasing by Fixing VGS:
• The most common approach to biasing a MOSFET is to fix its gate-to-
source voltage VGS to the value required to provide the desired ID.
• This voltage is derived from the power supply voltage VDD through the
use of an appropriate voltage divider.
• Independent of how the voltage VGS may be generated, this is not a
good approach to biasing a MOSFET.
Because we know that,
And the threshold voltage VO the oxide-capacitance COX, and transistor
aspect ratio W/L vary widely among devices of same size and type.

Mr. A. B. Shinde
20
• Biasing by Fixing VGS:
• Biasing by fixing VGS is not a
good technique.
• Figure two iD-vGS characteristic
curves representing extreme
values in a batch of MOSFETs
of the same type.
• For the fixed value of VGS, the
resultant spread in the values
of the drain current can be
substantial.

Mr. A. B. Shinde
21
• An excellent biasing technique for discrete
MOSFET circuits consists of fixing the dc voltage
at the gate, VG, and connecting a resistance in the
source lead, as shown in figure.
We can write,
VG = VGS + RSID
 Biasing by Fixing VG and Connecting a
Resistance in the Source:

Mr. A. B. Shinde
22
• If VG >> VGS, ID will be determined by the values
of VG and RS.
• If VG > VGS, resistor Rs provides negative
feedback, which will stabilize the value of the bias
current ID.
• From equation, when ID increases & VG is
constant, VGS will decrease. Which will further
decrease ID.
• Thus the Rs works to keep ID as constant as
possible.
• This negative feedback action of Rs gives it the
name degeneration resistance.
VG = VGS + RSID

Mr. A. B. Shinde
23
• Figure shows the iD – vGS characteristics
for two devices that represent the
extremes of a batch of MOSFETs.
• A straight line that represents the
constraint imposed by the bias circuit—
namely.
• The intersection of this straight line with
the iD –vGS characteristic curve provides
the coordinates (ID and VGS) of the bias
point.
• In this case, the variability obtained in ID
is much smaller. Also, note that the
variability decreases as VG and Rs are
made larger.
Biasing by Fixing VG and Connecting a Resistance in the Source:

Mr. A. B. Shinde
24
 Practical implementation using a single
supply:
• The circuit utilizes one power-supply VDD and
derives VG through a voltage divider (RG1, RG2).
• Since IG = 0, RG1 and RG2 can b e selected to b e
very large (in the M Ω range), allowing the
MOSFET to present a large input resistance to a
signal source

Mr. A. B. Shinde
25
 Biasing Using a Drain-to-Gate Feedback
Resistor:
• A simple and effective biasing arrangement utilizing
a feedback resistor connected between the drain
and the gate is shown in figure.
• Here the large feedback resistance RG (usually in
the M Ω range) forces the dc voltage at the gate to
be equal to that at the drain (because IG = 0).
Thus we can write
VGS = VDS = VDD – RDID
Which can be rewritten in the form
VDD = VGS + RDID

Mr. A. B. Shinde
26
• Biasing Using a Drain-to-Gate Feedback
Resistor:
• If ID increases due to any reason, then VGS must
decrease.
• The decrease in VGS in turn causes a decrease in
ID.
• Thus the negative feedback or degeneration
provided by RG works to keep the value of ID as
constant as possible.
VDD = VGS + RDID
VGS = VDS = VDD – RDID

Mr. A. B. Shinde
27
 Biasing Using a Constant-Current Source:
• The most effective scheme for biasing a MOSFET
amplifier is that using a constant-current source, as
shown in figure.
• Here RG (usually in M Ω range) establishes a dc
ground at the gate and presents a large resistance
to an input signal source that can be capacitively
coupled to the gate.
• Resistor RD establishes an appropriate dc voltage
at the drain to allow for the required output signal
swing while ensuring that the transistor always
remains in the saturation region.

Mr. A. B. Shinde
Small-Signal Operation and Models
29
• Consider the conceptual amplifier circuit
shown in figure.
• Here the MOS transistor is biased by
applying a dc voltage VGS, and the input
signal to be amplified, vgs, is superimposed
on the dc bias voltage VGS.
• The output voltage is taken at the drain.
Conceptual circuit to
study the operation
of the MOSFET as a
small-signal amplifier

Mr. A. B. Shinde
30
• DC Bias Point:
• The dc bias current ID can be found by setting the
signal vgs to zero;
Thus,
Here, It is assumed that λ = 0
Here, VOV = VGS −Vt is the overdrive voltage at
which the MOSFET is biased to operate.
The dc voltage at the drain, VDS, will be
VDS = VDD −RDID

Mr. A. B. Shinde
31
• DC Bias Point:
• To ensure saturation-region operation, we
must have
VDS > VOV
• Furthermore, since the total voltage at the
drain will have a signal component
superimposed on VDS, VDS has to be
sufficiently greater than VOV to allow for the
required negative signal swing.

Mr. A. B. Shinde
32
 Signal Current in the Drain Terminal:
• Consider the situation with the input signal vgs
applied.
• The total instantaneous gate-to-source voltage
will be
vGS = VGS + vgs
 resulting in a total instantaneous drain current
iD,
dc bias current ID
current component that is directly proportional to the input signal vgs
represents nonlinear distortion.

Mr. A. B. Shinde
33
• Signal Current in the Drain Terminal:
• To reduce the nonlinear distortion introduced by the MOSFET, the input
signal should be kept small so that
resulting in
or, equivalently,
If this small-signal condition is satisfied, then iD can be expressed as
iD ≈ ID +id
where
id = kn(VGS −Vt)vgs

Mr. A. B. Shinde
34
 The parameter that relates id and vgs is the MOSFET transconductance
gm,
or in terms of the overdrive voltage VOV ,
gm = kn VOV

Mr. A. B. Shinde
35
• Figure shows a
graphical interpretation
of the small-signal
operation of the
MOSFET amplifier.
• Note that gm is equal to
the slope of the iD–vGS
characteristic at the bias
point,
Small-signal operation
of the MOSFET amplifier

Mr. A. B. Shinde
36
 Voltage Gain:
• Total instantaneous drain voltage vDS as follows:
vDS = VDD −RDiD
• Under the small-signal condition, we have
vDS = VDD −RD(ID +id)
• which can be rewritten as
vDS = VDS −Rdid
• Thus the signal component of the drain voltage is
Vds =−idRD =−gmvgsRD
which indicates that the voltage gain is given by
The minus sign indicates that the output signal vds is 180° out of phase with respect
to the input signal vgs.
study operation of the
MOSFET

Mr. A. B. Shinde
37
 Voltage Gain:
• The input signal is assumed to have a triangular
waveform with an amplitude much smaller than
2(VGS – Vt), the small-signal condition to ensure
linear operation.
• For operation in the saturation (active) region at
all times, the minimum value of vDS should not
fall below the corresponding value of vGS by
more than Vt.
• The maximum value of vDS should be smaller
than VDD; otherwise the FET will enter the cutoff
region and the peaks of the output signal
waveform will be clipped off.
study operation of
the MOSFET

Mr. A. B. Shinde
38
 Voltage Gain:
Conceptual circuit to study
operation of the MOSFET Total instantaneous voltages vGS and vDS

Mr. A. B. Shinde
39
 Small-Signal Equivalent-Circuit Models:
• The FET behaves as a voltage-controlled current source.
• It accepts a signal vgs between gate and source and provides a current
gm.vgs at the drain terminal.
• The input resistance of this controlled source is very high — ideally,
infinite.
• The output resistance — is also high.

Mr. A. B. Shinde
40
Small-signal models for the MOSFET:
Neglecting the dependence of iD
on vDS in the active region
including the effect of channel-length
modulation, modeled by output
resistance

Mr. A. B. Shinde
41
• In the analysis of a MOSFET amplifier circuit,
the transistor can be replaced by the
equivalent-circuit model shown in Figure.
• The rest of the circuit remains unchanged
except that ideal constant dc voltage sources
are replaced by short circuits.
• Most serious shortcoming of this model is that
it assumes the drain current in saturation to
be independent of the drain voltage, but
actually drain current depends on vDS in a
linear manner.
• Such dependence was modeled by a finite
resistance ro between drain and source,
Neglecting the
dependence of iD on vDS in
the active region
including the effect of channel-
length modulation,

Mr. A. B. Shinde
42

Mr. A. B. Shinde
MOSFET as Amplifier
44
• In the saturation region, the MOSFET acts as a voltage-controlled
current source: Changes in the gate-to-source voltage vGS gives rise to
changes in the drain current iD.
• Thus the saturated MOSFET can be used to implement a
transconductance amplifier

Mr. A. B. Shinde
MOSFET as Amplifier
45
 Large-Signal Operation:
 The Transfer Characteristic:
• Grounded source terminal is common to
both the input and output.
• Here, changes in v1 (vGS = v1) give rise to
changes in iD, we are using a resistor RD to
obtain an output voltage v0
v0 = vDS = VDD – RD.iD
In this way the transconductance amplifier
is converted into a voltage amplifier.
• To determine the voltage transfer
characteristic of the CS amplifier, we will
assume vj to be in the range of 0 to VDD.
Basic structure of
common-source amplifier

Mr. A. B. Shinde
MOSFET as Amplifier
46
 Large-Signal Operation-The Transfer Characteristic:
Basic structure of
Transfer characteristic of the amplifier

Mr. A. B. Shinde
MOSFET as Amplifier
47
vDS = VDD – RD.iD
• Straight line on iD-vDS characteristics
curves shows the iD - vDS relationship.
• Since vGS = v1 , for v1 < Vt the transistor
will be cut off, iD will be zero, and v0 =
vDS = VDD (point A).
• As Vi exceeds Vt the transistor turns on,
iD increases, and v0 decreases.
• This corresponds to points along the
segment of the load line from A to B.
• We have identified a particular point in
this region of operation and labeled it
Q. It is obtained for VGS = VIQ and has
the coordinates V0Q = VDSQ and IDQ.
Transfer characteristic
of the amplifier

Mr. A. B. Shinde
MOSFET as Amplifier
48
• Saturation-region operation continues
until v0 decreases below Vt.
• At this point, vDS = vGS - VD and the
MOSFET enters its triode region.
• This is refers to point B in graph.
Point B is defined by v0B = v1B – Vt.
• For Vi > VIB, the transistor is driven
deeper into the triode region.
• The characteristic curves in the triode
region are bunched together, the output
voltage decreases slowly towards zero.
• Here we have identified a particular
operating point C obtained for v1 = VDD.
• The corresponding output voltage VOC will
usually be very small. Transfer characteristic
of the amplifier

Mr. A. B. Shinde
MOSFET as Amplifier
49
 Large-Signal Operation-The Transfer Characteristic:
Basic structure of
Transfer Characteristics

Mr. A. B. Shinde
MOSFET as Amplifier
50
 Point C obtained for vi = VDD.
 The corresponding output voltage
VOC will usually be very small.
 This point-by-point determination of
the transfer characteristic results in
the transfer curve shown in figure.
 Observe that we have delineated
its three distinct segments, each
corresponding to one of the three
regions of operation of MOSFET
Q1.
Transfer Characteristics

Mr. A. B. Shinde
MOSFET as Amplifier
51
 MOSFET as a Switch:
• When the MOSFET is used as a switch, it is operated at the extreme
points of the transfer curve.
• The device is turned off by keeping, v < Vt. Here, v0 = VDD.
• The switch is turned on by applying a voltage close to VDD. Here, v0 is
very small.
• The common-source MOS circuit can be used as a logic inverter with
the "low" voltage level close to 0 V and the "high" level close to VDD.

Mr. A. B. Shinde
MOSFET as Amplifier
52
 Operation as a Linear Amplifier
• To operate the MOSFET as an amplifier, saturation-mode is maintained.
• The device is biased at a somewhere near to the middle of the transfer
curve. The voltage signal to be amplified vt is then superimposed on the
dc voltage VIQ.
• By keeping vt sufficiently small to restrict operation to an almost linear
segment of the transfer curve, the resulting output voltage signal v0 will
be proportional to vt.
• That is, the amplifier will be very nearly linear, and vQ will have the same
waveform as vt except that it will be larger by a factor equal to the
voltage gain of the amplifier at Q.

Mr. A. B. Shinde
MOSFET as Amplifier
53
 Operation as a Linear Amplifier
 Thus the voltage gain is equal to the slope of the transfer curve at the
bias point Q.
 The slope is negative, hence the basic CS amplifier is inverting.
 If the amplitude of the input signal v, the output signal will become
distorted since operation will no longer be restricted to an almost linear
segment of the transfer Curve.

Mr. A. B. Shinde
MOSFET as Amplifier
54
 Analytical Expressions for the
Transfer Characteristic:
• From the i-v relationships we can see
that, the MOSFET operates in three
regions — cutoff, saturation, and
triode.
• Cutoff – Region Segment, XA:
Here, vi < Vt, and v0 = VDD.
• Saturation – Region Segment, AQB:
Here, vi, ≥ Vt and
v0 ≥ vi - Vt
• Triode-Region Segment, BC:
Here, vi ≥ Vt and v0 ≤ vi – Vt Transfer characteristic
of the amplifier

Mr. A. B. Shinde
Single Stage MOS Amplifier
56
• The Basic Structure:
• Figure shows the basic circuit to implement
the various configurations of discrete-circuit
MOS amplifiers.
• Due to effectiveness and simplicity constant-
current biasing technique is used for biasing
the MOS transistor.
• Figure indicates the dc current and the dc
voltages resulting at various nodes.

Mr. A. B. Shinde
57
 Characterizing Amplifiers:
1. The amplifier is with a signal source having an open-circuit voltage vsig
and an internal resistance Rsig. These are the parameters of an actual
signal source. Similarly, RL is an load resistance.
2. Parameters Ri, R0, Avs, Ais, and Gm pertain to the amplifier proper; that is,
they do not depend on the values of Rsig and RL. By contrast, Rin, Rout,
Av, Ai, Gv0, and Gv may depend on one or both of Rsig and RL.
3. As mentioned above, for nonunilateral amplifiers, Rin may depend on RL,
and Rout may depend on Rsig. No such dependencies exist for unilateral
amplifiers, for which Rin = Ri and Rout = R0.
4. The loading of the amplifier on the signal source is determined by the
input resistance Rin. The value of Rin determines the current that the
amplifier draws from the signal source. It also determines the proportion
of the signal vsig that appears at the input of the amplifier.

Mr. A. B. Shinde
58
• Characterizing Amplifiers:
• Figure shows an amplifier fed with a signal source having an open-
circuit voltage vsig and an internal resistance Rsig.
• These can be the parameters of an actual signal source,
• The amplifier is shown with a load resistance RL connected to the output
terminal.
• Here, RL can be an actual load resistance or the input resistance of a
succeeding amplifier stage in a cascade amplifier.

Mr. A. B. Shinde
59
• Figure shows the amplifier circuit with the amplifier block replaced by its
equivalent-circuit model.
• The input resistance Rin represents the loading effect of the amplifier
input on the signal source.
Rin and Rsig forms a voltage divider that reduces vsig to the value vi

Mr. A. B. Shinde
60
• The second parameter in characterizing amplifier performance is the
open-circuit voltage gain Avo, defined as
The last parameter is the output resistance Ro. From figure, Ro is the
resistance seen looking back into the amplifier output terminal with vi set
to zero.
As Ro is determined with vi = 0, the value of Ro does not depend on Rsig.

Mr. A. B. Shinde
61
Output voltage vo
Voltage gain of the amplifier, Av
Overall voltage gain, Gv

Mr. A. B. Shinde
62

Mr. A. B. Shinde
63
 CS Amplifier:
• Figure shows a common-source (CS) amplifier fed with a signal source
vsig having a source resistance Rsig.
• Analyze this circuit to determine Rin, Avo , and Ro. Here, assume RD is
part of the amplifier; thus if a load resistance RL is connected to the
amplifier output, RL appears in parallel with RD. In such a case, we wish
to determine Av and Gv as well.
• Replacing the MOSFET with its hybrid-π model (without ro), we obtain
the CS amplifier equivalent circuit as shown in second figure.

Mr. A. B. Shinde
64
 CS Amplifier:

Mr. A. B. Shinde
MOSFET Internal Capacitances
66
• Various internal
capacitances, are shown
for n-channel MOSFET
operating in the
saturation region.
• There are four internal
capacitances:
• Cgs and Cgd, result from
the gate-capacitance
effect;
• Csb and Cdb, are the
depletion capacitances of
the pn junctions formed
by the source region and
the substrate, and the
drain region and the
substrate, respectively.

Mr. A. B. Shinde
67
• The polysilicon gate forms a parallel-plate capacitor with the channel
region, where oxide layer works as dielectric.
• The gate (or oxide) capacitance per unit gate area is denoted Cox. When
the channel is tapered and pinched off, the gate capacitance is given by
2/3 WLCox.
• There are two other small capacitances resulting from the overlap of the
gate with the source region (or source diffusion) and the drain region (or
drain diffusion).
• Each of these overlaps has a length Lov and thus the resulting overlap
capacitances Cov are given by
Typically, Lov = 0.05 to 0.1L.
We can now express the gate-to-source capacitance Cgs as

Mr. A. B. Shinde
68
• For the gate-to-drain capacitance, we note that the channel pinch-off at
the drain end causes Cgd to consist entirely of the overlap component
Cov ,
The depletion-layer capacitances of the two reverse-biased pn junctions
formed between each of the source and the drain diffusions and the p-
type substrate.
Thus, for the source diffusion, we have the source-body capacitance,
Csb,
where Csb0 is the value of Csb at zero body-source bias, VSB is the
magnitude of the reverse-bias voltage, and V0 is the junction built-in
voltage (0.6 V to 0.8 V).

Mr. A. B. Shinde
69
• Similarly, for the drain diffusion, we have the drain-body capacitance
Cdb,
where Cdb0 is the capacitance value at zero reverse-bias voltage and
VDB is the magnitude of this reverse-bias voltage. Note that we have
assumed that for both junctions, the grading coefficient m = 1/2 .
Problem: For an n-channel MOSFET with tox = 10 nm, L = 1.0 μm,
W = 10 μm, Lov = 0.05 μm, Csb0 = Cdb0 = 10 fF, V0 = 0.6 V, VSB = 1 V and
VDS = 2 V. Calculate the following capacitances when the transistor is
operating in saturation: Cox, Cov , Cgs, Cgd , Csb, and Cdb.
Ans: Cox = 3.45 fF/μm2; Cov = 1.72 fF; Cgs = 24.7 fF;
Cgd = 1.72 fF; Csb = 6.1 fF; Cdb = 4.1 fF

Mr. A. B. Shinde
MOSFET High Frequency Model
71
• Figure shows the small-signal model of the MOSFET, including the four
capacitances Cgs, Cgd , Csb, and Cdb.
• This model is used to predict the high-frequency response of MOSFET
amplifiers.
High-frequency, equivalent-circuit model for the MOSFET

Mr. A. B. Shinde
72
• When the source is connected to the body, the model simplifies
considerably, as shown in figure.
• In this model, Cgd, although small, plays a significant role in determining
the high-frequency response of amplifiers and thus must be kept in the
model.
The equivalent circuit for source is connected to the substrate

Mr. A. B. Shinde
73
• Capacitance Cdb, can usually be neglected, resulting in significant
simplification of manual analysis.
• The resulting circuit is shown in figure.
The equivalent-circuit model with Cdb neglected

Mr. A. B. Shinde
74
• Figure shows the high-frequency T model in its simplified form.
The simplified high-frequency T model

Mr. A. B. Shinde
75
 MOSFET High-Frequency Model: Summary

Mr. A. B. Shinde
76
• Problem: Calculate fT for the n-channel MOSFET whose capacitances
were found in Exercise 10.3. Assume operation at 100 μA and that
kn = 160 μA/V2.
• Ans. 3.4 GHz

Frequency Response of
CS Amplifier

Mr. A. B. Shinde
Frequency Response of CS Amplifier
78
Magnitude of the gain of a discrete-circuit MOS amplifier
versus frequency

Mr. A. B. Shinde
79
• Figure shows, at lower frequencies, the magnitude of the amplifier gain
falls off due to coupling and bypass capacitors. Here, it is assumed that
their impedances were small enough to act as short circuits.
• At midband frequencies, as the frequency of the input signal is lowered,
the reactance 1/jωC of each of these capacitors becomes significant,
this results in a decrease in the overall voltage gain of the amplifier.
• Lower and upper cut-off frequency fL & fH, are the frequencies at which
the gain drops by 3 dB below its value in midband.
• BW = fH −fL (discrete-circuit amplifiers)
• BW = fH (integrated-circuit amplifiers)

Mr. A. B. Shinde
CMOS Inverter
81
 The CMOS inverter is constructed by using
nMOS & pMOS transistors.
 As the pMOS transistor passes strong 1 and
weak 0, it is connected to the supply voltage
VDD and
 nMOS transistor passes strong 0 and weak
1, it is connected to the ground.
CMOS inverter

Mr. A. B. Shinde
CMOS Inverter
82
 Circuit Operation:
• Consider the two extreme cases:
• When vi is at logic-0 level, which is 0 V, and
when vi is at logic-1 level, which is VDD volts.
• In both cases, for ease of exposition we
shall consider the n-channel device QN to be
the driving transistor and the p-channel
device QP to be the load.
• As circuit is symmetric, this assumption is
arbitrary, and the reverse would lead to
identical results.

Mr. A. B. Shinde
CMOS Inverter
83
Circuit with vi = VDD
equivalent circuit

Mr. A. B. Shinde
CMOS Inverter
84
Circuit with vi = 0 V
equivalent circuit

Mr. A. B. Shinde
CMOS Inverter
85
 Voltage-
Transfer
Characteristic:

Mr. A. B. Shinde
Reference
86
• Microelectronic Circuits by Adel S. Sedra & Kenneth C. Smith, 7e

This presentation is published only for educational purpose
87
Thank You…!!!
abshinde.eln@gmail.com

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