This document is a lab manual for a digital system design course. It contains documentation and code for various digital logic components including half adders, full adders, 4-bit and 16-bit magnitude comparators, up/down counters, decoders, and other basic building blocks. For each component, it provides entity diagrams, architecture diagrams, device utilization summaries from synthesis, and simulation waveforms. The manual was prepared by an instructor to provide materials and guidance for students in learning digital logic design.

1. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Padmabhooshan Vasantraodada Patil Institute of Technology,
Budhgaon-416304
Digital System Design
LAB MANUAL
Prepared by
Mr. A. B. Shinde
Assistant Professor,
Electronics Engineering,

Department of Electronics Engineering
2013-14

2. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
------Half Adder (Behavioral)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ha_adder is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end ha_adder;
architecture Behavioral of ha_adder is
begin
s<= a xor b;
c<= a and b;
end Behavioral
Entity Level Diagram
Architectural Level Diagram

3. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
XOR Gate
Device utilization Summary:
---------------------------
Number of Slices: 1 out of 1200 0%
Number of 4 input LUTs: 2 out of 2400 0%
Number of bonded IOBs: 4 out of 96 4%
Simulation Waveform

4. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Full Adder (Structural)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity f_adder is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic);
end f_adder;
architecture structural of f_adder is
signal s1, c1, c2: std_logic;
component ha_adder is
Port ( a : in std_logic;
b : in std_logic;
s : out std_logic;
c : out std_logic);
end component;
begin
u1: ha_adder port map(a, b, s1, c1);
u2: ha_adder port map(s1, cin, sum, c2);
carry<= c1 or c2;
end structural;
Entity Level Diagram

5. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 1 out of 1200 0%
Number of 4 input LUTs: 2 out of 2400 0%
Number of bonded IOBs: 5 out of 96 5%
Simulation Waveform

6. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------4 bit Full Adder (Structural)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
Sum : out std_logic_vector(3 downto 0);
Cy : out std_logic);
end adder_4bit;
architecture Behavioral of adder_4bit is
component f_adder is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
carry : out std_logic);
end component;
signal c1, c2, c3:std_logic;
begin
u1:f_adder port map(a=>a(0),
b=>b(0),
cin=>cin,
sum=>Sum(0),
carry=>c1);
u2:f_adder port map(a=>a(1),
b=>b(1),
cin=>c1,
sum=>Sum(1),
carry=>c2);
u3:f_adder port map(a=>a(2),
b=>b(2),
cin=>c2,
sum=>Sum(2),
carry=>c3);
u4:f_adder port map(a=>a(3),
b=>b(3),
cin=>c3,
sum=>Sum(3),
carry=>Cy);
end Behavioral;

7. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 5 out of 1200 0%
Number of 4 input LUTs: 9 out of 2400 0%
Number of bonded IOBs: 14 out of 96 14%
Simulation Waveform

8. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------16 bit Full Adder (Structural)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_16bit is
Port ( x : in std_logic_vector(15 downto 0);
y : in std_logic_vector(15 downto 0);
pre_carry : in std_logic;
Sum : out std_logic_vector(15 downto 0);
Carry : out std_logic);
end adder_16bit;
architecture Behavioral of adder_16bit is
component adder_4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
Sum : out std_logic_vector(3 downto 0);
Cy : out std_logic);
end component;
signal c1,c2,c3:std_logic;
begin
u1:adder_4bit port map(a=>x(3 downto 0),
b=>y(3 downto 0),
cin=>pre_carry,
Sum=>Sum(3 downto 0),
Cy=>c1);
u2:adder_4bit port map(a=>x(7 downto 4),
b=>y(7 downto 4),
cin=>c1,
Sum=>Sum(7 downto 4),
Cy=>c2);
u3:adder_4bit port map(a=>x(11 downto 8),
b=>y(11 downto 8),
cin=>c2,
Sum=>Sum(11 downto 8),
Cy=>c3);
u4:adder_4bit port map(a=>x(15 downto 12),
b=>y(15 downto 12),
cin=>c3,
Sum=>Sum(15 downto 12),
Cy=>Carry);
end Behavioral;

9. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 19 out of 1200 1%
Number of 4 input LUTs: 33 out of 2400 1%
Number of bonded IOBs: 50 out of 96 52%
Simulation Waveform

10. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------4bit Magnitude Comparator (Structural)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comp_4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
altb : out std_logic;
aeqb : out std_logic;
agtb : out std_logic);
end comp_4bit;
architecture comp_arch of comp_4bit is
component adder_4bit is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
Sum : out std_logic_vector(3 downto 0);
Cy : out std_logic);
end component;
component xnor_4 is
port (s: in std_logic_vector(3 downto 0);
t: in std_logic_vector(3 downto 0);
v: out std_logic_vector(3 downto 0));
end component;
component and_4 is
port ( p,q,r,s:in std_logic;
y:out std_logic);
end component;
component not_4 is
port ( i:in std_logic_vector(3 downto 0);
j:out std_logic_vector(3 downto 0));
end component;
signal s1,s2,s3,s5,s6:std_logic_vector(3 downto 0);
signal s4:std_logic:='0';
begin
u1: adder_4bit port map ( a=>s1,
b=>b,
cin=>s4,
Sum=>s5,
Cy=>altb);
u2: adder_4bit port map ( a=>s2,
b=>a,
cin=>s4,
Sum=>s6,
Cy=>agtb);
u3: xnor_4 port map ( s=>a,
t=>b,
v=>s3);

11. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
u4: and_4 port map ( p=>s3(3),
q=>s3(2),
r=>s3(1),
s=>s3(0),
y=>aeqb);
u5: not_4 port map ( i=>a,
j=>s1);
u6: not_4 port map ( i=>b,
j=>s2);
end comp_arch;
Entity Level Diagram
Architectural Level Diagram

12. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Device utilization summary:
---------------------------
Number of Slices: 5 out of 1200 0%
Number of 4 input LUTs: 9 out of 2400 0%
Number of bonded IOBs: 11 out of 96 11%
Simulation Waveform

13. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------BCD up-down Counter------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity coun_bcd_updn is
Port ( clk : in std_logic;
reset : in std_logic;
updn : in std_logic;
count : out std_logic_vector(3 downto 0));
end coun_bcd_updn;
architecture Behavioral of coun_bcd_updn is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if(reset='1')then
temp<="0000";
elsif(clk'event and clk='1')then
if (updn='1')then
if(temp=x"9")then
temp<=x"0";
else
temp<=temp+1;
end if;
else
if(temp=x"0")then
temp<=x"9";
else
temp<=temp-1;
end if;
end if;
end if;
end process;
count<=temp;
end Behavioral;
Entity Level Diagram

14. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 6 out of 1200 0%
Number of Slice Flip Flops: 4 out of 2400 0%
Number of 4 input LUTs: 11 out of 2400 0%
Number of bonded IOBs: 7 out of 96 7%
Number of GCLKs: 1 out of 4 25%
Simulation Waveform

15. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------4bit Binary up-down Counter------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_updn is
Port ( clk : in std_logic;
reset : in std_logic;
updn: in std_logic;
count : out std_logic_vector(3 downto 0));
end counter_updn;
architecture Behavioral of counter_updn is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk,reset)
begin
if(reset='1')then
temp<="0000";
elsif(clk'event and clk='1')then
if (updn='1')then
temp<=temp+1;
else
temp<=temp-1;
end if;
end if;
end process;
count<=temp;
end Behavioral;
Entity Level Diagram

16. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 2 out of 1200 0%
Number of Slice Flip Flops: 4 out of 2400 0%
Number of 4 input LUTs: 4 out of 2400 0%
Number of bonded IOBs: 7 out of 96 7%
Number of GCLKs: 1 out of 4 25%

17. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Simulation Waveform

18. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------3:8 Decoder------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity deco_3_8 is
Port ( input : in std_logic_vector(2 downto 0);
en : in std_logic;
output : out std_logic_vector(7 downto 0));
end deco_3_8;
architecture Behavioral of deco_3_8 is
begin
process(input,en)
begin
if (en='0') then
output<=(others=>'0');
else
case input is
when "000" => output<="00000001";
when "001" => output<="00000010";
when "010" => output<="00000100";
when "011" => output<="00001000";
when "100" => output<="00010000";
when "101" => output<="00100000";
when "110" => output<="01000000";
when others => output<="10000000";
end case;
end if;
end process;
end Behavioral;
Entity Level Diagram

19. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 4 out of 192 2%
Number of 4 input LUTs: 8 out of 384 2%
Number of bonded IOBs: 12 out of 90 13%
Simulation Waveform

20. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------5:32 Decoder (Structural)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity deco_5_32 is
Port ( i : in std_logic_vector(4 downto 0);
En : in std_logic;
y : out std_logic_vector(31 downto 0));
end deco_5_32;
architecture dec_arch of deco_5_32 is
component deco_2_4 is
Port ( i : in std_logic_vector(1 downto 0);
e : in std_logic;
y : out std_logic_vector(3 downto 0));
end component;
component deco_3_8 is
Port ( input : in std_logic_vector(2 downto 0);
en : in std_logic;
output : out std_logic_vector(7 downto 0));
end component;
signal s : std_logic_vector(3 downto 0);
begin
u1: deco_2_4 port map (i=>i(4 downto 3),
e=>En,
y=>s);
u2: deco_3_8 port map (input=>i(2 downto 0),
en=>s(3),
output=>y(31 downto 24));
u3: deco_3_8 port map (input=>i(2 downto 0),
en=>s(2),
output=>y(23 downto 16));
u4: deco_3_8 port map (input=>i(2 downto 0),
en=>s(1),
output=>y(15 downto 8));
u5: deco_3_8 port map (input=>i(2 downto 0),
en=>s(0),
output=>y(7 downto 0));
end dec_arch;

21. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 21 out of 192 10%
Number of 4 input LUTs: 36 out of 384 9%
Number of bonded IOBs: 38 out of 90 42%

22. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Simulation Waveform

23. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Encoder (When____Else)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity enco_8_3_when is
Port ( i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end enco_8_3_when;
architecture Behavioral of enco_8_3_when is
begin
y<="000" when i="00000001" else
"001" when i="00000010" else
"010" when i="00000100" else
"011" when i="00001000" else
"100" when i="00010000" else
"101" when i="00100000" else
"110" when i="01000000" else
"111" when i="10000000" else
"ZZZ";
end Behavioral;
-------Encoder (With____Select)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity enco_8_3_with is
Port ( i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end enco_8_3_with;
architecture Behavioral of enco_8_3_with is
begin
with i select
y<= "000" when "00000001",
"001" when "00000010",
"010" when "00000100",
"011" when "00001000",
"100" when "00010000",
"101" when "00100000",
"110" when "01000000",
"111" when "10000000",
"ZZZ" when others;
end Behavioral;

24. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 8 out of 192 4%
Number of 4 input LUTs: 16 out of 384 4%
Number of bonded IOBs: 11 out of 90 12%

25. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Simulation Waveform

26. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Priority Encoder------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity prio_enco is
Port ( i : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end prio_enco;
architecture Behavioral of prio_enco is
begin
process(i)
begin
if (i(7)='1')then
y<="111";
elsif (i(6)='1')then
y<="110";
elsif (i(5)='1')then
y<="101";
elsif (i(4)='1')then
y<="100";
elsif (i(3)='1')then
y<="011";
elsif (i(2)='1')then
y<="010";
elsif (i(1)='1')then
y<="001";
elsif (i(0)='1')then
y<="000";
else
y<="ZZZ";
end if;
end process;
end Behavioral;
Entity Level Diagram

27. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 4 out of 192 2%
Number of 4 input LUTs: 8 out of 384 2%
Number of bonded IOBs: 11 out of 90 12%
Simulation Waveform

28. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Single Port RAM------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram_1p is
Port ( clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(4 downto 0);
dio : inout std_logic_vector(3 downto 0));
end ram_1p;
architecture Behavioral of ram_1p is
type ram_type is array (31 downto 0) of std_logic_vector(3
downto 0);
signal ram: ram_type;
begin
process (clk)
begin
if (clk'event and clk='1')then
if (we='1')then
ram(conv_integer(addr))<=dio;
else
dio<=ram(conv_integer(addr));
end if;
end if;
end process;
end Behavioral;
Entity Level Diagram

29. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 8 out of 192 4%
Number of Slice Flip Flops: 4 out of 384 1%
Number of 4 input LUTs: 8 out of 384 2%
Number of bonded IOBs: 11 out of 90 12%
Number of GCLKs: 1 out of 4 25%
Simulation Waveform

30. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Dual Port RAM------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram_2p is
Port ( clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector(4 downto 0);
din : in std_logic_vector(3 downto 0);
spo : out std_logic_vector(3 downto 0);
dpo : out std_logic_vector(3 downto 0);
x : in std_logic);
end ram_2p;
architecture Behavioral of ram_2p is
type ram_type is array (31 downto 0) of std_logic_vector(3
downto 0);
signal ram:ram_type;
begin
process(clk)
begin
if (clk'event and clk='1')then
if(we='1')then
ram(conv_integer(addr))<=din;
end if;
end if;
end process;
process(clk)
begin
if (clk'event and clk='1')then
if (we='0')then
if(x='0')then
spo<=ram(conv_integer(addr));
else
dpo<=ram(conv_integer(addr));
end if;
end if;
end if;
end process;
end Behavioral;

31. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 10 out of 192 5%
Number of Slice Flip Flops: 8 out of 384 2%
Number of 4 input LUTs: 10 out of 384 2%
Number of bonded IOBs: 20 out of 90 22%
Number of GCLKs: 1 out of 4 25%

32. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Simulation Waveform

33. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------4:1 Multiplexer (CASE STATEMENT)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1_case is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_4_1_case;
architecture Behavioral of mux_4_1_case is
begin
process(a,b,c,d,s)
begin
case s is
when "00" => y<= a;
when "01" => y<= b;
when "10" => y<= c;
when others => y<= d;
end case;
end process;
end Behavioral;
-------4:1 Multiplexer (WHEN__ELSE STATEMENT)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1_when_else is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_4_1_when_else;
architecture Behavioral of mux_4_1_when_else is
begin
y<= a when s="00" else
b when s="01" else
c when s="10" else
d;
end Behavioral;

34. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------4:1 Multiplexer (IF__ELSE STATEMENT)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1_if is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_4_1_if;
architecture Behavioral of mux_4_1_if is
begin
process(s,a,b,c,d)
begin
if (s="00") then
y<=a;
elsif (s="01") then
y<=b;
elsif (s="10") then
y<=c;
else
y<=d;
end if;
end process;
end Behavioral;
-------4:1 Multiplexer (WITH___SELECT STATEMENT)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_4_1_with_select is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
d : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic);
end mux_4_1_with_select;
architecture Behavioral of mux_4_1_with_select is
begin
with s select
y<= a when "00",
b when "01",
c when "10",
d when others;
end Behavioral;

35. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Entity Level Diagram
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 1 out of 192 0%
Number of 4 input LUTs: 2 out of 384 0%
Number of bonded IOBs: 7 out of 90 7%
Simulation Waveform

36. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------8:1 Multiplexer------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_8_1 is
Port ( i : in std_logic_vector(7 downto 0);
s : in std_logic_vector(2 downto 0);
y : out std_logic);
end mux_8_1;
architecture Behavioral of mux_8_1 is
begin
with s select
y<= i(0) when "000",
i(1) when "001",
i(2) when "010",
i(3) when "011",
i(4) when "100",
i(5) when "101",
i(6) when "110",
i(7) when others;
end Behavioral;
Entity Level Diagram

37. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 2 out of 192 1%
Number of 4 input LUTs: 4 out of 384 1%
Number of bonded IOBs: 12 out of 90 13%
Simulation Waveform

38. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Sequence Detector (Mealy 1011)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mealy_1011 is
Port ( clk : in std_logic;
x : in std_logic;
reset:in std_logic;
z : out std_logic);
end mealy_1011;
architecture Behavioral of mealy_1011 is
type state is (s0,s1,s2,s3);
signal current:state;
begin
process(clk,x)
begin
if (reset='1')then
current<=s0;
z<='0';
elsif (clk'event and clk='1')then
case current is
when s0 =>
if (x='1')then
current<=s1;
z<='0';
else
current<=s0;
z<='0';
end if;
when s1 =>
if (x='0')then
current<=s2;
z<='0';
else
current<=s1;
z<='0';
end if;
when s2 =>
if (x='1')then
current<=s3;
z<='0';
else
current<=s0;
z<='0';
end if;

39. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
when s3 =>
if (x='1')then
current<=s1;
z<='1';
else
current<=s2;
z<='0';
end if;
when others=>
null;
end case;
end if;
end process;
end Behavioral;
Entity Level Diagram
Architectural Level Diagram

40. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 2 out of 768 0%
Number of Slice Flip Flops: 3 out of 1536 0%
Number of 4 input LUTs: 2 out of 1536 0%
Number of bonded IOBs: 4 out of 96 4%
Number of GCLKs: 1 out of 4 25%
Simulation Waveform

41. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Sequence Detector (Moore 1011)------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity moore_1011 is
Port ( clk : in std_logic;
x : in std_logic;
reset:in std_logic;
z : out std_logic);
end moore_1011;
architecture Behavioral of moore_1011 is
type state is (s0,s1,s2,s3,s4);
signal current:state;
begin
process(clk,x)
begin
if (reset='1')then
current<=s0;
elsif (clk'event and clk='1')then
case current is
when s0 =>
if (x='1')then
current<=s1;
else
current<=s0;
end if;
when s1 =>
if (x='0')then
current<=s2;
else
current<=s1;
end if;
when s2 =>
if (x='1')then
current<=s3;
else
current<=s0;
end if;
when s3 =>
if (x='1')then
current<=s4;
else
current<=s3;
end if;

42. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
when others=>
current<=s0;
end case;
end if;
end process;
z<='1' when current=s4 else
'0';
end Behavioral;
Entity Level Diagram
Architectural Level Diagram

43. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 2 out of 768 0%
Number of Slice Flip Flops: 3 out of 1536 0%
Number of 4 input LUTs: 3 out of 1536 0%
Number of bonded IOBs: 4 out of 96 4%
Number of GCLKs: 1 out of 4 25%
Simulation Waveform

44. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
-------Shift Register using Generate Statement------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shift_generate is
Port ( sin : in std_logic;
clk : in std_logic;
reset : in std_logic;
sout : out std_logic);
end shift_generate;
architecture Behavioral of shift_generate is
component d_ff is
Port ( d : in std_logic;
clk : in std_logic;
reset : in std_logic;
q : out std_logic);
end component;
signal temp:std_logic_vector(4 downto 0);
begin
temp(0)<=sin;
sreg:for i in 0 to 3 generate
u:d_ff port map (d=>temp(i),
clk=>clk,
reset=>reset,
q=>temp(i+1));
end generate;
sout<=temp(4);
end Behavioral;
Entity Level Diagram

45. Digital System Design
Department of Electronics Engg., P.V.P.I.T., Budhgaon
Architectural Level Diagram
Device utilization summary:
---------------------------
Number of Slices: 2 out of 1200 0%
Number of Slice Flip Flops: 4 out of 2400 0%
Number of bonded IOBs: 4 out of 96 4%
Number of GCLKs: 1 out of 4 25%
Simulation Waveform