SlideShare a Scribd company logo

2019 1 testing and verification of vlsi design_introduction

•
•
Usha Mehta
Usha Mehta

This is a introductory presentation for the course Testing and Verification of VLSI Design. The successive presentations follow.

Engineering
1 of 65
Download to read offline
Dr Usha Mehta usha.mehta@ieee.org usha.mehta@nirmauni.ac.in 1 DrUshaMehta22-07-2019
Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 DrUshaMehta22-07-2019
Agenda • Philosophy of Testing • Why to test • Do you love to be tested? • Where do bugs come from?. • When to test • When should be your test scheduled? • How to test • Verification and Testing in context of VLSI Design 3 DrUshaMehta22-07-2019
Murphy’s Law……. - Edward Murphy, An American aerospace engineer who worked on safety-critical systems 4 DrUshaMehta22-07-2019
Nothing is perfect……. 5 DrUshaMehta22-07-2019
6 DrUshaMehta22-07-2019
System Development … Project Starts here…. 7 DrUshaMehta22-07-2019 Courtesy: https://asiketltestanalyst.wordpress.com/tag/tom-and-jerry/
8 DrUshaMehta22-07-2019
9 DrUshaMehta22-07-2019
Tom has forgotten that “Nothing is perfect…….” 10 DrUshaMehta22-07-2019
11 DrUshaMehta22-07-2019
12 DrUshaMehta22-07-2019
13 DrUshaMehta22-07-2019
14 DrUshaMehta22-07-2019
15 DrUshaMehta22-07-2019
16 DrUshaMehta22-07-2019
17 DrUshaMehta22-07-2019
18 DrUshaMehta22-07-2019
19 DrUshaMehta22-07-2019
20 DrUshaMehta22-07-2019
21 DrUshaMehta22-07-2019
22 DrUshaMehta22-07-2019
23 DrUshaMehta22-07-2019
24 DrUshaMehta22-07-2019
• Intel, producer of the affected chip, claims that the common user would experience it once every 27,000 years while IBM, manufacturer of a chip competing with Intel's Pentium, claims that the common user would experience it once every 24 days • Loss of $475 million 25 DrUshaMehta22-07-2019
26 DrUshaMehta22-07-2019
27 DrUshaMehta22-07-2019
28 DrUshaMehta22-07-2019
If testing is so important, why do people not test it thoroughly? • To save money • To save time • To hide the inefficiencies • …. 29 DrUshaMehta22-07-2019
Tester…from Designer point of view….. • The relationship between the tester and everyone else in the project team has been like …. 30 DrUshaMehta22-07-2019
Why so love-hate relationship? Can you prove the lion exists ? Can you prove the ghost does exits ? Or does not exist? Testing can only show the presence of errors, never their absence. -Edsger Djikstra 31 DrUshaMehta22-07-2019
Tester….. From Production House point of view….. “Bugfree Design” does not give any extra revenue but bugs in design are very costly!!!! 32 DrUshaMehta22-07-2019
• Costly re-spin(s) • Companies may miss out market window • Large companies can have reputation at stake – e.g. Pentium Bug • Smaller companies can have hard to recover financial implications • For start-ups, their existence itself can be at stake! 33 DrUshaMehta22-07-2019 Respin…. 65 % of chips fail at first silicon Tester….. From Production House point of view…..
Tester….. From User Point of View….. 34 DrUshaMehta22-07-2019 Does user really value testing?
Tester Designer Does not love Consumer does not care Production house Does not want 35 DrUshaMehta22-07-2019
Even though….. testing is important….. 36 DrUshaMehta22-07-2019 • Does testing directly generate any revenue? • Does designer like testing? • Does it generate “trust” ? • Does trust generate “reusability”? • Does reusability generate “revenue”?
Why testing is of too much importance in today’s semiconductor world….. • In Earlier days, design had all the glamour and testing was considered to be a dirty job, but now… 37 DrUshaMehta22-07-2019 [Courtesy: ITRS]
Testing and Verification in Current Scenario • While the silicon capacity continues to increase along the Moore’s law, the efforts required to verify these designs have increased even a greater rate : doubling roughly every six to nine months. • In the era of multimillion gate Asics, reusable IPs, and SoC designs, 70% of the total efforts consumed by verification and testing. • Number of verification, validation, testing engineer is three the number of RTL design engineer • When design projects are completed, test benches makes up 80% of the total code volume. • Most of the job openings in India is in this field. • Design Hubs in Ahmedabad/Gujarat??? • Verification Hubs in Ahmedabad/Gujarat??? 38 DrUshaMehta22-07-2019
39 DrUshaMehta22-07-2019
Once they grow…… 40 DrUshaMehta22-07-2019 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
41 DrUshaMehta22-07-2019
• Design Errors • Misinterpretation of specification • Fabrication Errors • Wrong component • Incorrect Wiring • Fabrication Defects • Imperfect Process Variations • Physical Failure • During life time of a system 22-07-2019DrUshaMehta 42
ASIC Design Flow 43 DrUshaMehta22-07-2019
Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 44 DrUshaMehta22-07-2019 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field
Role of Testing in General • Verification • will any fault occur? • Validation • will fault occur during mass production? • Detection • Is there any fault? Yes or no? • Diagnosis • Where is the fault? • Device Characterization • Why the fault occurred? (Is design wrong or test process wrong?) • Failure Mode Analysis (FMA) • How that fault can be prevented? (Is manufacturing process wrong?) • Burn-In • Will it work for longer life? • Speed Binning • What is the speed of device? • Acceptance Testing/Incoming Inspection • Should I use it in my system? 45 DrUshaMehta22-07-2019
Verification • Verifies the correctness of Design • Performed once prior to manufacturing process • Performed by simulation, hardware emulation or formal methods • Responsible for quality of design • Like sonography used for unborn baby during pregnancy 46 DrUshaMehta22-07-2019
Validation Verification Testing/Characterization / Design Debug • After the first lot of prototypes are manufactured, IC goes through, design validation/pilot-run stage. • It checks that either the fabrication process was correct and fabricated IC is correct. ( Here it is assumed that design was error free) • Also verifies the correctness of test procedure. • AC, DC, Functional Test • Probing internal chip nodes also • Special tools like scanning electron Microscope, electron beam scanner, artificial intelligent technique etc, are used • Like Newborn sreening tests for baby 47 DrUshaMehta22-07-2019
Diagnosis • Identify the fault that exists in system. • Which fault is there (type of fault)? • Where is that fault (fault location)? • Like after a set of pathological test, the doctor diagnosis your disease. 48 DrUshaMehta22-07-2019
Device Characterization • Determination and correction of errors in device and/or test procedure • So that the next lot of IC will be error free. • Like doctor writes a prescription of medicine to cure your disease. • Here there is a difference between man and IC!!!!!!!!! 49 DrUshaMehta22-07-2019
Failure Mode Analysis • Why/How/when the fault had occurred? • Determine the manufacturing process errors that may have caused the fault. • Like determining why that disease occurred and find the preventive actions (bad health /food habits) which created disease 50 DrUshaMehta22-07-2019
Detection (testing in general…) • Does any of the fault exists? • Which, why, how, where, when is out of scope here. • Only YES/NO. Go/No Go test for IC to be shipped to market or not. • At fabrication unit • For all fabricated IC • Less comprehensive than characterization • Test should have high fault coverage, low cost and minimum test time • Are you completely fit? Does any of the disease there? • Like medical test for army ( if fit then go, otherwise no go) 51 DrUshaMehta22-07-2019
Burn-In/Stress Test • To stress the chip to accelerate the failure mechanism • Some chip passes the production test but will fail very quickly thereafter • To increase temp and/or voltage while applying test patterns • Infant Mortality Failures: 10-30 Hrs • Freak Failure: 100-1000Hrs 52 DrUshaMehta22-07-2019
Acceptance Testing/ Incoming Inspection • Customer performs this test • Like universal tester to test the IC at our Digital Electronics Labs 53 DrUshaMehta22-07-2019
Place of Verification in Design Flow • Specification • Finalization of specification • Behavioural Description/RTL code • Functional Verification • Gate level netlist • Static timing analysis • Circuit level • Propagation delay • Physical Domain • Layout vs Schematic (LVS) • During Fabrication • Wafer testing • Pilot lot production • Validation • Mass production • Testing • Burn-In • Speed Binning • Yield loss • Diagnosis • Failure Mode Analysis • Before use • Acceptance/Incomin g Testing • In-System 54 DrUshaMehta22-07-2019
Verification • On Design (functionality, estimated speed) • Pre-silicon • One time • Methods: • Simulation • Emulation • formal methods • A Design Bug • Makes all Fabricated IC useless Detection/Testing • On Device (manufactured hardware) • Post-Silicon • On all ICs, i.e. every time IC is fabricated • Methods: • Test Generation • Test Application • A fabrication defect • May cause all ICs or Some of the ICs useless. 55 DrUshaMehta22-07-2019
TTM : Time-to-MONEY 56 DrUshaMehta22-07-2019 Validation Test
Failure Rate vs Product Life Time 57 DrUshaMehta22-07-2019
Software Failure Rate 58 DrUshaMehta22-07-2019
59 DrUshaMehta22-07-2019
Test Principal for Digital Circuits 60 DrUshaMehta22-07-2019
61 DrUshaMehta22-07-2019
Mid Test….  Calculate the time required to test a 64 bit adder at the speed of 1 GHz  64 bit adder => 129 inputs, 65 outputs • Is it possible???????????????????????? • The manufacturing house wants to complete it into few mins only. 62 DrUshaMehta22-07-2019
63 DrUshaMehta22-07-2019
Thanks……

Recommended

6 verification tools
6 verification tools6 verification tools
6 verification toolsUsha Mehta
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yieldUsha Mehta
 
5 verification methods
5 verification methods5 verification methods
5 verification methodsUsha Mehta
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designUsha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verificationUsha Mehta
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testingUsha Mehta
 
1 why to_test
1 why to_test1 why to_test
1 why to_testUsha Mehta
 

Recommended

6 verification tools
6 verification tools6 verification tools
6 verification toolsUsha Mehta
 
3 test economic_test_equipments_yield
3 test economic_test_equipments_yield3 test economic_test_equipments_yield
3 test economic_test_equipments_yieldUsha Mehta
 
5 verification methods
5 verification methods5 verification methods
5 verification methodsUsha Mehta
 
Verification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designVerification flow and_planning_vlsi_design
Verification flow and_planning_vlsi_designUsha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verification2019 2 testing and verification of vlsi design_verification
2019 2 testing and verification of vlsi design_verificationUsha Mehta
 
2 when to_test_role_of_testing
2 when to_test_role_of_testing2 when to_test_role_of_testing
2 when to_test_role_of_testingUsha Mehta
 
1 why to_test
1 why to_test1 why to_test
1 why to_testUsha Mehta
 
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Usha Mehta
 
2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modeling2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modelingUsha Mehta
 
Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)Usha Mehta
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Usha Mehta
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planningUsha Mehta
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDilip Mathuria
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_designUsha Mehta
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_sta2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_staUsha Mehta
 
01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swetha01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swethaswethamg18
 
Testing and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionTesting and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionUsha Mehta
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossingUsha Mehta
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_designUsha Mehta
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsDr. Shivananda Koteshwar
 
Scan insertion
Scan insertionScan insertion
Scan insertionkumar gavanurmath
 
Design for Testability
Design for Testability Design for Testability
Design for Testability kumar gavanurmath
 
Clock Tree Timing 101
Clock Tree Timing 101Clock Tree Timing 101
Clock Tree Timing 101Silicon Labs
 
Fault equivalence and fault location
Fault equivalence and fault locationFault equivalence and fault location
Fault equivalence and fault locationPranoti Bachhav
 
1 why to_test
1 why to_test1 why to_test
1 why to_testUsha Mehta
 
6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem Final6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem FinalEggplant
 

More Related Content

What's hot

Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Usha Mehta
 
2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modeling2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modelingUsha Mehta
 
Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)Usha Mehta
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Usha Mehta
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planningUsha Mehta
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDilip Mathuria
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_designUsha Mehta
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_sta2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_staUsha Mehta
 
01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swetha01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swethaswethamg18
 
Testing and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionTesting and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionUsha Mehta
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossingUsha Mehta
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Usha Mehta
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_designUsha Mehta
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsDr. Shivananda Koteshwar
 
Clock Tree Timing 101
Clock Tree Timing 101Clock Tree Timing 101
Clock Tree Timing 101Silicon Labs
 
Fault equivalence and fault location
Fault equivalence and fault locationFault equivalence and fault location
Fault equivalence and fault locationPranoti Bachhav
 

What's hot (20)

Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
 
2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modeling2019 5 testing and verification of vlsi design_fault_modeling
2019 5 testing and verification of vlsi design_fault_modeling
 
Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)Fault Simulation (Testing of VLSI Design)
Fault Simulation (Testing of VLSI Design)
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdf
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)
 
4 verification flow_planning
4 verification flow_planning4 verification flow_planning
4 verification flow_planning
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generation
 
12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design12 static timing_analysis_3_clocked_design
12 static timing_analysis_3_clocked_design
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
 
2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_sta2019 3 testing and verification of vlsi design_sta
2019 3 testing and verification of vlsi design_sta
 
01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swetha01 Transition Fault Detection methods by Swetha
01 Transition Fault Detection methods by Swetha
 
Testing and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : IntroductionTesting and Verification of Electronics Circuits : Introduction
Testing and Verification of Electronics Circuits : Introduction
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing
 
Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)Automatic Test Pattern Generation (Testing of VLSI Design)
Automatic Test Pattern Generation (Testing of VLSI Design)
 
11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design11 static timing_analysis_2_combinational_design
11 static timing_analysis_2_combinational_design
 
Verification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICsVerification challenges and methodologies - SoC and ASICs
Verification challenges and methodologies - SoC and ASICs
 
Scan insertion
Scan insertionScan insertion
Scan insertion
 
Design for Testability
Design for Testability Design for Testability
Design for Testability
 
Clock Tree Timing 101
Clock Tree Timing 101Clock Tree Timing 101
Clock Tree Timing 101
 
Fault equivalence and fault location
Fault equivalence and fault locationFault equivalence and fault location
Fault equivalence and fault location
 

Similar to 2019 1 testing and verification of vlsi design_introduction

6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem Final6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem FinalEggplant
 
6 Top Tips to a Testing Strategy That Works
6 Top Tips to a Testing Strategy That Works6 Top Tips to a Testing Strategy That Works
6 Top Tips to a Testing Strategy That WorksEggplant
 
Software Testing Future and Challenges
Software Testing Future and ChallengesSoftware Testing Future and Challenges
Software Testing Future and ChallengesBakr Salim
 
Arizona State University Test Lecture
Arizona State University Test LectureArizona State University Test Lecture
Arizona State University Test LecturePete Sarson, PH.D
 
Claudiu Draghia ITEM 2018
Claudiu Draghia ITEM 2018Claudiu Draghia ITEM 2018
Claudiu Draghia ITEM 2018ITEM
 
onlineexaminationsystem-140315133558-phpapp01.pdf
onlineexaminationsystem-140315133558-phpapp01.pdfonlineexaminationsystem-140315133558-phpapp01.pdf
onlineexaminationsystem-140315133558-phpapp01.pdfNakhabalaMaurice
 
Online examination system
Online examination systemOnline examination system
Online examination systemAj Maurya
 
Onlineexaminationsystem 140315133558-phpapp01
Onlineexaminationsystem 140315133558-phpapp01Onlineexaminationsystem 140315133558-phpapp01
Onlineexaminationsystem 140315133558-phpapp01Er aditya kumar jha
 
Project report on online examination system
Project report on online examination systemProject report on online examination system
Project report on online examination systemMo Irshad Ansari
 
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​Eggplant
 
Keynote AST 2016
Keynote AST 2016Keynote AST 2016
Keynote AST 2016Kim Herzig
 
Technology-Driven Development: Using Automation and Development Techniques to...
Technology-Driven Development: Using Automation and Development Techniques to...Technology-Driven Development: Using Automation and Development Techniques to...
Technology-Driven Development: Using Automation and Development Techniques to...Hiroyuki Ito
 
FutureOfTesting2008
FutureOfTesting2008FutureOfTesting2008
FutureOfTesting2008vipulkocher
 
Ai lecture 06 applications of es
Ai lecture 06 applications of esAi lecture 06 applications of es
Ai lecture 06 applications of esAhmad sohail Kakar
 
Electronic product design and development -2
Electronic product design and development -2Electronic product design and development -2
Electronic product design and development -2Vinayak Bairagi
 
Testing without defined requirements
Testing without defined requirementsTesting without defined requirements
Testing without defined requirementsrrice2000
 
Test planning and software's engineering
Test planning and software's engineeringTest planning and software's engineering
Test planning and software's engineeringMansiganeshJawale
 
SOFTWARE TESTING W1_watermark.pdf
SOFTWARE TESTING W1_watermark.pdfSOFTWARE TESTING W1_watermark.pdf
SOFTWARE TESTING W1_watermark.pdfShubhamSingh606946
 

Similar to 2019 1 testing and verification of vlsi design_introduction (20)

1 why to_test
1 why to_test1 why to_test
1 why to_test
 
6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem Final6 Steps to Implementing a World Class Testing Ecosystem Final
6 Steps to Implementing a World Class Testing Ecosystem Final
 
6 Top Tips to a Testing Strategy That Works
6 Top Tips to a Testing Strategy That Works6 Top Tips to a Testing Strategy That Works
6 Top Tips to a Testing Strategy That Works
 
Software Testing Future and Challenges
Software Testing Future and ChallengesSoftware Testing Future and Challenges
Software Testing Future and Challenges
 
Arizona State University Test Lecture
Arizona State University Test LectureArizona State University Test Lecture
Arizona State University Test Lecture
 
Mbt4masses
Mbt4massesMbt4masses
Mbt4masses
 
Claudiu Draghia ITEM 2018
Claudiu Draghia ITEM 2018Claudiu Draghia ITEM 2018
Claudiu Draghia ITEM 2018
 
onlineexaminationsystem-140315133558-phpapp01.pdf
onlineexaminationsystem-140315133558-phpapp01.pdfonlineexaminationsystem-140315133558-phpapp01.pdf
onlineexaminationsystem-140315133558-phpapp01.pdf
 
Online examination system
Online examination systemOnline examination system
Online examination system
 
Onlineexaminationsystem 140315133558-phpapp01
Onlineexaminationsystem 140315133558-phpapp01Onlineexaminationsystem 140315133558-phpapp01
Onlineexaminationsystem 140315133558-phpapp01
 
Project report on online examination system
Project report on online examination systemProject report on online examination system
Project report on online examination system
 
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​
Strategy vs. Tactical Testing: Actions for Today, Plans for Tomorrow​
 
Keynote AST 2016
Keynote AST 2016Keynote AST 2016
Keynote AST 2016
 
Technology-Driven Development: Using Automation and Development Techniques to...
Technology-Driven Development: Using Automation and Development Techniques to...Technology-Driven Development: Using Automation and Development Techniques to...
Technology-Driven Development: Using Automation and Development Techniques to...
 
FutureOfTesting2008
FutureOfTesting2008FutureOfTesting2008
FutureOfTesting2008
 
Ai lecture 06 applications of es
Ai lecture 06 applications of esAi lecture 06 applications of es
Ai lecture 06 applications of es
 
Electronic product design and development -2
Electronic product design and development -2Electronic product design and development -2
Electronic product design and development -2
 
Testing without defined requirements
Testing without defined requirementsTesting without defined requirements
Testing without defined requirements
 
Test planning and software's engineering
Test planning and software's engineeringTest planning and software's engineering
Test planning and software's engineering
 
SOFTWARE TESTING W1_watermark.pdf
SOFTWARE TESTING W1_watermark.pdfSOFTWARE TESTING W1_watermark.pdf
SOFTWARE TESTING W1_watermark.pdf
 

More from Usha Mehta

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysUsha Mehta
 
Field Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureField Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureUsha Mehta
 
Programmable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDProgrammable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDUsha Mehta
 
Programmable Switches for Programmable Logic Devices
Programmable Switches for Programmable Logic DevicesProgrammable Switches for Programmable Logic Devices
Programmable Switches for Programmable Logic DevicesUsha Mehta
 
2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdf2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdfUsha Mehta
 
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdfUsha Mehta
 
7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdfUsha Mehta
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdfUsha Mehta
 
8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdf8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdfUsha Mehta
 
9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdf9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdfUsha Mehta
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdfUsha Mehta
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memoryUsha Mehta
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysisUsha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehtaUsha Mehta
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignUsha Mehta
 

More from Usha Mehta (15)

Basic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate ArraysBasic Design Flow for Field Programmable Gate Arrays
Basic Design Flow for Field Programmable Gate Arrays
 
Field Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : ArchitectureField Programmable Gate Arrays : Architecture
Field Programmable Gate Arrays : Architecture
 
Programmable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLDProgrammable Logic Devices : SPLD and CPLD
Programmable Logic Devices : SPLD and CPLD
 
Programmable Switches for Programmable Logic Devices
Programmable Switches for Programmable Logic DevicesProgrammable Switches for Programmable Logic Devices
Programmable Switches for Programmable Logic Devices
 
2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdf2_DVD_ASIC_Design_FLow.pdf
2_DVD_ASIC_Design_FLow.pdf
 
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
3_DVD_IC_Fabrication_Flow_designer_perspective.pdf
 
7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf7_DVD_Combinational_MOS_Logic_Circuits.pdf
7_DVD_Combinational_MOS_Logic_Circuits.pdf
 
5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf5_DVD_VLSI Technology Trends.pdf
5_DVD_VLSI Technology Trends.pdf
 
8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdf8_DVD_Sequential_MOS_logic_circuits.pdf
8_DVD_Sequential_MOS_logic_circuits.pdf
 
9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdf9_DVD_Dynamic_logic_circuits.pdf
9_DVD_Dynamic_logic_circuits.pdf
 
13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf13_DVD_Latch-up_prevention.pdf
13_DVD_Latch-up_prevention.pdf
 
9 semiconductor memory
9 semiconductor memory9 semiconductor memory
9 semiconductor memory
 
10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis10 static timing_analysis_1_concept_of_timing_analysis
10 static timing_analysis_1_concept_of_timing_analysis
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehta
 
BUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI DesignBUilt-In-Self-Test for VLSI Design
BUilt-In-Self-Test for VLSI Design
 

Recently uploaded

(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...ranjana rawat
 
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Dr.Costas Sachpazis
 
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur High Profile
 
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...ranjana rawat
 
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...Soham Mondal
 
Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)simmis5
 
Extrusion Processes and Their Limitations
Extrusion Processes and Their LimitationsExtrusion Processes and Their Limitations
Extrusion Processes and Their Limitations120cr0395
 
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escortsranjana rawat
 
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...Dr.Costas Sachpazis
 
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...Call Girls in Nagpur High Profile
 
KubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlyKubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlysanyuktamishra911
 
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130Suhani Kapoor
 
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).pptssuser5c9d4b1
 
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...Christo Ananth
 
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...roncy bisnoi
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxAsutosh Ranjan
 
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...ranjana rawat
 
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...ranjana rawat
 
AKTU Computer Networks notes --- Unit 3.pdf
AKTU Computer Networks notes --- Unit 3.pdfAKTU Computer Networks notes --- Unit 3.pdf
AKTU Computer Networks notes --- Unit 3.pdfankushspencer015
 

Recently uploaded (20)

(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
(SHREYA) Chakan Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Esc...
 
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
Sheet Pile Wall Design and Construction: A Practical Guide for Civil Engineer...
 
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur EscortsCall Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
Call Girls in Nagpur Suman Call 7001035870 Meet With Nagpur Escorts
 
Water Industry Process Automation & Control Monthly - April 2024
Water Industry Process Automation & Control Monthly - April 2024Water Industry Process Automation & Control Monthly - April 2024
Water Industry Process Automation & Control Monthly - April 2024
 
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...
The Most Attractive Pune Call Girls Manchar 8250192130 Will You Miss This Cha...
 
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...
OSVC_Meta-Data based Simulation Automation to overcome Verification Challenge...
 
Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)Java Programming :Event Handling(Types of Events)
Java Programming :Event Handling(Types of Events)
 
Extrusion Processes and Their Limitations
Extrusion Processes and Their LimitationsExtrusion Processes and Their Limitations
Extrusion Processes and Their Limitations
 
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
(MEERA) Dapodi Call Girls Just Call 7001035870 [ Cash on Delivery ] Pune Escorts
 
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...
Structural Analysis and Design of Foundations: A Comprehensive Handbook for S...
 
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...
Booking open Available Pune Call Girls Koregaon Park 6297143586 Call Hot Ind...
 
KubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghlyKubeKraft presentation @CloudNativeHooghly
KubeKraft presentation @CloudNativeHooghly
 
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130
VIP Call Girls Service Kondapur Hyderabad Call +91-8250192130
 
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
247267395-1-Symmetric-and-distributed-shared-memory-architectures-ppt (1).ppt
 
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...
Call for Papers - African Journal of Biological Sciences, E-ISSN: 2663-2187, ...
 
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
Call Girls Pimpri Chinchwad Call Me 7737669865 Budget Friendly No Advance Boo...
 
Coefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptxCoefficient of Thermal Expansion and their Importance.pptx
Coefficient of Thermal Expansion and their Importance.pptx
 
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(PRIYA) Rajgurunagar Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
 
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
(ANVI) Koregaon Park Call Girls Just Call 7001035870 [ Cash on Delivery ] Pun...
 
AKTU Computer Networks notes --- Unit 3.pdf
AKTU Computer Networks notes --- Unit 3.pdfAKTU Computer Networks notes --- Unit 3.pdf
AKTU Computer Networks notes --- Unit 3.pdf
 

2019 1 testing and verification of vlsi design_introduction

  • 2. Acknowledgement….. This presentation has been summarized from various books, papers, websites and presentations on VLSI Design and its various topics all over the world. I couldn’t item-wise mention from where these large pull of hints and work come. However, I’d like to thank all professors and scientists who created such a good work on this emerging field. Without those efforts in this very emerging technology, these notes and slides can’t be finished. 2 DrUshaMehta22-07-2019
  • 3. Agenda • Philosophy of Testing • Why to test • Do you love to be tested? • Where do bugs come from?. • When to test • When should be your test scheduled? • How to test • Verification and Testing in context of VLSI Design 3 DrUshaMehta22-07-2019
  • 4. Murphy’s Law……. - Edward Murphy, An American aerospace engineer who worked on safety-critical systems 4 DrUshaMehta22-07-2019
  • 7. System Development … Project Starts here…. 7 DrUshaMehta22-07-2019 Courtesy: https://asiketltestanalyst.wordpress.com/tag/tom-and-jerry/
  • 10. Tom has forgotten that “Nothing is perfect…….” 10 DrUshaMehta22-07-2019
  • 25. • Intel, producer of the affected chip, claims that the common user would experience it once every 27,000 years while IBM, manufacturer of a chip competing with Intel's Pentium, claims that the common user would experience it once every 24 days • Loss of $475 million 25 DrUshaMehta22-07-2019
  • 29. If testing is so important, why do people not test it thoroughly? • To save money • To save time • To hide the inefficiencies • …. 29 DrUshaMehta22-07-2019
  • 30. Tester…from Designer point of view….. • The relationship between the tester and everyone else in the project team has been like …. 30 DrUshaMehta22-07-2019
  • 31. Why so love-hate relationship? Can you prove the lion exists ? Can you prove the ghost does exits ? Or does not exist? Testing can only show the presence of errors, never their absence. -Edsger Djikstra 31 DrUshaMehta22-07-2019
  • 32. Tester….. From Production House point of view….. “Bugfree Design” does not give any extra revenue but bugs in design are very costly!!!! 32 DrUshaMehta22-07-2019
  • 33. • Costly re-spin(s) • Companies may miss out market window • Large companies can have reputation at stake – e.g. Pentium Bug • Smaller companies can have hard to recover financial implications • For start-ups, their existence itself can be at stake! 33 DrUshaMehta22-07-2019 Respin…. 65 % of chips fail at first silicon Tester….. From Production House point of view…..
  • 34. Tester….. From User Point of View….. 34 DrUshaMehta22-07-2019 Does user really value testing?
  • 35. Tester Designer Does not love Consumer does not care Production house Does not want 35 DrUshaMehta22-07-2019
  • 36. Even though….. testing is important….. 36 DrUshaMehta22-07-2019 • Does testing directly generate any revenue? • Does designer like testing? • Does it generate “trust” ? • Does trust generate “reusability”? • Does reusability generate “revenue”?
  • 37. Why testing is of too much importance in today’s semiconductor world….. • In Earlier days, design had all the glamour and testing was considered to be a dirty job, but now… 37 DrUshaMehta22-07-2019 [Courtesy: ITRS]
  • 38. Testing and Verification in Current Scenario • While the silicon capacity continues to increase along the Moore’s law, the efforts required to verify these designs have increased even a greater rate : doubling roughly every six to nine months. • In the era of multimillion gate Asics, reusable IPs, and SoC designs, 70% of the total efforts consumed by verification and testing. • Number of verification, validation, testing engineer is three the number of RTL design engineer • When design projects are completed, test benches makes up 80% of the total code volume. • Most of the job openings in India is in this field. • Design Hubs in Ahmedabad/Gujarat??? • Verification Hubs in Ahmedabad/Gujarat??? 38 DrUshaMehta22-07-2019
  • 40. Once they grow…… 40 DrUshaMehta22-07-2019 Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process
  • 42. • Design Errors • Misinterpretation of specification • Fabrication Errors • Wrong component • Incorrect Wiring • Fabrication Defects • Imperfect Process Variations • Physical Failure • During life time of a system 22-07-2019DrUshaMehta 42
  • 44. Architectural Behavioural RTL Gate Transistor Physical Unpacked Chip 44 DrUshaMehta22-07-2019 Circuit Chip, Components, Interconnects… System System on Chip Network on Chip Prototype Testing Mass Production Testing System @ Field
  • 45. Role of Testing in General • Verification • will any fault occur? • Validation • will fault occur during mass production? • Detection • Is there any fault? Yes or no? • Diagnosis • Where is the fault? • Device Characterization • Why the fault occurred? (Is design wrong or test process wrong?) • Failure Mode Analysis (FMA) • How that fault can be prevented? (Is manufacturing process wrong?) • Burn-In • Will it work for longer life? • Speed Binning • What is the speed of device? • Acceptance Testing/Incoming Inspection • Should I use it in my system? 45 DrUshaMehta22-07-2019
  • 46. Verification • Verifies the correctness of Design • Performed once prior to manufacturing process • Performed by simulation, hardware emulation or formal methods • Responsible for quality of design • Like sonography used for unborn baby during pregnancy 46 DrUshaMehta22-07-2019
  • 47. Validation Verification Testing/Characterization / Design Debug • After the first lot of prototypes are manufactured, IC goes through, design validation/pilot-run stage. • It checks that either the fabrication process was correct and fabricated IC is correct. ( Here it is assumed that design was error free) • Also verifies the correctness of test procedure. • AC, DC, Functional Test • Probing internal chip nodes also • Special tools like scanning electron Microscope, electron beam scanner, artificial intelligent technique etc, are used • Like Newborn sreening tests for baby 47 DrUshaMehta22-07-2019
  • 48. Diagnosis • Identify the fault that exists in system. • Which fault is there (type of fault)? • Where is that fault (fault location)? • Like after a set of pathological test, the doctor diagnosis your disease. 48 DrUshaMehta22-07-2019
  • 49. Device Characterization • Determination and correction of errors in device and/or test procedure • So that the next lot of IC will be error free. • Like doctor writes a prescription of medicine to cure your disease. • Here there is a difference between man and IC!!!!!!!!! 49 DrUshaMehta22-07-2019
  • 50. Failure Mode Analysis • Why/How/when the fault had occurred? • Determine the manufacturing process errors that may have caused the fault. • Like determining why that disease occurred and find the preventive actions (bad health /food habits) which created disease 50 DrUshaMehta22-07-2019
  • 51. Detection (testing in general…) • Does any of the fault exists? • Which, why, how, where, when is out of scope here. • Only YES/NO. Go/No Go test for IC to be shipped to market or not. • At fabrication unit • For all fabricated IC • Less comprehensive than characterization • Test should have high fault coverage, low cost and minimum test time • Are you completely fit? Does any of the disease there? • Like medical test for army ( if fit then go, otherwise no go) 51 DrUshaMehta22-07-2019
  • 52. Burn-In/Stress Test • To stress the chip to accelerate the failure mechanism • Some chip passes the production test but will fail very quickly thereafter • To increase temp and/or voltage while applying test patterns • Infant Mortality Failures: 10-30 Hrs • Freak Failure: 100-1000Hrs 52 DrUshaMehta22-07-2019
  • 53. Acceptance Testing/ Incoming Inspection • Customer performs this test • Like universal tester to test the IC at our Digital Electronics Labs 53 DrUshaMehta22-07-2019
  • 54. Place of Verification in Design Flow • Specification • Finalization of specification • Behavioural Description/RTL code • Functional Verification • Gate level netlist • Static timing analysis • Circuit level • Propagation delay • Physical Domain • Layout vs Schematic (LVS) • During Fabrication • Wafer testing • Pilot lot production • Validation • Mass production • Testing • Burn-In • Speed Binning • Yield loss • Diagnosis • Failure Mode Analysis • Before use • Acceptance/Incomin g Testing • In-System 54 DrUshaMehta22-07-2019
  • 55. Verification • On Design (functionality, estimated speed) • Pre-silicon • One time • Methods: • Simulation • Emulation • formal methods • A Design Bug • Makes all Fabricated IC useless Detection/Testing • On Device (manufactured hardware) • Post-Silicon • On all ICs, i.e. every time IC is fabricated • Methods: • Test Generation • Test Application • A fabrication defect • May cause all ICs or Some of the ICs useless. 55 DrUshaMehta22-07-2019
  • 57. Failure Rate vs Product Life Time 57 DrUshaMehta22-07-2019
  • 60. Test Principal for Digital Circuits 60 DrUshaMehta22-07-2019
  • 62. Mid Test….  Calculate the time required to test a 64 bit adder at the speed of 1 GHz  64 bit adder => 129 inputs, 65 outputs • Is it possible???????????????????????? • The manufacturing house wants to complete it into few mins only. 62 DrUshaMehta22-07-2019
  • 64.