This document discusses fault models for testing digital circuits. It begins with acknowledging previous work in the field and defining key terms like defects, errors, and faults. It then discusses the structural fault model and focuses on single stuck-at faults, providing examples of detectable, undetectable, and redundant faults. The document also discusses fault equivalence, fault collapsing, and fault dominance techniques for reducing the number of faults to be tested. It promotes developing one's own EDA tool to perform operations like fault equivalence on circuit netlists.
Introduction of testing and verification of vlsi designUsha Mehta
This slides are introductory slides for the course testing and verification of VLSI Design which cover the basics of Why, Where, When and How of VLSI design testing
Introduction of testing and verification of vlsi designUsha Mehta
This slides are introductory slides for the course testing and verification of VLSI Design which cover the basics of Why, Where, When and How of VLSI design testing
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Spyglass DFT is comprehensive process of resolving RTL Design issues, thereby ensuring high quality RTL with fewer design bugs.
Improves test quality by diagnosing DFT issues early at RTL or netlist.
Shortens test implementation time and cost by ensuring RTL or netlist is scan-compliant.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
This is the first session from a series of sessions on Verification of VLSI Design. It focus on the basic flow of verification in context of system design flow, types of verification, Functional, formal and semi-formal verification, Simulation, Emulation and Static Timing Analysis.
Level sensitive scan design(LSSD) and Boundry scan(BS)Praveen Kumar
This presentation contains,
Introduction,design for testability, scan chain, operation, scan structure, test vectors, Boundry scan, test logic, operation, BS cell, states of TAP controller, Boundry scan instructions.
Spyglass DFT is comprehensive process of resolving RTL Design issues, thereby ensuring high quality RTL with fewer design bugs.
Improves test quality by diagnosing DFT issues early at RTL or netlist.
Shortens test implementation time and cost by ensuring RTL or netlist is scan-compliant.
01 Transition Fault Detection methods by Swethaswethamg18
Fault Models
Stuck-at fault test covers
Shorts and opens
Resistive shorts – Not covered
Delay fault test covers
Resistive opens and coupling faults
Resistive power supply lines
Process variations
Delay Fault Testing
Propagation delay of all paths in a circuit must be less than clock period for correct operation
Functional tests applied at operational speed of circuit are often used for delay faults
Scan based stuck-at tests are often applied at speed
However, functional and stuck-at testing even if done at-speed do not specifically target delay faults
Scan design is currently the most popular structured DFT approach. It is implemented by Connecting selected storage elements present in the design into multiple shift registers, called Scan chains.
Scannability Rules -->
The tool perform basic two check
1) It ensures all the defined clocks including set/Reset are at their off-states, the sequential element remain stable and inactive. (S1)
2) It ensures for each defined clocks can capture data when all other defined clocks are off. (S2)
This is the first session from a series of sessions on Verification of VLSI Design. It focus on the basic flow of verification in context of system design flow, types of verification, Functional, formal and semi-formal verification, Simulation, Emulation and Static Timing Analysis.
PLCs running code generated from MATLAB/Simulink have recently been promoted heavily on the Hannover Messe and SPS Drives. What is this? How do we use the quite unknown oversampling and I-Device features of PROFINET to even extend the application range? Some basics and use cases from industry to inspire you!
Get Loose! Microservices and Loosely Coupled Architectures DevOps.com
The recently published results from the 2017 State of DevOps Survey shows that loosely coupled architectures and teams are the strongest predictor of continuous delivery. Microservices and Containers are a great choice for creating these loosely coupled systems. But, many teams find it hard to decompose monolithic applications into Microservices, and they find it harder still to coordinate deployments and releases into the emergent “hyper-hybrid” operating environments.
Get Loose! Microservices and Loosely Coupled ArchitecturesDeborah Schalm
The recently published results from the 2017 State of DevOps Survey shows that loosely coupled architectures and teams are the strongest predictor of continuous delivery. Microservices and Containers are a great choice for creating these loosely coupled systems. But, many teams find it hard to decompose monolithic applications into Microservices, and they find it harder still to coordinate deployments and releases into the emergent “hyper-hybrid” operating environments.
Bart Knaack - The Truth About Model-Based Quality ImprovementsTEST Huddle
EuroSTAR Software Testing Conference 2008 presentation on The Truth About Model-Based Quality Improvements by Bart Knaack. See more at conferences.eurostarsoftwaretesting.com/past-presentations/
As many utilities have elected to deploy advanced metering systems and millions of new solid-state, microprocessor based end-points with communications under glass, a dramatic shift has begun regarding where metering resources are being deployed and what they are doing.
This presentation will highlight the new value proposition for metering personnel at their respective utility companies in this AMI dominated World.
Examples of issues which have arisen or been identified over the course of various deployments and in the immediate aftermath of an AMI deployment.
Fiatech 2014 - Computer Simulation of Pipe Fabrication, Ramzi LabbanCCT International
Pipe spool fabrication is major component of construction operations on large industrial projects. The nature of spooling is relatively short term involving complex construction process and riddled with uncertainty due to the intrinsic unique nature of its outputs and the numerous factors affecting its activities.
With this in mind, it is important for all stakeholders to have a good grasp of the performance of pipe fabrication shops and their ability to meet the site pipe installation schedules.
Matthew Hause "Building Bridges between Systems and Software with SysML and UML" presentation to INCOSE Colorado Front Range Chapter at Northrop Grumman, Boulder, CO. March 17, 2015
Pipe spool fabrication is major component of construction operations on large industrial projects. The nature of spooling is relatively short term involving complex construction process and riddled with uncertainty due to the intrinsic unique nature of its outputs and the numerous factors affecting its activities.
With this in mind, it is important for all stakeholders to have a good grasp of the performance of pipe fabrication shops and their ability to meet the site pipe installation schedules.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
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The Division of Vaccine and Immunization is facing increasing difficulty monitoring vaccines and other commodities distribution once they have been distributed from the national stores. With the introduction of new vaccines, more challenges have been anticipated with this additions posing serious threat to the already over strained vaccine supply chain system in Kenya.
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CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
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Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Courier management system project report.pdfKamal Acharya
It is now-a-days very important for the people to send or receive articles like imported furniture, electronic items, gifts, business goods and the like. People depend vastly on different transport systems which mostly use the manual way of receiving and delivering the articles. There is no way to track the articles till they are received and there is no way to let the customer know what happened in transit, once he booked some articles. In such a situation, we need a system which completely computerizes the cargo activities including time to time tracking of the articles sent. This need is fulfilled by Courier Management System software which is online software for the cargo management people that enables them to receive the goods from a source and send them to a required destination and track their status from time to time.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
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2. Acknowledgement…..
This presentation has been summarized from
various books, papers, websites and
presentations on VLSI Design and its various
topics all over the world. I couldn’t itemwise
mention from where these large pull of hints and
work come. However, I’d like to thank all
professors and scientists who created such a
good work on this emerging field. Without those
efforts in this very emerging technology, these
notes and slides can’t be finished.
05-10-2019DrUshaMehta
2
4. Test Principal for Digital Circuits is
Universal…….
05-10-2019DrUshaMehta
4
5. Verification
• On Design
(functionality,
estimated speed)
• Pre-silicon
• One time
• By simulation,
emulation, formal
methods
• A Design Bug
• Makes all Fabricated
IC useless
• Less prone to occur
Detection/Testing
• On Device
(manufactured
hardware)
• Post-Silicon
• On all ICs, i.e. every
time IC is fabricated
• By Test Generation
and Test Application
• A fabrication defect
• May cause all ICs or
Some of the ICs
useless.
• More prone to occur
because of small
geometry
05-10-2019DrUshaMehta
5
6. What is Ideal Test?
• Ideal tests detect all defects produced in the manufacturing
process.
• Ideal tests pass all functionally good devices.
• Very large numbers and varieties of possible defects need to
be tested.
• Difficult to generate tests for some real defects.
• Defect-oriented testing is an open problem.
• Is it practical?
05-10-2019DrUshaMehta
6
7. Testing Philosophy
• Students-chips
• Course syllabus – specifications
• No one has infinite time
• Test paper – fault model
• If Failed,
• repeat the course - respin
• Interaction in class: verification
• Asking teachers the details in
advance – DFT
• If too hard question paper: a
student of pass category fails –
student’s image at risk
(manufacturer’s risk) – yield loss
• If too easy question paper: a
student of fail category passes –
teacher’s image at risk
(consumer’s risk) – defect level
or reject rate
05-10-2019DrUshaMehta
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8. Test Plan
• Design House: Design is complete and checked
(verified)
• Fab vendor: How will you test it?
• Design house: I have checked it and …
• Fab vendor: OK. But, how would you test it?
• Design house: Why is that important?
• Complete the story…..
• None of the fab will manufacture your design if
you can not satisfy them with proper test plan.
• That is one reason for design-for testability,
test generation, Built-In-Self-Test etc.
05-10-2019DrUshaMehta
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10. Cost Components of Testing
• Test Development Cost
• Software process of test
• Test generation and fault simulation
• Test programming and debugging
• Test Application Cost
• ATE Cost
• Test Center Operation Cost
• Depends on Test Time per IC
• DFT
• Chip Area Overhead and Yield Reduction
• Performance Overhead
05-10-2019DrUshaMehta
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11. What do we mean by
Effective Testing…..
• It means… now onwards all over efforts should be
for more and more effective testing….
It means……
• More fault coverage
• Less test cost
• Less test application time
• Less test power
• More yield
05-10-2019DrUshaMehta
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12. Functional vs Structural testing
• For your hardware projects, the steps you follow
are:
• Specification
• Design
• Simulate (Verification – Functional Testing)
• Fabricate
• Testing (Structural Testing)
• Observation of each component and wire working fine
individually!, assumed that if it individual components
are fine and connections are right, the PCB will produce
intended functions correctly)
• Easy and Fast compared to structural
12
DrUshaMehta05-10-2019
13. Functional Test
• Black Box Approach
Functional ATPG –
generate complete set of
tests for circuit input-
output combinations
◦ 129 inputs, 65 outputs:
◦ 2129 =
680,564,733,841,876,92
6,926,749,214,863,536,
422,912 patterns
◦ Using 1 GHz ATE, would
take
2.15 x 1022 years
Structural Test
• White Box Approach
Structural test:
◦ No redundant adder hardware,
64 bit slices
◦ Each with 27 faults (using fault
equivalence)
◦ At most 64 x 27 = 1728 faults
(tests)
◦ Takes 0.000001728 s on 1
GHz ATE
05-10-2019DrUshaMehta
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14. Causes of the Defects in Circuit
• Design Errors
• Verification process will catch it
• Fabrication Errors
• Wrong component
• Incorrect Wiring
• Fabrication Defects
• Imperfect Process Variations
• Physical Failure
• During life time of a system
05-10-2019DrUshaMehta
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15. Classifications of the Defects
• Permanent
• Intermittent
• During some intervals
• Transient
• One time only
05-10-2019DrUshaMehta
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16. Structural Testing
• Hardware components
• Defects in Hardware
• Its effect on output
• Complete list of all possible defects in given
circuits……
• The test which can prove the presence or absence
of the defect from given list
• Test set that can prove the presence or absence of
all possible defects from given list
05-10-2019DrUshaMehta
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18. Defects, Errors, Faults…..
• Defects: A defect in an electrical system is the unintended difference
between the implemented hardware and its intended design
• Process Defects:
• missing contact window, parasitic transistors, etc.
• Material Defect:
• bulk defects, material impurities etc
• Age Defects:
• Dielectric Breakdown, electromigration etc.
• Package Defects:
• contact degradation, seal leak etc.
• Errors
• A wrong output signal produced by a defective system is called an
error.
• An error is an effect whose cause is some defect.
• Faults
• A representation of a defect at the abstracted level is called a fault.
• The fault is imperfection in function while the defect is imperfection
in hardware.
05-10-2019DrUshaMehta
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19. Defects modeled as Faults
• Failure mode is used in reference to the
manifestation of a "defect" at the electrical level.
• Failure modes are modeled as faults at logic or
behavioral level of abstraction.
• At the logic level, failure mode can be interpreted in
different ways.
Physical defect
Physical model
05-10-2019DrUshaMehta
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20. Why Models?
Models
• are easier to work with
• are portable
• can be used for simulation so avoid h/w
requirement at early stage
• Nearly all engineering systems are studied
using models
• are used to bridge the gap between
physical reality and mathematical
abstraction
05-10-2019DrUshaMehta
20
21. Structural Fault Model
• Considering at gate level schematic….
• Let’s start with listing all possible faults
to be considered
• For gate level schematic, fault may be
in:
• components (i.e. gate)
• nets (i.e. connections)
• Let’s assume components are fault free
(not a good assumption?? but for a moment….let’s
assume, we will justify the assumption later on….. )
05-10-2019DrUshaMehta
21
22. • So the nets are only culprits…..
• The nets may be open or shorted with some other net
• Let’s focus on nets shorted with some other one else
and
• neglect net open for a while.
• Nets may be shorted with Vdd line, ground line or some
other active net.
• If net connected with some other net
• bridge fault
• Net connected to power line
• stuck-at-1 fault,
• Net connected to ground line
• stuck-at-0 line
05-10-2019DrUshaMehta
22
23. • We will consider bridge fault later on……..
• FOCUS ON STUCK-AT FAULTS ONLY
• For a given fault model with k different types of
faults that can occur at each of n different
potential fault sites,
• So for n nets, there are 3n-1 possible faulty
conditions to be considered separately for
stuck-at fault model.
• Prepare the list for
05-10-2019DrUshaMehta
23
24. Single Stuck at Fault (SSF)
• Let’s consider, there is only one stuck at fault at a time,
• Ignore multiple suck-at faults
• Considering only single stuck-at a time…..2n possible
faults
05-10-2019DrUshaMehta
24
25. Stuck-at Faults,
So classic, so legacy…
• Eldred (1959) – First use of structural testing
for the Honeywell Datamatic 1000 computer
• Galey, Norby, Roth (1961) – First publication of
stuck-at-0 and stuck-at-1 faults
• Seshu & Freeman (1962) – Use of stuck-faults
for parallel fault simulation
• Poage (1963) – Theoretical analysis of stuck-at
faults
05-10-2019DrUshaMehta
25
26. Stuck-at Faults:
Classical Faults
• Why stuck-at faults are considered as classical
faults?
• They are found capable to detect other type of faults
also.
• Relates to yield modeling
• Simple to use
05-10-2019DrUshaMehta
26
27. Stuck-At Faults
• Single Stuck-at fault
• Only one line is faulty at a time
• The faulty line is permanently stuck at either zero or
one
• Stuck at zero (s-a-0)
• Stuck-at-one (s-a-1)
05-10-2019DrUshaMehta
27
28. Example of single stuck-at fault
• Taking an example of an
AND gate as shown below:
Inputs
AB
True
Response
Faulty Response
A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
05-10-2019DrUshaMehta
28
29. Detectable Faults
• For any fault/faults to be detectable, the output must
have the different value compared to the error free
output. For digital function, if error free output is 1, the
erroneous output should be 0 and vice versa.
• Zf(t) /= Z(t) Zf(t) XOR Z(t) = 1
05-10-2019DrUshaMehta
29
30. Single Stuck At Fault
• Find the test vector for given fault,
1100 0T(1F)
05-10-2019DrUshaMehta
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32. Redundant/Undetectable Fault
• For which Zf(t) = Z(t)
• As redundant fault do not change the functionality
of circuit, should it be ignored?.....
05-10-2019DrUshaMehta
32
33. Try this for a s-a-1….
• Undetectable fault a s-a-1
05-10-2019DrUshaMehta
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34. For b s-a-0 ??
• b s-a-0 is detected by t=1101
05-10-2019DrUshaMehta
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35. Multiple faults
{ a s-a-1, b s-a-0}….
• In presence of a s-a-1 undetectable fault, b
is no longer detected by t=1101 but it is
detected by t=0X0X
05-10-2019DrUshaMehta
35
36. C s-a-1 is undetectable Z= AB, Zf=AB
A s-a-0 is detectable by 110
Fault {C s-a-1, a s-a-0} is undetectable.
05-10-2019DrUshaMehta
36
37. Effect of Undetectable Fault
• If f is detectable fault and g is an undetectable
fault, then f may become undetectable in presence
of g. Such a fault f is called a second generation
redundant fault.
• Two undetectable single faults f and g may become
detectable if simultaneously present.
05-10-2019DrUshaMehta
37
38. Why single stuck-at fault?
• If we consider multiple stuck at faults, we will
have to consider total 3n-1 possible fault. Even
for moderate n, the number of faults rises to a
large amount.
• Considering single-stuck at fault, this number
reduces to 2n.
• Further the single stuck-at fault gives a quite
good fault coverage nearly 99%.
• Frequent testing strategy
But frequent testing is not enough in following condition.
1. Some physical faults manifest as multiple faults in high density chips
2. Prior to first testing in newly manufactured chip, multiple faults can
exist
3. If testing experiment does not detect every fault, the circuit will contain
undetectable fault every time.
In most cases, a multiple fault can be detected by the tests designed
for the individual single faults that can compose the multiple one.
So single fault assumption is mostly adopted.
05-10-2019DrUshaMehta
38
39. Fault Equivalence
(by structural approach)
• Two faults of a Boolean circuit are called
equivalent iff they transform the circuit such
that the two faulty circuits have identical output
functions. Equivalent faults are also called
indistinguishable and have exactly the same set
of tests.
05-10-2019DrUshaMehta
39
40. Fault Equivalence
at Fan-out Branches
• The stuck-at fault on stem is equivalent to
multiple stuck-at fault on all branches. Prove
this.
• A
• X s-a-0, the test set is a1, x0, y1
• Y s-a-0, the test set is a1, x1, y0
• A s-a-0, the test set is a1, x0, y0
• X, Y, A s-a-0 are not equivalent but A s-a-0 is
equivalent to multiple fault {x s-a-0, y s-a-0}
X
Y
05-10-2019DrUshaMehta
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42. Fault Collapsing
• The input to output pass? or output to input pass?
• s-a-0 at d to keep or s-a-0 at e to keep or s-a-1 at g
to keep? Why?
• Input to output pass. Because the Boolean gate has
always single output and collapsing is not possible
for fanout. So no one has to choose one i/p from
multiple i/p. The selection of i/p can affect the
overall no. of fault reduction.
• Collapse Ratio = # of faults in collapsed fault set/ #
all faults
05-10-2019DrUshaMehta
42
44. Fault Dominance
• If all test of some fault f2 detects another
fault f1, then f1 is said to dominate f2. f1
is removed from fault list.
05-10-2019DrUshaMehta
44
45. Let’s Develop our own EDA tool for fault
equivalence…….
05-10-2019DrUshaMehta
45
46. • Express circuit at gate level as a program
consisting of interconnected logic operations
• External representation in the form of
netlist…ISCAS format, uv fomat, EDIF format…
• Execute the program on netlist to determine the
circuit output for varying input.
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50. Transistor (Switch) Faults
• MOS transistor is considered an ideal switch
and two types of faults are modeled:
• Stuck-open -- a single transistor is permanently
stuck in the open state.
• Stuck-short -- a single transistor is permanently
shorted irrespective of its gate voltage.
• Detection of a stuck-open fault requires two
vectors.
• Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ).
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51. Stuck-Open Fault
Two-vector s-op test
can be constructed by
ordering two s-at tests
A
B
VDD
C
pMOS
FETs
nMOS
FETs
Stuck-
open
1
0
0
0
0 1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1)
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53. Modelling of Open Faults
• Stuck open fault of a pMOS can be modelled as a s-a-1
fault at the corresponding input signal
• Stuck open fault of a nMOS can be modelled as a s-a-o
fault at the corresponding input signal
• One more reason why stuck-at are called classical
faults!!!
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56. Bridge Fault
• After single stuck-at
faults, bridge faults
are the most
important class of
faults.
• Most commonly
occurring type of
fault.
• Simplified model
assumes 0 resistance
(short) between two
lines (dotted line in
the figure)
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62. • Wired-AND
• y=0 --> x is s-a-0
• Test for bridge fault:
• Set y to 0 and test for x s-a-0 –or-
• Set x to 0 and test for y s-a-0
• Wired-OR
• y=1 --> x is s-a-1
• Test for bridge fault:
• Set y to 1 and test for x s-a-1 –or-
• Set x to 1 and test for y s-a-1
• Dominant driver
• x always outdrives y
• y always outdrives x
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63. Bridge Fault cont….
• Need to consider drive
strengths of bridged nodes to
determine voltage level.
• Gates driven by the bridged
nodes may interpret the
voltage level differently,
depending on their logic
threshold voltages.
• The faulty logic value depends
on:
• The relative strength of pull-
up and pull-down network
• The number of transistors
that are activated in
conflicting network
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65. Feedback Bridge Faults
• In a feedback bridge fault, there exists at least one path between the
two bridged nodes.
• The back line b is the line closest to the PI’s.
• The front line f is the line closest to the PO’s.
• AND:
• set b=0 and test for f s-a-0 (no logical feedback)
• set f=0 and test for b s-a-0, but not through f (i.e., f is not
sensitive to b).
• OR: ???
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66. IDDQ Testing
• It relies on measuring the supply current (Idd)
in the quiescent state (when the circuit is not
switching and inputs are held at static values).
The current consumed in the state is
commonly called Iddq for Idd (quiescent) and
hence the name.
• IDDQ testing refers to the integrated circuit
(IC) testing method based upon measurement
of steady state power-supply current.
• Iddq stands for quiescent Idd, or quiescent
power-supply current.
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67. IDDQ Testing cont….
• In case of a defect such as gate-oxide short or short
between two metal lines, a conduction path from power-
supply (Vdd) to ground (Gnd) is formed and
subsequently the circuit dissipates significantly high
current.
• This faulty current is a few orders of magnitude higher
than the fault-free leakage current.
• Iddq testing provides physical defect oriented testing
• SoCs contain huge number of transistors
• Summation of leakage current of all transistors becomes
too large to distinguish between faulty and fault-free
chips
• Most of the SoCs contain multiple power supplies
• Iddq testing is done on one power supply at a time
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69. IDDT testing
• When a CMOS circuit switches state, a momentary
path is established between the supply lines and
results in dynamic current IDDT
• IDDT exhibits spikes every time circuit switches. The
magnitude and frequency components of the
waveform depends upon switching activity.
• By observing the magnitude and frequency
spectrum of IDDT, addition diagnostic information
about possible defects unmatched with IDDQ and
other methods can be found.
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