This document discusses basic logic concepts used in ladder logic programming including gates, latch/unlatch coils, and processor status files. It introduces binary concepts and how gates like AND, OR, NOT, NAND, NOR, and XOR make decisions. Examples of gate circuits are shown in electromechanical and PLC/PAC ladder diagrams. Latch and unlatch coils are used to control outputs and the first scan bit is identified as a useful processor status address.

1. Chapter 03 Logic Concepts,
Latch/Unlatch, Intro to Processor
Status File
Basic logic concepts, Latch/Unlatch,
Set/Reset coils

2. The Binary Concept –
Multiple Input
 This two-state binary concept, applied to gates, can be
the basis for making decisions in ladder logic.
 The gate is a device that has one or more inputs and
one output.
 The gate will perform a logical decision based on the
status of its inputs and produce a result at its one output.

3. Using Gates to Make
Decisions
 The logical AND gate or function.
 All inputs must be true to obtain an output.
AND
Gate
Air Conditioner
Switch
Blower Switch
Cold Air
The automotive air conditioning to work,
the Air Conditioner must be turned on
and the Blower must be turned on.

4. Using Gates to Make
Decisions
 The logical OR gate or function.
 Any one input must be true to obtain an
output.
OR
Gate
Passenger
Door Switch
Driver Door
Switch
Dome Light
The automotive dome light will be on
when the passenger door OR the driver
door or both door switch(s) is activated.

5. The AND Function
 The AND function has two or
more inputs and one output.
The input signals are labeled
A, B, C, etc. and the output
signal is labeled Y.
 A binary 1 represents the
presence of a voltage (signal).
A binary 0 represents the
absence of voltage (no signal,
0 V or ground).
 Logic functions can be
represented using a truth table.
The truth table lists all possible
input status conditions with the
corresponding output status for
each set of input condition.
AND
Gate
A
B
YInputs
Output
Two input AND gate

6. An AND Gate Application
 An AND gate functions like switches in series.
 The light will only be ON when switch A AND
switch B are both closed.
AND
Gate
PB1 = 1
LT1 ON
PB2 = 1

7. The OR Function
 The OR function has two or
more inputs and one output.
The input signals are labeled
A, B, C, etc. and the output
signal is labeled Y.
 A binary 1 represents the
presence of a voltage
(signal). A binary 0
represents the absence of
voltage (no signal, 0 V or
ground).
 Logic functions can be
represented using a truth
table. The truth table lists all
possible input status
conditions with the
corresponding output status
for each set of input
condition.
OR
Gate
A
B
YInputs
Output
Two input OR gate

8. An OR Gate Application
 An OR gate functions like switches in parallel.
 The light will be ON when either or both switch A
OR switch B are closed.
OR
Gate
PB3 = 1
PB4 = 0
LT2 ON

9. The NOT Function
(Inverter)
 The NOT function gate,
also called an inverter,
has one input and one
output.
 The NOT gate functions
like its name states, it
inverts the input signal
status.
 If the input is a 1 the
output is a 0.
 If the input is a 0, the
output is a 1.
Input Input
A A
(not A)

10. A NOT Gate Application
 The NOT gate functions like a normally closed switch.
 The light will be ON if the switch is NOT being activated
and OFF when the switch IS being activated.
Input Input
PB5 PB5
(not PB5)

11. The NAND Function
 The NAND gate functions
like an AND gate with an
INVERTER on its output.
 The only time that the
output of a NAND gate is
a 0 is when all the inputs
are a binary 1.
NAND
Gate
PB6
PB7
Light
Two input NAND gate

12. The NOR Function
 The NOR gate functions
like an OR gate with an
INVERTER on its output.
 The only time that the
output of a NOR gate is a
1 is when all the inputs
are a binary 0.
NOR
Gate
PB8
PB9
LT5
Two input NOR gate

13. The XOR (Exclusive- OR)
Function
 The XOR gate has two
inputs and one output.
 The output of this gate is a 1
when the two inputs are
opposite to each other.
Therefore, one input a 1 and
the other a 0.
 The output of this gate is a 0
when both inputs are the
same, either two 0’s or two
1’s.
XOR
Gate
PB10
PB11
LT6

14. Important!
 When reading or designing PLC/PAC
ladder logic it’s not enough to only have
the PLC/PAC ladder logic. You MUST
know the status of the input field device(s).
 The circuits on the following slides will
help support this idea.
 While reading the following circuits,
remember how the I/O interacts with the
PLC/PAC instructions in memory.

15. AND Gate Circuits
AND
Gate
LS10
LS10A
SOL010Inputs
Output
Two input AND gate
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

16. OR Gate Circuits
OR
Gate
LS011
LS012
Sol011Inputs
Output
Two input OR gate
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

17. Combinations of Gates
OR
Gate AND
Gate
LS013
LS014 LT013
Inputs
Output
CR
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

18. Combination of Gates
AND
Gate
OR
Gate
OR
Gate
LS015
LS016
LT016Inputs
Output
CR01
CR02
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

19. Combination of Gates
AND
Gate
OR
Gate
LS017
LS031
AH017
Inputs Output
LS018
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

20. Combination of Gates
AND
Gate
OR
Gate
AND
Gate
PB019
PB020
LT019Inputs
Output
PB021
PB022
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

21. Why is this
instruction
programmed open?
Combination of Gates
AND
Gate
CR6
LS021
SOL021
Inputs Output
CR6
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram

22. Why are these
instruction
programmed open?
Combination of Gates
Electromechanical Ladder Diagram
PLC/PAC Ladder Diagram
This is an XOR circuit

23. Combination of Gates
AND
Gate
OR
Gate
A
B
M
Inputs
Output
C
D
Electromechanical Ladder Diagram
Draw the PLC/PAC
ladder diagram
for this logic

24.  Latch coils – Output Latched (OTL) instructions energize when the
rung containing the OTL is true and will stay energized when the
rung goes false.
 Unlatch coils – Output Unlatch (OTU) instructions will unlatch or
de-energize an OTL instruction having the same address as the
OTU when the rung containing the OTU becomes true.
 If the OTU instruction remains true the OTL instruction with the
same address will never energize.
 The OTU instruction can turn off any bit in the processor memory
that is set to a logic 1.
 OTL and OUT instructions use tags of data type BOOL.
Latch/Unlatch Coils –
ControlLogix

25.  The Siemens Set/Reset output instruction
work exactly the same as the AB
OTL/OTU instructions but they are called;
Set (S) and Reset (R)
Latch/Unlatch Coils –
Siemens

26.  The Creative Components Workbench (CCW)
Set/Reset output instruction work exactly the same
as the AB OTL/OTU instructions and the Siemens
Set (S) and Reset (R). These are also called Set
(S) and Reset (R).
 The Set/Reset instructions conform to the IEC
61131-3 standard.
Latch/Unlatch Coils –
CCW

27.  Obtaining the process status in a
ControlLogix processor is an advance
topic and will not be discussed in this
course.
 A few status bits will be discussed when
needed.
Processor Status –
ControlLogix

28.  Obtaining the process status in a Siemens
processor is an advance topic and will not
be discussed in this course.
 Any status required will be discussed
when needed.
Processor Status – Siemens

29. Useful Status File Addresses
(ControlLogix)
 The following status file address will be
useful for this and many labs in the
PLC/PAC courses:
 S:FS – First Scan Bit
 This bit will be set to a logic ‘1’ at the beginning of
the very first scan of the program. At the beginning
of the next scan this bit will reset to a logic ‘0’ and
will not set to a logic ‘1’ again until the processor is
switched from PROG mode to RUN mode.
 This is the tag for the First Scan Bit. It cannot be
picked from a tag list and must be manually typed
into the instruction tag field.

30. Useful Status File Addresses
(CCW)
 The following status file address will be
useful for this and many labs in the
PLC/PAC courses:
 _SYSVA_FIRST_SCAN – First Scan Bit
 This bit will be set to a logic ‘1’ at the beginning of
the very first scan of the program. At the beginning
of the next scan this bit will reset to a logic ‘0’ and
will not set to a logic ‘1’ again until the processor is
switched from PROG mode to RUN mode.
 This is the tag for the First Scan Bit. It can be
picked from a tag list.