The document discusses various logic gates and flip flops. It begins by explaining the AND, OR, and NOT gates as the fundamental logic gates. It then discusses the JK flip flop, explaining its operation and how it can be used to create counters. It also briefly discusses the SR flip flop and D flip flop. The document provides truth tables and diagrams to illustrate the working of these logic components.

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Logic Design
BT0064 Paper-1
By Milan K Antony

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1. Convert the following binary numbers to base 10.
a. 10101101 = 173
b. 110110.1 = 54.1
2. How AND gate can be realized using NOR gate?
The NOR gate can also be classed as a "Universal"
type gate. NOR gates can be used to produce any other type
of logic gate function just like the NAND gate and by
connecting them together in various combinations the three
basic gate types of AND function can be formed using only
NOR's, for example.

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3. Simplify the following three-variable Boolean functions
algebraically:
a. f = 1,2,5,6∑
b. f = 0,1,2,3∑
4. Draw the circuit for 3-to-8 line decoder.
5. Write a short note on J-K Master Slave Flip-Flop.
The Master-Slave Flip-Flop is basically two JK bistable flip-
flops connected together in a series configuration with the
outputs from Q and Q from the "Slave" flip-flop being fed
back to the inputs of the "Master" with the outputs of the

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"Master" flip-flop being connected to the two inputs of the
"Slave" flip-flop as shown below.
Master-Slave JK Flip-Flops
The input signals J and K are connected to the "Master" flip-
flop which "locks" the input while the clock (Clk) input is high
at logic level "1". As the clock input of the "Slave" flip-flop
is the inverse (complement) of the "Master" clock input, the
outputs from the "Master" flip-flop are only "seen" by the
"Slave" flip-flop when the clock input goes "LOW" to logic
level "0". Therefore on the "High-to-Low" transition of the
clock pulse the locked outputs of the "Master" flip-flop are
fed through to the JK inputs of the "Slave" flip-flop making
this type of flip-flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is
"HIGH", and passes the data to the output on the falling-
edge of the clock signal. In other words, the Master-Slave
JK Flip-flop is a "Synchronous" device as it only passes data
with the timing of the clock signal.

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6. Convert the following decimal numbers to base 2:
a. 122 = (1111010)
b. 98 = (1100010)
7. List the fundamental logical gates.
While each logical element or condition must always have a logic
value of either "0" or "1", we also need to have ways to
combine different logical signals or conditions to provide a
logical result.
For example, consider the logical statement: "If I move the
switch on the wall up, the light will turn on." At first glance,
this seems to be a correct statement. However, if we look at
a few other factors, we realize that there's more to it than
this. In this example, a more complete statement would be:
"If I move the switch on the wall up and the light bulb is
good and the power is on, the light will turn on."
If we look at these two statements as logical expressions and
use logical terminology, we can reduce the first statement to:
Light = Switch
This means nothing more than that the light will follow the
action of the switch, so that when the switch is up/on/true/1

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the light will also be on/true/1. Conversely, if the switch is
down/off/false/0 the light will also be off/false/0.Looking at
the second version of the statement, we have a slightly more
complex expression:Light = Switch and Bulb and PowerNormally,
we use symbols rather than words to designate the and
function that we're using to combine the separate variables of
Switch, Bulb, and Power in this expression. The symbol normally
used is a dot, which is the same symbol used for multiplication
in some mathematical expressions. Using this symbol, our
three-variable expression becomes:Light = Switch Bulb
PowerWhen we deal with logical circuits (as in computers), we
not only need to deal with logical functions; we also need
some special symbols to denote these functions in a logical
diagram. There are three fundamental logical operations, from
which all other functions, no matter how complex, can be
derived. These functions are named and, or, and not. Each of
these has a specific symbol and a clearly-defined behavior, as
follows:
The AND Gate
The AND gate implements the AND
function. With the gate shown to
the left, both inputs must have
logic 1 signals applied to them in
order for the output to be a logic
1. With either input at logic 0, the
output will be held to logic 0.

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If your browser supports the
Javascript functions required for
the demonstrations built into this
page, you can click the buttons to
the left of the AND gate drawing
to change their assigned logic
values, and the drawing will change
to reflect the new input states.
Other demonstrations on these
pages will work the same way.
There is no limit to the number of
inputs that may be applied to an
AND function, so there is no
functional limit to the number of
inputs an AND gate may have.
However, for practical reasons,
commercial AND gates are most
commonly manufactured with 2, 3,
or 4 inputs. A standard Integrated
Circuit (IC) package contains 14 or
16 pins, for practical size and
handling. A standard 14-pin
package can contain four 2-input
gates, three 3-input gates, or two
4-input gates, and still have room
for two pins for power supply

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connections.
The OR Gate
The OR gate is sort of the reverse
of the AND gate. The OR
function, like its verbal
counterpart, allows the output to
be true (logic 1) if any one or
more of its inputs are true.
Verbally, we might say, "If it is
raining OR if I turn on the
sprinkler, the lawn will be wet."
Note that the lawn will still be wet
if the sprinkler is on and it is also
raining. This is correctly reflected
by the basic OR function.
In symbols, the OR function is
designated with a plus sign (+).
In logical diagrams, the symbol to
the left designates the OR gate.
As with the AND function, the OR
function can have any number of
inputs. However, practical
commercial OR gates are mostly
limited to 2, 3, and 4 inputs, as

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with AND gates.
The NOT Gate, or Inverter
The inverter is a little different
from AND and OR gates in that it
always has exactly one input as well
as one output. Whatever logical
state is applied to the input, the
opposite state will appear at the
output.
The NOT function, as it is called,
is necesasary in many applications
and highly useful in others. A
practical verbal application might
be:
The door is NOT locked = You may
enter
The NOT function is denoted by a
horizontal bar over the value to be
inverted, as shown in the figure to
the left. In some cases a single
quote mark (') may also be used
for this purpose: 0' = 1 and
1' = 0. For greater clarity in some

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logical expressions, we will use the
overbar most of the time.
In the inverter symbol, the triangle
actually denotes only an amplifier,
which in digital terms means that it
"cleans up" the signal but does not
change its logical sense. It is the
circle at the output which denotes
the logical inversion. The circle
could have been placed at the
input instead, and the logical
meaning would still be the same.
The logic gates shown above are used in various combinations
to perform tasks of any level of complexity. Some functions
are so commonly used that they have been given symbols of
their own, and are often packaged so as to provide that
specific function directly. On the next page, we'll begin our
coverage of these functions.
By combining thousands or millions of logic gates, it is possible
to perform highly complex operations. The maximum number of
logic gates on an integrated circuit is determined by the size
of the chip divided by the size of the logic gates. Since
transistors make up most of the logic gates in computer

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processors, smaller transistors mean more complex and faster
processors.Minimize the following functions using the ‘don’t
care’ terms for simplification wherever possible:
a. f(A,B,C) = 3,5 with don’t care term 0,7∑
b. f(A,B,C,D) = 1,2,3,4,5,6,7,8,9,10 with ‘don’t care’ terms∑
9, 12, 15
9. Design full-adder using only NOR gates.
First of all, NAND and NOR gates have been proven to be
logically complete. That means you can create every other
logical gate with just NANDs or just NORs. Other gate
functions are XOR, AND, OR, NOT, etc.
To clarify: The notation I am using is [NAND] represents the
NAND gate. Having A,B means the two inputs are A and B. If
there is just one input, then that input gets mapped to both
inputs. The '|' is supposed to show a junction between two
lines. '-' is a single line and '=' is a double line. The
'. . .' is just empty space, trying to keep the diagram
intact.
Some NAND designs we will need are:
AND: A,B--[NAND]==[NAND]-->out
OR: A--[NAND]--|==[NAND]--out

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. . . .B--[NAND]--|
first NAND connects to top and bottom NANDs
last NAND has inputs taken from output of the middle two
NANDs
. . . . . . . . . . . . . . . A--|[NAND]---|
XOR: A,B--[NAND]------| . . . . . . . |===[NAND]--out
. . . . . . . . . . . . . . . B--|[NAND]---|
The second part is what a full adder is. A full adder is a
system that takes in three signals and outputs two. The three
input signals are A, B, and Cin. The two outputs are S and
Cout. The point of a full adder is that you can cascade them.
The Cout of the first becomes the Cin of the second. That
way you have a general one bit adder, but can make an N bit
adder by stringing cascading them. So the first step in
creating a full adder is writing out the truth table, a table
where inputs get mapped to specific outputs. I am going to
use '-' in place of spaces so the spacing stays the same
after I post.
Input- - - - - - - - - - - - - - - -Output
A - - B - - Cin - - - - - - - - - S - - Cout
0 - - 0 - - 0 - - - - - - - - - - -0 - - 0
0 - - 0 - - 1 - - - - - - - - - - -1 - - 0
0 - - 1 - - 0 - - - - - - - - - - -1 - - 0

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0 - - 1 - - 1 - - - - - - - - - - -0 - - 1
1 - - 0 - - 0 - - - - - - - - - - -1 - - 0
1 - - 0 - - 1 - - - - - - - - - - -0 - - 1
1 - - 1 - - 0 - - - - - - - - - - -0 - - 1
1 - - 1 - - 1 - - - - - - - - - - -1 - - 1
It can be seen that S = [A XOR B XOR Cin]
It can be seen that C = [(A AND B) OR (A AND Cin) or (B
AND Cin)]
or equivelently (and more efficiently) C = [(A AND B) or (C
AND (A XOR B))]
10. Draw and explain the working of JK, S-R, and D flip
flops.
In The J-K Flip-Flop
This diagram, P stands for "Preset," C stands for "Clear"
and Clk stands for "Clock." The logic table looks like this:
P C Clk J K Q Q'
1 1
1-
to-
0
1 0 1 0
1 1 1- 0 1 0 1

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to-
0
1 1
1-
to-
0
1 1
Togg
les
1 0 X X X 0 1
0 1 X X X 1 0
Here is what the table is saying: First, Preset and Clear
override J, K and Clk completely. So if Preset goes to 0,
then Q goes to 1; and if Clear goes to 0, then Q goes to
0 no matter what J, K and Clk are doing. However, if
both Preset and Clear are 1, then J, K and Clk can
operate. The 1-to-0 notation means that when the clock
changes from a 1 to a 0, the value of J and K are
remembered if they are opposites. At the low-going edge
of the clock (the transition from 1 to 0), J and K are
stored. However, if both J and K happen to be 1 at the
low-going edge, then Q simply toggles. That is, Q changes
from its current state to the opposite state.
You might be asking yourself right now, "What in the world is
that good for?" It turns out that the concept of "edge
triggering" is very useful. The fact that J-K flip-flop only
"latches" the J-K inputs on a transition from 1 to 0 makes it
much more useful as a memory device. J-K flip-flops are
also extremely useful in counters (which are used extensively

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when creating a digital clock). Here is an example of a 4-bit
counter using J-K flip-flops:
The outputs for this circuit are A, B, C and D, and they
represent a 4-bit binary number. Into the clock input of the
left-most flip-flop comes a signal changing from 1 to 0 and
back to 1 repeatedly (an oscillating signal). The counter will
count the low-going edges it sees in this signal. That is,
every time the incoming signal changes from 1 to 0, the 4-bit
number represented by A, B, C and D will increment by 1. So
the count will go from 0 to 15 and then cycle back to 0. You
can add as many bits as you like to this counter and count
anything you like. For example, if you put a magnetic switch
on a door, the counter will count the number of times the
door is opened and closed. If you put an optical sensor on a
road, the counter could count the number of cars that drive
by.
Another use of a J-K flip-flop is to create an edge-
triggered latch, as shown here:

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In this arrangement, the value on D is "latched" when the
clock edge goes from low to high. Latches are extremely
important in the design of things like central processing units
(CPUs) and peripherals in computers.
SR Flip-Flop
An SR Flip-Flop can be considered as a basic one-bit memory
device that has two inputs, one which will "SET" the device and
another which will "RESET" the device back to its original state
and an output Q that will be either at a logic level "1" or
logic "0" depending upon this Set/Reset condition. A basic
NAND Gate SR flip flop circuit provides feedback from its
outputs to its inputs and is commonly used in memory circuits
to store data bits. The term "Flip-flop" relates to the actual
operation of the device, as it can be "Flipped" into one logic
state or "Flopped" back into another.
The simplest way to make any basic one-bit Set/Reset SR
flip-flop is to connect together a pair of cross-coupled 2-
input NAND Gates to form a Set-Reset Bistable or a SR

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NAND Gate Latch, so that there is feedback from each output
to one of the other NAND Gate inputs. This device consists
of two inputs, one called the Reset, R and the other called
the Set, S with two corresponding outputs Q and its inverse or
complement Q as shown below.
The SR NAND Gate Latch
D flip flops
The edge-triggered D flip-flop is easily derived from its RS
counterpart. The only requirement is to replace the R input
with an inverted version of the S input, which thereby becomes
D. This is only needed in the master latch section; the slave
remains unchanged.
One essential point about the D flip-flop is that when the
clock input falls to logic 0 and the outputs can change state,
the Q output always takes on the state of the D input at the
moment of the clock edge. This was not true of the RS and
JK flip-flops. The RS master section would repeatedly change
states to match the input signals while the clock line is logic 1,
and the Q output would reflect whichever input most recently

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received an active signal. The JK master section would receive
and hold an input to tell it to change state, and never change
that state until the next cycle of the clock. This behavior is
not possible with a D flip-flop.
The edge-triggered D NAND flip-flop is shown below.