This document discusses different circuit design techniques for combinational logic, including: 1. Pseudo-nMOS circuits which use a permanently on pMOS transistor but have static power consumption issues. 2. Cascode Voltage Switch Logic seeks the performance of pseudo-nMOS without static power draw but requires input complements. 3. Pass transistor logic uses only two transistors but output levels are not restored perfectly and cannot drive other gates directly.

1. Design and Implementation of VLSI Systems
(EN1600)
Lecture 20: Combinational Circuit Design (2/3)
S. Reda EN160 SP’08

2. Let’s get rid of pMOS
 Reduced the capacitance and improved the delay
 Increased static power consumption
Implementing a large resistive load in CMOS is not readily available
[see subsection 2.5.4]
S. Reda EN160 SP’08

3. 2. Pseudo-nMOS circuits
• Use a pull-up transistor that is always ON
• Issues:
– Ratio or relative strength
– Make pMOS about ¼ effective strength of pulldown network
[see subsection 2.5.4]
S. Reda EN160 SP’08

4. Logical effort of pseudo-nMOS gates
• Design for unit current on output to compare with unit inverter.
• pMOS fights nMOS
• psuedo-nMOS is slower on the average than CMOS but it works
well for wide NOR gates
logical effort independent of
number of inputs!
S. Reda EN160 SP’08

5. Pseudo-nMOS power
en
Y
A B C
• Pseudo-nMOS draws power whenever Y = 0
– Called static power P = I•VDD
– A few mA / gate * 1M gates would be a problem
– This is why nMOS went extinct!
• Use pseudo-nMOS sparingly for wide NORs
• Turn off pMOS when not in use
S. Reda EN160 SP’08

6. Ganged CMOS
Traditional pseudo-nMOS
• When A=B=0:
• both pMOS turn on in parallel pulling the output high fast
• When both inputs are ‘1’:
• both pMOS transistors turn off saving power over psuedo-nMOS
• When one is ‘1’ or one is ‘0’ then it is just like the pseudo-nMOS case
S. Reda EN160 SP’08

7. 3. Cascode Voltage Switch Logic (CVSL)
• Seeks the performance of pseudo-nMOS without the static power
consumption
• CVSL disadvantages:
– Require input complement
– NAND gate structures can be tall and slow
S. Reda EN160 SP’08

8. 4. Pass Transistor Logic
B
A
B
F = AB
0
Advantage:
• just uses two transistors
Problem:
• ‘1’ is not passed perfectly
• cannot the output to the input of another gate
S. Reda EN160 SP’08

9. Complementary Pass Transistor Logic (CPTL)
A
Pass-Transistor
A F
B Network
B
(a)
A Inverse
A Pass-Transistor F
B
B Network
B B B B B B
A A A
B F=AB B F=A+B A F=A ⊕Β
A A A (b)
B F=AB B F =A+B A F=A ⊕Β
AND/NAND OR/NOR EXOR/NEXOR
• Complementary data inputs and outputs are available
• Very suitable for XOR realization (compare to traditional CMOS)
• Interconnect overhead to route the signal and its complement
S. Reda EN160 SP’08

10. Possible solution: interface to a CMOS inverter
3.0
In
In
1.5µ m/0.25 µm Out
Voltage [V]
2.0
VD D x x
Out
0.5 µ m/0.25µ m
1.0
0.5µ m/0.25 µm
0.00 0.5 1 1.5 2
Time [ns]
Threshold voltage loss causes static power consumption
V DD
V DD
Level Restorer
Mr (AKA Lean Integration
B
M2 with Pass Transistors
A Mn
X
Out
- LEAP)
M1
A better design: full swing; reduces static power
S. Reda EN160 SP’08

11. Pass Transistor Logic with transmission gates
• In pass-transistor circuits, inputs are also applied to the
source/drain terminals.
• Circuits are built using transmission gates.
Problem:
• Non-restoring logic.
• Traditional CMOS “rejuvenates” signals
S. Reda EN160 SP’08

12. Restoring Pass Transistor Logic
VDD
S
A
M2
S F
M1
B
S
S. Reda EN160 SP’08

13. Circuit Families
 Static CMOS
 Ratioed Circuits
 Cascode Voltage Switch Logic
 Pass-transistor Circuits
 Dynamic Circuits
S. Reda EN160 SP’08