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Layouts
The document discusses layout design rules in semiconductor manufacturing, highlighting their role in defining the relationship between various circuit features, particularly in field-effect transistors. It outlines different approaches to design rules, such as micron rules and lambda-based rules, explaining their advantages and disadvantages in terms of feature sizes, spacing, and process control. Additionally, it provides specific design rules for different layers including metal, diffusion, and polysilicon, aimed at avoiding issues such as shorts and ensuring compatible circuit designs.
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Layouts
- 1. LAYOUTS By: Sudhanshu Janwadkar, TA, SVNIT(March 14&17th, 2017)
- 2. Layout designrules describe how small features can be and how closely they can be reliably packed in a particular manufacturing process. Layout design rules act as Interface between designer and process engineer Why we use design rules?
- 3. Historically, theprocess technology referred to the length of the channel between the source and drain terminals in field effect transistors. The sizes of other features are generally derived as a ratio of the channel length, where some may be larger than the channel size and some smaller. For example, in a 90 nm process, the length of the channel may be 90 nm, but the width of the gate terminal may be only 50 nm. Why we use design rules?
- 4. Transistor Sizes overthe years Year Feature Size 1971 10 µm 1974 6 µm 1985 1 µm 1995 350 nm 1999 180 nm 2004 90 nm 2008 45 nm 2010 32 nm 2012 22 nm 2014 14 nm 2017 10 nm 2019 7 nm 2021 5 nm Feature Size = l = 0.5 X (channel length)
- 5. Hence , thelayouts Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon Interface between circuit designer and fabrication engineer
- 6. Design rulesdefine ranges for features Examples: min. wire widths to avoid breaks min. spacing to avoid shorts minimum overlaps to ensure complete overlaps Required for resolution/tolerances of masks Fabrication processes defined by minimum channel width What are design Rules?
- 7. Two majorapproaches: “Micron” rules: stated at micron resolution absolute dimensions l rules: Simplified micron rules with limited scaling attributes. Scalable design rules: lambda parameter Design Rules?
- 8. All minimumsizes and spacing specified in microns. Rules don't have to be multiples of λ. Can result in 50% reduction in area over λ based rules. Disadvantage: Migrating from one process to a more advanced process or a different foundry’s process difficult because not all rules scale in the same way. Micron Rules
- 9. Lambda-based (scalableCMOS) design rules define scalable rules based on l (which is half of the minimum channel length) Lambda Based Design Rules
- 10. Circuit designerin general want tighter, smaller layouts for improved performance and decreased silicon area. –Advantage of Micron Rules On the other hand, the process engineer wants design rules that result in a controllable and reproducible process. - Advantage of Lambda Based Rules Generally we find there has to be a compromise for a competitive circuit to be produced at a reasonable cost. In l rules, All widths, spacing, and distances are written in the form l = 0.5 X minimum drawn transistor length Lambda Based Design Rules
- 11. Features: Design rulesbased on single parameter, λ Simple for the designer Wide acceptance Provide feature size independent way of setting out mask If design rules are obeyed, masks will produce working circuits Minimum feature size is defined as 2 λ Used to preserve topological features on a chip Prevents shorting, opens, contacts from slipping out of area to be contacted Lambda Based Design Rules
- 12. Ease oflearning because they are scalable, portable, durable Longevity of designs that are simple, abstract and minimal clutter Automatic translation to final layout Advantages of Generalised Design Rules
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- 14. Rule for MetalLayer Metal Layers have Minimum width and Spacing of 4l. Lambda Based Design Rules
- 15. Rule for DiffusionLayers ((p-diff) / (n-diff)) Diffusion Layers have Minimum width and Spacing of 4l. Lambda Based Design Rules
- 16. Rule for PolysiliconLayer Polysilicon Layers have Minimum width of 2l. And the Minimum Spacing between two Poly Si must be 3l Lambda Based Design Rules
- 17. Rule for ContactCuts Contacts are 2l × 2 l and must be surrounded by 1l on the layers above and below Lambda Based Design Rules The Shaded portion is the contact, has overlapped area 2l X 2l The Contact is to be surrounded by 1l of the Diffusion/Poly Si Layer on all the four sides
- 18. Rule forSpacing between Contact Cuts Contacts have a spacing of 3 l from other contacts. Lambda Based Design Rules
- 19. Rule for Spacingbetween Poly Si and Diffusion Layers Polysilicon overlaps diffusion by 2 l when a transistor is desired Lambda Based Design Rules Contact: Overlap 4l X 4l Surround the contact by l on all sides Poly Si Overlaps Diffusion by 2l, transistor is formed Contact: Overlap 4l X 4l Surround the contact by l on all sides
- 20. Rule for Spacingbetween Poly Si and Diffusion Layers Polysilicon has a spacing of 1 l away from diffusion where no transistor is desired. Lambda Based Design Rules
- 21. Rule for N-Well N-well surrounds pMOS transistors by 6 l and avoids nMOS transistors by 6 l Lambda Based Design Rules The minimum separation between N-Well surrounding pMOS and nMOS is 6l The shaded region represents N- Well. A minimum of 6l spacing surrounding pMOS on all four sides should be provided
- 22. Rule for Spacingbetween NMOS & PMOS The Minimum space between nMOS and pMOS should be 12l Lambda Based Design Rules N-Well surrounds pMOS by 6l + Min space between N-Well and nMOS 6l =12l Follows from Rules on metal layer width and spacing
- 23. Minimum widthof PolySilicon 2l Minimum width of diffusion line 4l Minimum width of Metal line 4l as metal lines 2l Metal Diffusion Polysilicon 4l 4l Lambda Based Design Rules
- 24. PolySi –PolySi space 3l Metal - Metal space 4l Diffusion – Diffusion space 3l 3l Metal Diffusion Polysilicon 4l 4l Lambda Based Design Rules
- 25. Diffusion –PolySi space l To prevent the lines overlapping to form unwanted capacitor Metal lines can pass over both diffusion and polySi without electrical effect. Where no separation is specified, metal lines can overlap or cross l Metal Diffusion Lambda Based Design Rules Polysilicon
- 26. Metal linescan pass over both diffusion and polySi without electrical effect It is recommended practice to leave l between a metal edge and a polySi or diffusion line to which it is not electrically connected l Metal Polysilicon Lambda Based Design Rules
- 27. • Metal connectsto polySi/diffusion by contact cut. • Contact area: 2 l X 2 l • Metal and polySi or diffusion must overlap this contact area by l so that the two desired conductors encompass the contact area despite any mis-alignment between conducting layers and the contact hole 4l Contact Cut Lambda Based Design Rules
- 28. Contact Cut • Contactcut – any gate: 2 l apart • Why? No contact to any part of the gate. 4l 2l Lambda Based Design Rules
- 29. Contact Cut • Contactcut – contact cut: 3 l apart • Why? To prevent holes from merging. 3l Lambda Based Design Rules
- 30. Lambda Based DesignRules : Summary
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- 32. n+ n+ n+n+ p+ p+ p+ p+ NMOS NMOS PMOS PMOS n-well Layout
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- 34. A B C yx y x AB C Layout: MOS Array
- 35. x y A B X XX A B x y A B y X X X X x A B y Layouts: Parallel MOSFETs
- 36. • Both thepower supply and ground are routed using the Metal layer • n+ and p+ regions are denoted using the same fill pattern. The only difference is the n-well • Contacts are needed from Metal to n+ or p+ Layout : Basic Approach
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- 42. Gnd Vp ba a b X Vp Gnd X X XX a b ba CMOS NOR Gate
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- 44. UNIT – IICIRCUIT DESIGN PROCESSES 3-input NAND 3- Input CMOS NAND Gate
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- 46. 1. The electricalgate design must be completed by checking the followings: a. Right power and ground supplies b. Noise at the gate input c. Faulty connections and transistors d. Improper ratios e. Incorrect clocking and charge sharing 2. VDD and the VSS lines run at the top and the bottom of the design 3. Vertical poysilicon for each gate input 4. Order polysilicon gate signals for maximal connection between transistors 5. The connectivity requires to place NMOS close to VSS and PMOS close to VDD 6. Connection to complete the logic must be made using poly, metal and even metal2 General Layout Guidelines
- 47. • Efficient routingspace usage. They can be placed over the cells or even in multiple layers. • Source drain connections must be merged better. • White (blank) spaces must be minimum. • The devices must be of optimum sizes. • Transparent routing can be provided for cell to cell interconnection, this reduces global wiring problems General Layout Guidelines