This document discusses various datapath subsystems used in VLSI systems, including adders, multipliers, comparators, counters, and shifters. It focuses on adders, describing how a basic N-bit carry-ripple adder works and its drawbacks. Optimized adder designs are then presented, including a mirror adder that reduces area and propagation delay by exploiting the self-dual property of full adders. Faster ripple carry adders can also be created by minimizing the critical carry path using modified full adder cells without inverters in the carry path.

1. Design and Implementation of VLSI Systems
(EN1600)
Lecture 25: Datapath Subsystems 1/4
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2. Datapath Subsystems
 Adders
 Multipliers
 Comparators
 Counters
 Shifters
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3. Adders
Addition is the most commonly
used arithmetic operation
→ could be speed limiting
→ optimization of the adder is
of the utmost importance
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4. A N-bit carry-ripple adder can be
constructed by cascading 1-bit FA
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 Co,0 Co,1 Co,2
FA FA FA FA
(= Ci,1)
S0 S1 S2 S3
Worst case delay linear with the number of bits
td = O(N)
tadder = (N-1)tcarry + tsum
Goal: Make the fastest possible carry path circuit
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5. Full adder Boolean equations
A B
S = A⊕ B ⊕C Full
Cin Cout
Cout = MAJ ( A, B, C ) adder
Sum
S = A ⊕ B ⊕ Ci
= ABC i + ABC i + ABCi + ABCi
C o = AB + BCi + AC i
S can be factored to reuse the Co term
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6. An implementation that requires 28 transistors
VDD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A
Ci
A B B VDD
A B Ci A
Co B
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7. Problems with the design VDD
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A
Ci
A B B VDD
A B Ci A
Co B
Problems: Note
• Large area • Ci is connected to the transistor
• Tall transistor stacks
closest to the output
• Large intrinsic capacitance for Co
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8. Self-dual property of FAs
A. A full adder receiving
complementary inputs
produce complementary
outputs
B. An inverting full adder receiving
complementary inputs produce
true outputs
A B A B
Self duality enables two
optimizations: Ci FA Co Ci FA Co
B.PGK mirror FA
C.Faster ripple carry
adder S S
S ( A, B, C i ) = S ( A, B , C i )
C ( A, B, C ) = C ( A, B , C )
o i o i
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9. A. PGK mirror FA design
• For a full adder, define what happens to carry
– Generate: Cout = 1 independent of C
• G=A•B
– Propagate: Cout = C
• P=A⊕B
– Kill: Cout = 0 independent of C
• K = ~A • ~B
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10. A. The mirror adder
VDD
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
 Still need two B
inverters to • Less area
generate Co and • Shorter stacks
S
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• Less intrinsic capacitance

11. A. Mirror adder stick diagram
VDD
A B Ci B A Ci Co Ci A B
Co
S
GND
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12. B. Minimize critical path (carry) by reducing
the number of inverters along the path
Even cell Odd cell
A0 B0 A1 B1 A2 B2 A3 B3
Ci,0 , Co,0 , Co,1 , Co,2 , Co,3
FA FA FA FA
S0 S1 S2 S3
• FA’ is a FA without the inverter in the carry path
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