This document compares the use of complementary pass-transistor logic (CPL) to conventional CMOS design. CPL uses fewer transistors than CMOS gates, has smaller capacitances, and is faster. A 2:1 multiplexer is designed using both CMOS and CPL in Microwind and DSCH2 layout tools. Simulation results show the CPL multiplexer has lower power consumption, smaller area, faster rise/fall delays compared to the CMOS multiplexer. Therefore, CPL offers advantages over conventional CMOS in terms of speed, area, and power-delay products.

1. Presented by-:
Diwaker Pant
ME ECE Regular

2.  IntroductIon.
 AdvAntAges of usIng pAss trAnsIstor logIcs As
compAred to conventIonAl cmos logIc.
 lAb work relAted to pAss trAnsIstor logIc.
 conclusIons.
Pass Transistor Logic October 9, 2012 2

3.  In electronics pass transistor logic (PTL) describes
several logic families used in the design of integrated
circuits.
 It reduces the count of transistors used to make
different logic gates, by eliminating redundant
transistors.
 Disadvantage that output levels are always lower than
the input level.
Pass Transistor Logic October 9, 2012 3

4.  In conventional logic families input is applied to gate
terminal of transistor but in PTL it is also applied to
source /drain terminal.
 These circuits act as switches use either NMOS
transistors or parallel pair of NMOS and PMOS
transistor called Transmission gate.
 Here the width of PMOS is taken equal to NMOS so
that both transistors can pass the signal
simultaneously in parallel.
Pass Transistor Logic October 9, 2012 4

5.  nMOS passes g=1 input ‘0’
Output Strong ‘0’
g g=1 input ‘1’
• strong ‘ 0’ Output weak ‘1’
• Weak ‘ 1 s d
 pMOS passes g=0 input ‘0’
Output weak ‘0’
g
• Strong ‘ 1’ g=0 input ‘1’
s d Output strong ‘1’
• Weak ‘ 0’
Pass Transistor Logic October 9, 2012 5

6.  pAss trAnsIstor logIc
g g=0, gb=1 g=1, gb=0
Switch is open Switch is closed
a b So when g=1
If input is ‘ 0’ then output will be
strong ‘ 0’ .
gb
If input is ‘ 1’ then output will be
strong ‘ 1’
Pass Transistor Logic October 9, 2012 6

7.  Fewer devices to implement the logical functions as
compared to CMOS.
 Example AND gate.
When B is “ 1” , top device
turns on and copies the input
A to output F.
When B is low, bottom device
turns on
and passes a “ 0” .
Pass Transistor Logic October 9, 2012 7

8.  Some logical circuits using PTL
Pass Transistor Logic October 9, 2012 8

10. This paper compares the use of complementary pass-transistor
logic (CPL) as more power-efficient than conventional CMOS
design. However, new comparisons performed on more efficient
CMOS circuit realizations and demonstrate CPL to be superior
to conventional CMOS in most cases with respect to speed,
area, and power-delay products. This is basically explained by
the fact that CPL gates uses less transistors, have smaller
capacitances, and are faster than gates in complementary
CMOS. In this paper 2:1 Multiplexer is designed using the
conventional CMOS design and CPL logic design and the
results are compared using Microwind and DSCH2 CMOS
layout tools.
October 9, 2012 Pass Transistor Logic 10

11.  VLSI (Very large scale integration) implementation.
 Major problems are heat dissipation and power consumptions.
 Solutions have been proposed to decrease the power supply
voltage, switching frequency and capacitance of transistor.
 2:1 MUX by using CMOS and CPL on MICROWIND/
DSCH2.
October 9, 2012 Pass Transistor Logic 11

12.  Any logic function can be realized by NMOS pull-down and
PMOS pull-up networks connected between the gate output
and the power lines.
Fig. 1 Schematic of 2:1 MUX using CMOS Logic in DSCH2
October 9, 2012 Pass Transistor Logic 12

13.  Timing operation performed on 2:1 MUX conventional
CMOS logic design, the rise delay and fall delay calculated is
0.012 ns and 0.012 ns respectively.
Fig.2 Timing diagram and layout structure
October 9, 2012 Pass Transistor Logic 13

14.  PTL has been successfully used to implement digital systems
which are smaller, faster, and more energy efficient than static
CMOS implementations for the same designs.
Fig.3 Schematic of 2:1 MUX using CPL in DSCH2
October 9, 2012 Pass Transistor Logic 14

15.  Timing operation performed on 2:1 MUX CPL design, the
rise delay and fall delay calculated is 0.005 ns and 0.004 ns
respectively.
Fig.4 Timing diagram and layout structure
October 9, 2012 Pass Transistor Logic 15

16. S.N. Parameters Conventional CMOS PASS TRANSISTOR
LOGIC
1 Width of Layout 21.7 μm (434 lambda) 11.3 μm (226 lambda)
2 Height Of Layout 7.0 μm (140 lambda) 5.8 μm (116 lambda)
3 Surface Area of Layout 151.9 μm2 65.5 μm2
4 Power Consumption 12.204 μW 1.381 μW
5 Rise Delay 0.012 ns 0.005 ns
6 Fall delay 0.012 ns 0.004 ns
7 No. of Transistor required 12 6
October 9, 2012 Pass Transistor Logic 16

17. Pass Transistor Logic October 9, 2012 17

18.  A. P. Chandrakasan and R. W. Brodersen , “ Low Power Digital CMOS
Design, Kluwer, Norwell MA. 1995.
 Neil Weste, Harris & Banerjee, CMOS VLSI Design: A Circuits and
Systems Perspective, 3rd Edition, Pearson Education, Boston, 2005, p1-16.
 Zimmermann, R.; Fichtner, W.; “ Low-Power Logic Styles: CMOS versus
Pass-Transistor Logic” IEEE Transaction on Solid-State Circuits, Volume
32, Page(s) 1079-1090, Publication Year: 1997.
 Microwind user manual and DSCH user manual. Retrieved February 2012
from Microwind commercial website: http://www.microwind.net.
 Zhou, H.; Aziz, A.; “ Buffer Minimization in Pass Transistor Logic” , IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, Volume 20, Page(s ) 693-697, May 2001.
October 9, 2012 Pass Transistor Logic 18

19. Pass Transistor Logic October 9, 2012 19

20. Pass Transistor Logic October 9, 2012 20