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1. Design and Implementation of VLSI Systems
(EN1600)
Lecture08

2. Summary of Shockley model
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9)
p-type body

 0 Vgs < Vt cutoff


I ds =  β Vgs − Vt − ds V V < V
V
  ds linear
2 ds dsat
  
 β
( Vgs − Vt )
2
 Vds > Vdsat saturation
 2
for nMOS for pMOS

3. Ideal vs. non-ideal
ideal Non-ideal
 Saturation current does not increase quadratically with Vgs
 Saturation current lightly increases with increase in Vds

4. Ideal vs. non-ideal
 There is leakage current when the transistor is in cut off
 Ids depends on the temperature

5. Velocity saturation
At high electric field, drift velocity rolls
υ n (m /s )
of due to carrier scattering
υsat= 105
Constant velocity
Constant mobility (slope = µ)
ξc = 1.5
ξ (V/µm)
Empirically:

6. Alpha model
 0 Vgs < Vt cutoff

 V
I ds =  I dsat ds Vds < Vdsat linear
 Vdsat
 I dsat
 Vds > Vdsat saturation
β
= Pc ( Vgs − Vt )
α
I dsat
2
Vdsat = Pv ( Vgs − Vt )
α /2
Pc, Pv and alpha are found by fitting the model to the empirical
modeling results

7. Channel length modulation VDD VDD
GND
Source Gate Drain
Depletion Region
Width: Ld
• The reverse-bias p-n junction between drain
and body forms a depletion region with a width n+
L
Leff n+
Ld that increases with Vdb p GND bulk Si
• Increasing Vds
 increases depletion width
 decreases effective channel length
 increases current
Channel length
modulation factor
(empirical factor)

8. Leakage current: subthreshold
Tunnel current
polysilicon
gate
W
t ox
L
n+ n+
p-type body Subthreshold conduction
Junction leakage
 Subthreshold leakage is
the biggest source in
modern transistors 180nm process
Vgs −Vt
 −Vds

I ds = I ds 0e nvT
1 − e T
v

 
 
I ds 0 = β vT e1.8
2
n = 1.4-15

9. Leakage current: junction leakage and
tunneling
Junction leakage: reverse-biased p-n junctions have
 VD 
some leakage. I D = I S  e − 1
vT
Is depends on doping levels and area and perimeter  
 
of diffusion regions
p+ n+ n+ p+ p+ n+
n well
p substrate
109
tox
VDD trend 0.6 nm
Tunneling leakage:
106
0.8 nm
J (A/cm )
1.0 nm
103
2
 Carriers may tunnel thorough very thin gate oxides
1.2 nm
100 1.5 nm
G
 Negligible for older processes 10-3
1.9 nm
(and future processes with high-k dielectrics!) 10-6
10-9
0 0.3 0.6 0.9 1.2 1.5 1.8
VDD

10. Impact of temperature
• Increases in temperature increases leakage current
• Increases in temperature decreases leakage current

11. Body effect
 Vt is sensitive to Vsb -> body effect
Vt = Vt 0 + γ ( φs + Vsb − φs )
NA
φs = 2vT ln
ni
tox 2qε si N A
γ = 2qε si N A =
ε ox Cox
• What is the impact on Vt if we increase/decrease the body bias?

12. Process variations
Both MOSFETs have 30nm channel with 130
dopant atoms in the channel depletion region
threshold voltage 0.97V threshold voltage 0.57V
Process variations impact gate length, threshold
voltage, and oxide thickness

13. Summary
 Ideal transistor characteristics
 Non-ideal transistor characteristics
 Inverter DC transfer characteristics
 Simulation with SPICE and integration with L-Edit