This document describes domino CMOS logic. It explains that domino CMOS logic cascades a dynamic CMOS logic stage with a static CMOS inverter stage. During precharge, the dynamic stage output is high and the inverter output is low. During evaluation, the dynamic stage output can either discharge low or remain high, triggering the next stage. Multiple stages can be cascaded like falling dominoes. Limitations include only supporting non-inverting logic and susceptibility to charge sharing errors. Ways to prevent errors include adding weak pull-up transistors and precharging all high-capacitance nodes. Performance can be improved by adjusting transistor sizes to reduce discharge time.

1. DOMINO CMOS LOGIC
Priya Srivastava,090105801
Sharda University.

2. INTRODUCTION:
 A dynamic CMOS logic stage is being cascaded
with a static CMOS inverter stage.
 The addition of the inverter allows us to operate
a number of structures in cascade.

3.  During the precharged stage,
the output node of the
dynamic CMOS stage is
precharged to a high logic
level, & the output of the
CMOS inverter becomes low.
 When the clock signal rises
at the beginning of evaluation
phase, there are 2
possibilities: the output node
is ether discharged to the
low level or it remains high.
 Each buffer output can make
almost one transition in
evaluation phase.

4.  In a cascade structure
consisting of several stages,
the evalution of each stage
ripples the next stage
evaluation, similar to the
chain of dominos falling one
after the other. The
structure is called domino
CMOS structure.

5. LIMITATION:
o The number of inverting static logic stages in
cascade must be even, to let the inputs of next
domino stage can have only 0 to 1 transitions during
the evaluation.
o Can implement only non-inverting logic .
o Due to precharge use, can suffer from charge
sharing during the evaluation which may cause
erroneous outputs.

7. CHARGE SHARING:
 The intermediate node capacitance C2 is
comparable to the output node capacitance C1.
 Assuming all inputs are low, voltage across C2=0v
 Precharge phase, C1 is charged upto logic level of
VDD through pMOS transistor.
 In next phase, the clock signal becomes high &
the evalution starts.
 If the input signal of uppermost nMOS switches
from low to high, the charge initially at C1 will b
shared by C2, this phenomenon is called charge
sharing.

9. PREVENTING ERRONEOUS OUTPUT:
 To prevent erroneous output levels due to charge
sharing,
 1. add a weak pMOS pull-up device to CMOS
output.
 It forces a high output level unless there is a
strong pull down path between the output and
the ground.
 The week pMOS will be turned on only when the
precharge node voltage is kept high.

11.  2. use separate pMOS transistors to precharge
all intermediate nodes in nMOS pull-down which
have a large capacitance. The precharging of all
high-capacitances nodes within the circuit
eliminates all potential charge-sharing problems
due to evaluation.
 3. the logic threshold voltage is made smaller,
such that the final stage output is not affected
by lowering of node voltage due to charge
sharing.

12. IMPROVING PERFORMANCE
 The transient performance of domino CMOS
logic gates can be improved by adjusting nMOS
transistor sizes in pull down path, to reduce the
discharge time.
 The best performance is obtained with a graded
size of nMOS transistor in series structure,
where the nMOS transistor closest to the
output node also has the smallest (W/L) ratio.

14. THANK YOU…!!!