International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
VHDL Implementation of Capacitor Voltage Balancing Control with Level-Shifted...IAES-IJPEDS
Power electronics converters are a key component in high voltage direct
current (HVDC) power transmission. The modular multilevel converter
(MMC) is one of the latest topologies to be proposed for this application. An
MMC generates multilevel output voltage waveforms which reduces the
harmonics contents significantly. This paper presents a VHDL
implementation of the capacitor voltage balancing control and level-shifted
pulse width modulation (LSPWM) for MMC. The objective is to minimize
the processing time with minimum gate counts. The design details are fully
described and validated experimentally. An experiment is conducted on a
small scale MMC prototype with two units of power cells on each arm. The
test results are enclosed and discussed.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
Stack Contention-alleviated Precharge Keeper for Pseudo Domino LogicjournalBEEI
The dynamic circuits are supposed to offer superior speed and low power dissipation over static CMOS circuits. The domino logic circuits are used for high system performance but suffer from the precharge pulse degradation. This article provides different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay. The precharge keeper circuit has been proposed such that the keeper transistors also work as the precharge transistors to realize multiple output function. The performance improvement of the circuit’s analysis have been done for adders and logic gates using HSPICE tool. The proposed keeper techniques reveal lower power dissipation and lesser delay over the standard keeper circuit with less transistor count for different process variation.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
VHDL Implementation of Capacitor Voltage Balancing Control with Level-Shifted...IAES-IJPEDS
Power electronics converters are a key component in high voltage direct
current (HVDC) power transmission. The modular multilevel converter
(MMC) is one of the latest topologies to be proposed for this application. An
MMC generates multilevel output voltage waveforms which reduces the
harmonics contents significantly. This paper presents a VHDL
implementation of the capacitor voltage balancing control and level-shifted
pulse width modulation (LSPWM) for MMC. The objective is to minimize
the processing time with minimum gate counts. The design details are fully
described and validated experimentally. An experiment is conducted on a
small scale MMC prototype with two units of power cells on each arm. The
test results are enclosed and discussed.
High Speed Low Power CMOS Domino or Gate Design in 16nm Technologycsandit
Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. This paper proposes a wide
fan-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other
circuits. The design also offers very less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Design of High-Speed Dynamic Double-Tail ComparatorIJERDJOURNAL
ABSTRACT:- The analog-to-digital converters which are of ultra low-power, area efficient, and high speed converters are made of dynamic regenerative comparators. These comparators can maximize speed and power efficiency. The delay and power dissipation of dynamic comparators are analyzed in this paper. The delays and tradeoff can be explored. The circuit of a conventional double tail comparator in this analysis is modified for fast operation even in different supply voltages. By using power gating technique and adding few transistors, the positive feedback during the regeneration is strengthened in the proposed comparator structure. The delay time can be reduced by providing positive feedback instead of adding few transistors. The analysis results are going to be confirmed on the basis of 0.25-µm CMOS technology. The power consumption and delay time can be significantly reduced based on this analysis. All the simulation are made using TANNER TOOLS, Generic 250nm. The schematic are drawn in the T-SPICE schematic editor.
This document describes a hybrid full adder design using both CMOS and transmission gate technologies that achieves low power and high speed. The design is divided into modules: 1) an XOR-XNOR module using weak inverters to reduce power, 2) a sum generation module using transmission gates, and 3) a carry generation module using strong transmission gates to reduce delay. Simulation results show the hybrid full adder achieves a power dissipation of 2.94μW and delay of 61.4ps at 1.8V in a 180nm technology, with lower power at lower voltages. This design coupled weak inverters with strong transmission gates to achieve both low power and high speed.
Design of Low Voltage D-Flip Flop Using MOS Current Mode Logic (MCML) For Hig...IOSRJVSP
This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC’s. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.
This document proposes a new dynamic power control algorithm with variable quality of service (QoS) for different substreams in CDMA systems. It aims to minimize transmitter power while maintaining reliable communication. The algorithm assigns different power levels to each traffic type/substream to provide unequal error protection. It uses a combination of open-loop power control to compensate for slow fading and closed-loop power control using power control bits transmitted every 1.25ms to adjust power based on measured signal quality and compensate for fast fading. This allows supporting variable QoS while transmitting the minimum necessary power for each substream to reduce interference for other users.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
logical effort based dual mode logic gates by mallikaMallika Naidu
Logic optimization and timing estimations are basic tasks for digital circuit designers. Dual Mode Logic (DML) allows operation in two modes such as static and dynamic modes. DML gates can be switched between these two modes on feature very low power dissipation in the static mode and high speed of operation in dynamic mode which is achieved at the expense of increased power dissipation. We introduce the logical effort (LE) methodology for the CMOS-based family. The proposed methodology allows path length, delay and power optimization for number of stages with load. Logical effort is the transistor sizing optimization methodology reduces the delay and power with number of stages with any static logic gate. The proposed optimization is shown for dual mode logic gates with logical effort using Digital Schematic Tool (DSCH).
Brushless DC Motor Drive using an Isolated-Luo Converter for Power Factor Cor...IRJET Journal
This document summarizes a research paper on a brushless DC motor drive using an isolated Luo converter for power factor correction. Key points:
1) A brushless DC motor drive is presented using an isolated Luo converter to improve power quality at the AC mains while allowing for speed control of the BLDC motor.
2) The isolated Luo converter operates in discontinuous inductor current mode using a single voltage sensor, achieving inherent power factor correction with reduced sensing requirements.
3) Simulation results are presented to evaluate the performance of the drive in improving power quality for varying motor speeds and supply voltages.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Iaetsd design and analysis of low-leakage high-speedIaetsd Iaetsd
This document summarizes and compares different domino circuit designs for wide fan-in OR gates. It describes 8 different domino circuit techniques: 1) Standard Footless Domino, 2) Conditional-Keeper Domino, 3) High-Speed Domino, 4) Leakage Current Replica Keeper Domino, 5) Controlled Keeper by Current-Comparison Domino, 6) Diode Footed Domino, 7) Diode-Partitioned Domino, and 8) Wide Fan-In OR gate Current Comparison Domino. It simulates these circuits in 180nm, 130nm, and 90nm technologies and compares their power, propagation delay, energy, and energy-delay product performance.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
The 3GPP evolution for the 3G mobile system created the new base station system, called Evolved UMTS Terrestrial Radio Access Network (E-UTRAN) and a new core network, called Evolved Packet Core (EPC) as a result of two standardisation projects: Long Term Evolution (LTE) and System Architecture Evolution (SAE). Under these specifications a mobile phone gets access to higher bandwidth with low latency in an improved and more efficient network architecture. The standards define an all-IP network as a base for the E-UTRAN/EPC. The E-UTRAN/EPC does not have a separate PS data traffic and CS voice network, both communicate over the same new Evolved Packet System (EPS) network. LTE/EPS Technology course is an intermediate technical course, which covers all aspects of architecture and functionality of the EPS.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Delay Optimized Full Adder Design for High Speed VLSI ApplicationsIRJET Journal
This document describes the design and simulation of a hybrid full adder circuit for high-speed VLSI applications. Full adders are important components used in arithmetic logic units, floating point units, and address generation. The author first reviews existing full adder designs based on static CMOS, transmission gate, and dynamic logic styles. Then, a previously proposed hybrid CMOS full adder using both transmission gates and CMOS is described. To improve speed, the author proposes a modified full adder design using only 14 transistors instead of 16. Both the existing and proposed designs are simulated in Cadence Virtuoso at 180nm and 90nm technology nodes. Simulation results show the proposed design has lower power consumption and propagation delay compared to the
Microcontroller–Based Modified SEPIC Converter for Driving Lamp with Power Fa...IJERA Editor
A methodological study of electronic ballast for electrode less lamps including design and development issues is
presented in this paper. The ballast is intended to feed a 300 W ultra violet lamp at 100 kHz with dimming
feature. The proposed topology is composed of a Single-Ended Primary Inductance Converter (SEPIC), used as
power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control
(PC) stage. The integration of both stages is proposed in this paper, in order to reduce the number of active
switches, as well as to simplify the required driving and control circuitry for this application. The implemented
topology attained very high power factor (0.9982), and low line current total harmonic distortion (THD)
(1.86%), without using electromagnetic interference (EMI) filter, while the measured efficiency was 90% at
nominal lamp power.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Fuzzy Logic Controller Based Single Buck Boost Converter for Solar PV CellIJAPEJOURNAL
This paper deals with solar power production controlled by Fuzzy Logic Controller (FLC) and Single Input Buck-Boost (SIBB) converter. Since the solar energy is continuously varying, according to the irradiation the FLC generates control pulses to switch on the MOSFET device. To analyze the real time feasibility of this method, the system is simulated by using MATLAB/Simulink 2010a. A simulation model of the system is developed with solar Photovoltaic (PV) cell, FLC and SIBB in contradiction of the real world conditions. The results are presented and discussed in this paper.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
The document discusses harmonic mitigation in power systems to reduce transmission losses. It describes how the increasing use of power electronics devices introduces harmonics and reactive power issues. A 48-pulse voltage source inverter StatCom configuration is proposed and analyzed through simulation. The StatCom utilizes four three-level converters linked by phase-shifting transformers to generate low harmonic voltage waveforms. Simulation results show the StatCom is effective in mitigating harmonics, improving power quality, regulating voltage, and reducing transformer loading. A techno-economic analysis indicates it can provide approximately $2 lakh yearly savings with a six year payback period.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document summarizes research on the synthesis and characterization of a new nonlinear organic single crystal called urea L-asparagine. Key findings include:
1) Urea L-asparagine crystals were grown using a slow evaporation solution method and yielded bright, transparent crystals measuring 11 x 0.7 x 0.3 cm3.
2) Elemental analysis and powder X-ray diffraction confirmed the crystalline nature and stoichiometric composition of the compound.
3) Single crystal X-ray diffraction showed the crystal has an orthorhombic structure with space group P.
4) Optical and vibrational spectroscopy showed the crystal has good transmittance in the visible range
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This document proposes a new dynamic power control algorithm with variable quality of service (QoS) for different substreams in CDMA systems. It aims to minimize transmitter power while maintaining reliable communication. The algorithm assigns different power levels to each traffic type/substream to provide unequal error protection. It uses a combination of open-loop power control to compensate for slow fading and closed-loop power control using power control bits transmitted every 1.25ms to adjust power based on measured signal quality and compensate for fast fading. This allows supporting variable QoS while transmitting the minimum necessary power for each substream to reduce interference for other users.
The document summarizes two new buffer circuit designs for footed domino logic that aim to reduce power consumption. The proposed circuits minimize redundant switching at the output node during the precharge phase, which saves power. Simulation results using a 180nm CMOS technology show that the proposed circuits reduce power consumption and power-delay product compared to a standard domino circuit across different logic functions, loading conditions, clock frequencies, temperatures and power supplies. Power savings of up to 36% were achieved at higher operating frequencies.
logical effort based dual mode logic gates by mallikaMallika Naidu
Logic optimization and timing estimations are basic tasks for digital circuit designers. Dual Mode Logic (DML) allows operation in two modes such as static and dynamic modes. DML gates can be switched between these two modes on feature very low power dissipation in the static mode and high speed of operation in dynamic mode which is achieved at the expense of increased power dissipation. We introduce the logical effort (LE) methodology for the CMOS-based family. The proposed methodology allows path length, delay and power optimization for number of stages with load. Logical effort is the transistor sizing optimization methodology reduces the delay and power with number of stages with any static logic gate. The proposed optimization is shown for dual mode logic gates with logical effort using Digital Schematic Tool (DSCH).
Brushless DC Motor Drive using an Isolated-Luo Converter for Power Factor Cor...IRJET Journal
This document summarizes a research paper on a brushless DC motor drive using an isolated Luo converter for power factor correction. Key points:
1) A brushless DC motor drive is presented using an isolated Luo converter to improve power quality at the AC mains while allowing for speed control of the BLDC motor.
2) The isolated Luo converter operates in discontinuous inductor current mode using a single voltage sensor, achieving inherent power factor correction with reduced sensing requirements.
3) Simulation results are presented to evaluate the performance of the drive in improving power quality for varying motor speeds and supply voltages.
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Iaetsd design and analysis of low-leakage high-speedIaetsd Iaetsd
This document summarizes and compares different domino circuit designs for wide fan-in OR gates. It describes 8 different domino circuit techniques: 1) Standard Footless Domino, 2) Conditional-Keeper Domino, 3) High-Speed Domino, 4) Leakage Current Replica Keeper Domino, 5) Controlled Keeper by Current-Comparison Domino, 6) Diode Footed Domino, 7) Diode-Partitioned Domino, and 8) Wide Fan-In OR gate Current Comparison Domino. It simulates these circuits in 180nm, 130nm, and 90nm technologies and compares their power, propagation delay, energy, and energy-delay product performance.
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
High-Performance of Domino Logic Circuit for Wide Fan-In Gates Using Mentor G...iosrjce
IOSR journal of VLSI and Signal Processing (IOSRJVSP) is a double blind peer reviewed International Journal that publishes articles which contribute new results in all areas of VLSI Design & Signal Processing. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & Signal Processing concepts and establishing new collaborations in these areas.Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
Design and Analysis of New Modified Feedthrough Logic (MFTL) Circuits Using C...IJERA Editor
It is a challenging task for a VLSI design engineer to develop low power VLSI circuits, without sacrificing its performance. Feedthrough Logic (FTL) is a new technology which could be considered better than the existing technologies for improving circuit efficiency. Modified Feedthrough Logic (MFTL), offers a better power factor than the FTL logic structures, and also shows an improvement in the speed factor. But the scenario again changes when the design extends to nano scales of device dimension, where many factors which were neglected otherwise need to be given more importance. To avoid or minimize problems like hot carrier effects, electro migration, drain induced barrier lowering and other issues that becomes prominent in nano scale MOSFET‟s, Carbon Nanotube Field Effect Transistor (CNTFET) is considered to be a promising candidate in future integrated circuits. Hence this work extends the advantages of MFTL logic into nano level by incorporating CNTFETs in place of MOSFETs. The modifications have been implemented using CNTFETs of 16nm technology from HSPICE library on a 10 chain inverter stage, an 8 bit RCA and a Vedic multiplier and performance factors like PDP and ADP are compared to that of the conventional MOSFET circuits.
A Novel Low Power Energy Efficient SRAM Cell With Reduced Power Consumption u...iosrjce
In modern high performance integrated circuits, maximum of the total active mode energy is
consumed due to leakage current. SRAM cell array is main source of leakage current since majority of
transistor are utilized for on-chip memory in today high performance microprocessor and system on chip
designs. Therefore the design of low leakage SRAM is required. Reducing power dissipation, supply voltage,
leakage currents, area of chip are the most important parameters in today`s VLSI designs. But scaling of these
parameters will lead to drastic increase in sub threshold leakage currents and power dissipation because of that
performance of the design is degraded. So to overcome these issues it is better to concentrate on reduction of
active leakage currents and dynamic power dissipation by using power reduction techniques. In this paper 9T
SRAM (data retention p-gated) cell for low voltage and energy constrain application is analyzed with respect to
power dissipation, area and delay. The analyzed design of 9T SRAM cell with MTCMOS technique has been
proposed. Designed circuits are simulated in Microwind 3.1 VLSI CAD Tool in 90 and 65nm CMOS technology.
In this article, we proposed a Variable threshold MOSFET(VTMOS)approach which is realized from Dynamic Threshold MOSFET(DTMOS), suitable for sub-threshold digital circuit operation. Basically the principle of sub- threshold logics is operating MOSFET in sub-threshold region and using the leakage current in that region for switching action, there by drastically decreasing power .To reduce the power consumption of sub-threshold circuits further, a novel body biasing technique termed VTMOS is introduced .VTMOS approach is realized from DTMOS approach. Dynamic threshold MOS (DTMOS) circuits provide low leakage and high current drive, compared to CMOS circuits, operated at lower voltages.
The VTMOS is based on operating the MOS devices with an appropriate substrate bias which varies with gate voltage, by connecting a positive bias voltage between gate and substrate for NMOS and negative bias voltage between gate and substrate for PMOS. With VTMOS, there is a considerable reduction in operating current and power dissipation, while the remaining characteristics are almost the same as those of DTMOS. Results of our investigations show that VTMOS circuits improves the power up to 50% when compared to CMOS and DTMOS circuits, in sub- threshold region..
The performance analysis and comparison of VTMOS , DTMOS and CMOS is made and test results of Power dissipation, Propagation delay and Power delay product are presented to justify the superiority of VTMOS logic over conventional sub-threshold logics using Hspice Tool. . The dependency of these parameters on frequency of operation has also been investigated.
The 3GPP evolution for the 3G mobile system created the new base station system, called Evolved UMTS Terrestrial Radio Access Network (E-UTRAN) and a new core network, called Evolved Packet Core (EPC) as a result of two standardisation projects: Long Term Evolution (LTE) and System Architecture Evolution (SAE). Under these specifications a mobile phone gets access to higher bandwidth with low latency in an improved and more efficient network architecture. The standards define an all-IP network as a base for the E-UTRAN/EPC. The E-UTRAN/EPC does not have a separate PS data traffic and CS voice network, both communicate over the same new Evolved Packet System (EPS) network. LTE/EPS Technology course is an intermediate technical course, which covers all aspects of architecture and functionality of the EPS.
Theoretical Analysis of a two-stage Sagnac loop filter Using Jones Matrices IJECEIAES
In this work, a theoretical analysis of a Sagnac loop filter (SLF) with twostage polarization maintaining fibers (PMFs) and polarization controllers (PCs) is presented. The transmission function of this two-stage SLF is calculated in detail by using Jones matrix. The calculation is performed in order to investigate the filtering characteristics. The theoretical results show that the wavelength interval is depending on the dynamic settings of the length of the PMFs and the polarization angle of the PCs. By changing the polarization angle of the PCs, a multiple of single, dual or triple wavelength in each channel can be achieved. Based on this study, a flat multiwavelength spectrum can be obtained by adjusting the PMFs and the PCs in the twostage SLF. This finding significantly contributes to the generation of multiwavelength fiber laser (MWFL) that can be used for many optical applications.
Delay Optimized Full Adder Design for High Speed VLSI ApplicationsIRJET Journal
This document describes the design and simulation of a hybrid full adder circuit for high-speed VLSI applications. Full adders are important components used in arithmetic logic units, floating point units, and address generation. The author first reviews existing full adder designs based on static CMOS, transmission gate, and dynamic logic styles. Then, a previously proposed hybrid CMOS full adder using both transmission gates and CMOS is described. To improve speed, the author proposes a modified full adder design using only 14 transistors instead of 16. Both the existing and proposed designs are simulated in Cadence Virtuoso at 180nm and 90nm technology nodes. Simulation results show the proposed design has lower power consumption and propagation delay compared to the
Microcontroller–Based Modified SEPIC Converter for Driving Lamp with Power Fa...IJERA Editor
A methodological study of electronic ballast for electrode less lamps including design and development issues is
presented in this paper. The ballast is intended to feed a 300 W ultra violet lamp at 100 kHz with dimming
feature. The proposed topology is composed of a Single-Ended Primary Inductance Converter (SEPIC), used as
power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control
(PC) stage. The integration of both stages is proposed in this paper, in order to reduce the number of active
switches, as well as to simplify the required driving and control circuitry for this application. The implemented
topology attained very high power factor (0.9982), and low line current total harmonic distortion (THD)
(1.86%), without using electromagnetic interference (EMI) filter, while the measured efficiency was 90% at
nominal lamp power.
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Cl...IJECEIAES
This paper presents a design and implementation of 2*2 array and 4*4 array multiplier using proposed Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit. The proposed 2PASCL circuit is based on adiabatic energy recovery principle which consumes less power. The proposed 2PASCL uses two sinusoidal power clocks which are 180 0 phase shifted with each other. The measurement result of 2*2 array proposed 2PASCL multiplier gives 80.16 % and 97.67 %power reduction relative to reported 2PASCL and conventional CMOS logic and the measurement result of 4*4 array proposed 2PASCL multiplier demonstrate 32.88 % and 82.02 %power reduction compared to reported 2PASCL and conventional CMOS logic. Another advantage of the proposed circuit is that it gives less power though the number of transistors in proposed and reported 2PASCL circuit is same. From the result we conclude that proposed 2PASCL technology is advantageous to application in low power digital systems, pacemakers and sensors. The circuits are simulated at 180nm technology mode.
Fuzzy Logic Controller Based Single Buck Boost Converter for Solar PV CellIJAPEJOURNAL
This paper deals with solar power production controlled by Fuzzy Logic Controller (FLC) and Single Input Buck-Boost (SIBB) converter. Since the solar energy is continuously varying, according to the irradiation the FLC generates control pulses to switch on the MOSFET device. To analyze the real time feasibility of this method, the system is simulated by using MATLAB/Simulink 2010a. A simulation model of the system is developed with solar Photovoltaic (PV) cell, FLC and SIBB in contradiction of the real world conditions. The results are presented and discussed in this paper.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
The document discusses harmonic mitigation in power systems to reduce transmission losses. It describes how the increasing use of power electronics devices introduces harmonics and reactive power issues. A 48-pulse voltage source inverter StatCom configuration is proposed and analyzed through simulation. The StatCom utilizes four three-level converters linked by phase-shifting transformers to generate low harmonic voltage waveforms. Simulation results show the StatCom is effective in mitigating harmonics, improving power quality, regulating voltage, and reducing transformer loading. A techno-economic analysis indicates it can provide approximately $2 lakh yearly savings with a six year payback period.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The document summarizes research on the synthesis and characterization of a new nonlinear organic single crystal called urea L-asparagine. Key findings include:
1) Urea L-asparagine crystals were grown using a slow evaporation solution method and yielded bright, transparent crystals measuring 11 x 0.7 x 0.3 cm3.
2) Elemental analysis and powder X-ray diffraction confirmed the crystalline nature and stoichiometric composition of the compound.
3) Single crystal X-ray diffraction showed the crystal has an orthorhombic structure with space group P.
4) Optical and vibrational spectroscopy showed the crystal has good transmittance in the visible range
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
O documento descreve as ações realizadas pelo Brasília Shopping para aproveitar as oportunidades de marketing durante a Copa do Mundo de 2014 no Brasil, como criar um ambiente para assistir aos jogos e encontrar torcedores, promover campanhas publicitárias e divulgação, e oferecer serviços aos turistas. Essas ações resultaram em aumento significativo no fluxo e vendas do shopping durante o evento.
Mary Dilts is a television host and narrator based in San Francisco. She has experience hosting shows for networks like QVC, Travel Channel, and local stations. She has also worked as a reporter on films and television shows. Additionally, she provides narration and spokesperson work for many large corporations. Her skills include using earprompters, teleprompters, working with virtual sets, music and sound design, character voices, and illustrations. A DVD/CD demo of her work is available upon request.
The document discusses the benefits of exercise for mental health. Regular physical activity can help reduce anxiety and depression and improve mood and cognitive functioning. Exercise boosts blood flow and levels of neurotransmitters and endorphins which elevate and stabilize mood.
Este documento describe los principios de la terapia antidótica. Explica que un antídoto es una sustancia terapéutica utilizada para contrarrestar los efectos tóxicos de un químico. Los antídotos actúan a través de mecanismos farmacocinéticos o farmacodinámicos, como interferir con la absorción, distribución o eliminación del tóxico, o bloquear su mecanismo de acción. El éxito de la terapia antidótica depende de la especificidad del ant
Este documento presenta un taller grupal sobre la creación de instrumentos de evaluación basados en procedimientos de observación y rendimiento. El grupo debe crear una prueba escrita evaluando conceptos y procedimientos sobre evaluación educativa, y dos copias, una con las preguntas y otra con las respuestas y criterios de corrección.
Herramientas para el trabajo colaborativoAndres MaYa
Este documento describe diferentes herramientas para el trabajo colaborativo como Google Maps, Google Calendar, Google Docs, foros, microblogs, marcadores sociales, redes sociales, wikis y Dropbox. Cada herramienta se explica detallando sus funciones y cómo pueden ser utilizadas para mejorar la colaboración dentro de una empresa.
Este edital de concurso público descreve as seguintes informações essenciais:
1) Estabelece as vagas disponíveis para diversos cargos na Câmara Municipal de Colombo e os requisitos mínimos para cada cargo.
2) Detalha o processo de inscrição no concurso, incluindo taxa de inscrição, prazo para inscrição e pagamento, e requisitos para candidatos com deficiência.
3) Apresenta as etapas do concurso, incluindo provas eliminatórias e classificat
Los niños de parvulario aprendieron a identificar objetos rojos y cuadrados. A través de juegos y actividades prácticas, los estudiantes practicaron reconocer y nombrar cosas que son rojas o tienen forma cuadrada para desarrollar sus habilidades de percepción visual y vocabulario.
O documento discute os benefícios do uso de celulares em sala de aula para promover o desenvolvimento intelectual, social e cognitivo dos alunos. Ele argumenta que os celulares podem ser usados para engajar os alunos ativamente na construção do conhecimento e desenvolver suas habilidades de comunicação. Além disso, o documento fornece dicas sobre como criar políticas e conteúdo educacional que otimizem o uso de celulares em sala de aula de forma responsável.
Este documento apresenta um resumo de 5 textos e trabalhos realizados por alunos sobre a cidade de São Paulo. Cada texto aborda um aspecto diferente da cidade, como sua diversidade cultural e monumentos históricos. Os alunos também produziram crônicas individuais sobre suas experiências na metrópole e um trabalho de antropologia urbana.
O documento discute a importância do brincar para o desenvolvimento infantil, os riscos do sedentarismo e os diferentes graus de obesidade. A primeira seção explica que, apesar da importância reconhecida do brincar, as crianças têm rotinas muito atarefadas com pouca tempo para brincar. A segunda seção define sedentarismo como falta de atividade física suficiente, enquanto as seções seguintes descrevem os graus 1 e 2 de obesidade.
The document summarizes updates to Honey Spots, a tool for detecting structural variants from long read sequencing data. It describes performance optimizations that reduced runtime for an example dataset from 2 days to 6 hours. It also reports on less restrictive filtering that allows more sensitive calling. The document then shows results of applying Honey Spots to detect insertions and deletions in real sequencing data from several individuals, demonstrating detection rates over 65% for most variant size ranges.
A Survey Analysis on CMOS Integrated Circuits with Clock-Gated Logic StructureIJERA Editor
Various circuit design techniques has been presented to improve noise tolerance of the proposed CGS logic families. Noise in deep submicron technology limits the reliability and performance of ICs. The ANTE (Average Noise Threshold Energy) metric is used for the analysis of noise tolerance of proposed CGS. A 2-input NAND and NOR gate is designed by the proposed technique. Simulation results for a 2-input NAND gate at clock gated logic show that the proposed noise tolerant circuit achieves 1.79X ANTE improvement along with the reduction in leakage power. Continuous scaling of technology towards the manometer range significantly increases leakage current level and the effect of noise. This research can be further extended for performance optimization in terms of power, speed, area and noise immunity.
Energy Efficient Design of Multiplexer Using Adiabatic logicIJEEE
the increasing prominence of portable systems and the need to limit the power consumption in very high density VLSI chips have led to rapid and innovative developments in low power design during the recent years. The CMOS technology provides circuits with very low static power dissipation, during the switching operation currents are generated, due to the discharge of load capacitances that cause power dissipation increasing with the clock frequency. The adiabatic technique prevents such losses, the charge does not flow from the supply voltage to the load capacitance and then to ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be reused.In this paper a low 2:1 multiplexer is designed using positive feedback adiabatic logic. The design is simulated at .12µm technology using Microwind 3.1. Simulated results shows that proposed design saves 38% energy as compare to conventional CMOS design.
Analysis and design_of_a_low-voltage_low-power[1]Srinivas Naidu
The document presents an analysis of the delay characteristics of dynamic comparators. It analyzes the delay of conventional dynamic and double-tail comparators, deriving analytical expressions showing the impact of various design parameters on delay. A new dynamic comparator is then proposed based on modifying the circuit of a conventional double-tail comparator to strengthen positive feedback, reducing delay time. Simulation results on the proposed comparator show significantly reduced power consumption and delay compared to conventional designs, enabling higher clock frequencies at lower supply voltages.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
This paper presents a recursive designing approach for high energy efficient carry select adder (CSA). Nowadays, the portable equipment’s like mobile phones and laptops have higher demands in the market. So, the designers must focus greater attention while designing such devices. Which means that have the devices must have lesser power consumption, low cost and have a better performance. The customers mainly focus on the equipment’s which have lesser power consumption, low cost and better performance. As we all know that the adders are the basic building block of microprocessors. The performance of the adders greatly influences the performance of those processors. The carry select adder is most suitable among other adders which have fast addition operation at low cost. The carry select adder (CSA) consists of chain full adders (FAs) and multiplexers. Here a carry select adder is designed with four FAs and four multiplexers. The proposed structure is assessed by the power consumption of the carry select adder using a 32-nm static CMOS technology for a wide range of supply voltages. The simulation results are obtained using Tanner EDA which reveals that the carry select adder has low power consumption.
This document analyzes and compares different existing domino logic full adder circuits and proposes a new hybrid logic domino full adder circuit. It finds that the proposed circuit provides better performance in terms of area, power consumption, and number of transistors compared to existing circuits. The document also presents two applications of the proposed full adder circuit: a 1-bit ALU and a 2-bit comparator. All circuits are designed and simulated using DSCH and MICROWIND tools, and simulation results show that the proposed full adder and its applications reduce power consumption and area over previous designs.
This paper presents the functions of Series-Loaded Resonant Converter (SLRC). Series Loaded Resonant DC-DC converter is a type of soft-switching topology widely known for providing improved efficiency. Zero voltage switching (ZVS) buck converter is more preferable over hard switched buck converter for low power, high frequency DC-DC conversion applications. Zero Voltage switching techniques will be used to improve the efficiency of current and voltage at the series loaded half-bridge rectifier. The results will be described from PSIM simulation, Programming of MATLAB calculation and hardware testing.
An Ultra-Low Power Robust Koggestone Adder at Sub-Threshold Voltages for Impl...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold region minimize the energy per operation, thus providing a better platform for energy constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages which can be used for low power implantable bio-medical devices such as pacemakers. To improve the performance of these adders in sub-threshold region, forward body bias technique and multi-threshold transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using 0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing technique shows an effective improvement compared to high threshold voltage and multi threshold voltage techniques. The forward biasing technique maintains a balance between delay reduction and increase in average power, thus reducing the power delay product when compared to the other two techniques.
AN ULTRA-LOW POWER ROBUST KOGGESTONE ADDER AT SUB-THRESHOLD VOLTAGES FOR IMPL...VLSICS Design
The growing demand for energy constrained applications and portable devices have created a dire need for
ultra-low power circuits. Implantable biomedical devices such as pacemakers need ultra-low power
circuits for a better battery life for uninterrupted biomedical data processing. Circuits operating in subthreshold
region minimize the energy per operation, thus providing a better platform for energy
constrained implantable biomedical devices. This paper presents 8, 16 and 32-bit ultra-low power robust
Kogge-Stone adders with improved performance. These adders operate at subthreshold supply voltages
which can be used for low power implantable bio-medical devices such as pacemakers. To improve the
performance of these adders in sub-threshold region, forward body bias technique and multi-threshold
transistors are used. The adders are designed using NCSU 45nm bulk CMOS process library and the
simulations were performed using HSPICE circuit simulator. Quantitative power-performance analysis is
performed at slow-slow (SS), typical-typical (TT) and fast-fast (FF) corners clocked at 50 KHz for
temperature ranging from 25̊C to 120̊C. For a supply voltage 0.3V, all the adders had the least PDP. Using
0.3V as the supply voltage, multi threshold voltage and forward body biasing techniques were applied to
further improve the performance of the adders. The PDP obtained using the forward body biasing
technique shows an effective improvement compared to high threshold voltage and multi threshold voltage
techniques. The forward biasing technique maintains a balance between delay reduction and increase in
average power, thus reducing the power delay product when compared to the other two techniques.
GENERIC SYSTEM VERILOG UNIVERSAL VERIFICATION METHODOLOGY BASED REUSABLE VERI...VLSICS Design
In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and verification of corner cases through pseudo random test scenarios is required. Also, standardization of verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP
level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
This document discusses BICMOS technology. It begins by justifying the need for transistors and explaining the progression from vacuum tubes to BJT to FET to BICMOS. BICMOS combines bipolar and CMOS technologies, allowing designers to use both device types on a single integrated circuit. This provides benefits like high speed, gain, and driving capability from bipolar devices, along with low power and high density from CMOS. Key uses of BICMOS include high-performance microprocessors and mixed-signal circuit design. The document covers basic BICMOS circuitry and switching behavior, as well as applications like input/output and sample and hold circuits.
Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction...IJECEIAES
To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 µW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 µW while CVSL shows total power consumption of 18.94 µW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCU...VLSICS Design
This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.
A Review of Analysis and Modeling of Grid Connected Three Phase Multilevel Un...IRJET Journal
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WeTestAthens: Postman's AI & Automation Techniques
D41022328
1. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
RESEARCH ARTICLE
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OPEN ACCESS
High Speed Boosted Cmos Differential Logic for Ripple Carry
Adders
Meenu Roy1, N.Kirthika2
1
2
PG Scholar, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore.
Assistant Professor, Department of VLSI Design, Sri Ramakrishna Engineering College, Coimbatore.
ABSTRACT
This paper describes a high speed boosted CMOS differential logic which is applicable in Ripple Carry Adders.
The proposed logic operating with supply voltage approaching the MOS threshold voltage. The logic style
improves switching speed by boosting the gate-source voltage of transistors along timing critical signal path. It
allows a single boosting circuit to be shared by complementary outputs as a result the area overhead also
minimizes. As compared to the conventional logic gates the EDP (energy delay product) is improved. The test
sets of logic gates and adders where designed in tsmc0.18μm of Mentor Graphics EDA tool. The experimental
result for Ripple Carry Adders using the proposed logic style revealed that the addition time is reduced as
compared with the conventional CMOS circuits.
Keywords- Adder, low power, low voltage, voltage boosting.
I.
INTRODUCTION
Low voltage design may offer a benefit in
terms of flexibility in power sources i.e. different
battery options. Low voltage does not necessarily
imply low power; the power consumed by a gate is
proportional to the active current driving the output of
the gate. Hence, delay and power consumption are
both dependent on the current [1]. Energy or power
delay product is not significantly dependent on the
current. Energy required to toggle a bit is more
dependent on the load and configuration of the gate.
Energy Delay Product (EDP) is more dependent on
speed than power and will be improved by increasing
the current for a specific supply voltage. Optimal
supply voltage for CMOS logic in terms of EDP is
close to the threshold voltage of nMOS transistor for
specific process. Thus current increased, the Energy
Delay Product (EDP) also increased and by the way,
the speed is also increased. The current level can be
increased by using different initialization voltages to
the gates.
Bootstrapping is an efficient technique for
speed enhancement and power reduction. One of the
popular ways of reducing the power consumption of a
CMOS digital circuit is to scaling down the supply
voltage. This is mainly because the switching power
consumption of the circuit has a quadratic dependency
on supply voltage. In the extreme case, the circuit can
be made to be operated in the sub threshold region for
maximum energy efficiency [2, 3]. However this
approach is limited to be only used in a low-end
design, where speed is the secondary concern, because
of severe speed degradation due to small switching
current and high performance variability due to
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process, temperature and threshold voltage variations
[4]. For medium and high end design, where speed
performance and energy efficiency are both important,
that much aggressive voltage scaling is not acceptable,
and thereby, a near-threshold voltage design is more
suitable for achieving relatively high energy efficiency
without severe speed degradation.
As the supply voltage scales down toward the
threshold voltage, the speed performance of
conventional CMOS circuits, such as the static CMOS
logic, the differential cascade voltage switch (DCVS)
logic[5] [see Fig. 1(a)], and the domino CMOS
logic[6] [see Fig. 1(b)], is still severely degraded due
to the reduced overdrive voltage (VGS − VTH) of
transistors. To overcome this problem, a bootstrapped
CMOS large capacitive-load driver[7] was proposed.
It was a solution to the speed degradation problem. It
can improve the switching speed at low supply voltage
by allowing the voltage of some internal nodes to be
boosted beyond the supply rails. And here two
capacitors are used for bootstrapping purpose. One
capacitor for pull up bootstrap circuit and another for
pull down bootstrap circuits. However, since the
circuit was proposed for use as a large capacitive-load
driver, logic functions cannot be efficiently embedded
into the circuit and the speed advantage was not fully
exploited. And there is an inefficiency in terms of
boosted voltage generation due to the driver uses only
one bootstrap capacitors for each bootstrapping
operation despite having dual bootstrap capacitors in
the circuit. For fast logic operation at low supply
voltage, CMOS bootstrapped dynamic logic (BDL)[8]
[see Fig. 1(c)] was proposed. However, the speed of
this logic style was not so much improved since the
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2. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
latency of bulky bootstrapping circuit was
superimposed on the overall latency of the circuit.
And moreover, logic composition of this logic style is
constrained since it is configured as a single ended
structure. Although some recent circuit techniques
adopting bootstrapped operation have been proposed,
they are all not for logic composition but for large
capacitance driving [9, 10]. And all proposed ones
requires larger area [11].
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To overcome the aforementioned problems
and to further improve the switching performance, a
novel boosting CMOS differential logic style is
proposed in this paper. It also minimizes the area and
also eliminates the problem of inefficiency. And the
latency problem can be solved by giving the voltage
boosting block directly to the differential logic tree.
Section II describes the circuit structure and operation
of the proposed logic style. In Section III, comparison
results for some representative logic gates are
presented to assess the performance of the proposed
logic style. In section IV, describes the experimental
result for 64-bit adders as a design example to prove
the practicality of the proposed logic style. And
finally, present the conclusion in Section V.
Fig. 1. Conventional digital CMOS circuits. (a)
DCVS. (b) Domino CMOS logic. (c) BDL.
Fig.2 Proposed BCDL. (a) Structure. (b) Simulated waveforms.
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24 | P a g e
3. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
II.
CIRCUIT STRUCTURE AND
OPERATION
Fig.2(a) shows a generic structure of the
proposed logic style, i.e., boosted CMOS differential
logic (BCDL). BCDL consists of a precharged
differential logic block and a voltage-boosting block.
The voltage-boosting block, which is shown in the
dotted box at the bottom part of the circuit, is
composed of transistors MN2, MN3, and MP3 and
boosting capacitor CBOOT which is used to boost the
voltage of NP below the ground.
The precharged differential logic block,
which is composed of a differential logic tree with
bottom transistor MN1, precharge transistors MP1 and
MP2, and output inverters which receives the boosted
voltage at NP and swiftly evaluates the output logic
values. Let us explain the operation of BCDL. BCDL
has two phases of operation, namely, a precharge
phase and a boosted evaluation phase. When the CLK
is low the circuit is in the precharge phase. During this
phase, the precharged differential logic block is
separated from the voltage-boosting block since MN1
is fully off. Precharge nodes P and PB in the
differential logic block are then precharged to the
supply voltage by MP1 and MP2, letting outputs OUT
and OUTB identically low. At the same time,
transistors MP3 and MN2 in the voltage-boosting
block turn on, allowing NS and NP to be high and
low, respectively. Then, a voltage identical to the
supply voltage is applied across CBOOT. When CLK
changes to high, the circuit goes into the boosted
evaluation phase.
The simulated waveforms of BCDL in this
phase are shown in Fig. 2(b), where a 0.5V supply
voltage is used. Since CLK goes high, MN1 turns on
and connects the differential logic tree to the voltageboosting block. At the same time, NS is pulled down
toward the ground, and by capacitive coupling through
CBOOT, allowing NP and NT to be boosted below the
ground. As shown in Fig. 2(b), NP temporally reaches
−250 mV and settles at around −200 mV by the
boosting action. Then, the gate–source voltages of
MN1 and transistors that are on in the logic tree are
enlarged this resulting in an increased driving strength
of these transistors. And moreover, a slightly forward
source–body voltage established in these transistors by
boosting source voltages below the ground leads to a
reduction in threshold voltages of these transistors,
further increasing their driving strength. In turn, the
boosted voltage at NT is then transferred to P or PB
through the logic tree, depending on input data. [In
Fig. 2(b), input data are such that PB is pulled down
below the ground]. The gate–source voltage of the
driver pMOS transistor is also enlarged and this
enhances its driving strength. Along the timing-critical
signal paths from the inputs to the outputs via
precharge nodes all these driving strength-enhancing
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effects by boosting are combined together, resulting in
significantly improved switching speed at a lowvoltage region.
Figure.3 shows the conventional CMOS 28transistor adder. I am using this circuit for Differential
logic tree and logic tree block for Fig. 1(a) and Fig.
1(b). The CMOS structure combines PMOS pull-up
and NMOS pull-down networks to produce considered
outputs. In this style all transistors (either PMOS or
NMOS) are arranged in completely separate branches
and each may consist of several sub-branches. The
mutually exclusiveness of pull-up and pull-down
networks is of a great concern. One possible
implementation of the full adder is the Mirror Full
Adder. The mirror full adder circuit device consists of
28 total transistors (4 transistors used for the
construction of two inverters). Hence the full adder
acts as a fundamental building-block component to
larger circuits units, timing and power consumption
optimization efforts at the adder level can lead to
improved circuit throughput ratings, enhanced speed
performance, and lowered power consumption
requirements. Therefore, at this fundamental level it is
very important to minimize latency and resolve any
timing issues in order to avoid issues inevitably
brought about by scaling.
Fig.3. Conventional CMOS Full Adder.
III.
SIMULATION COMPARISON
To assess the performance of the proposed
circuit technique, various multi-input logic gates are
designed using the conventional and proposed logic
styles in a tsmc0.18-μm of Mentor Graphics EDA
tool. The nominal threshold voltages of p- and nchannel MOS transistors are −0.45 and 0.42 V,
respectively. The boosting capacitor was implemented
using the gate-oxide capacitance of a pMOS transistor.
Transistor widths in each logic gate and the amount of
boosting capacitance were individually optimized at
each supply voltage for each logic style to provide a
minimum energy–delay product (EDP).
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4. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
Table.1: Simulated Power, Delay and Area of circuits
CIRCUITS
POWER
DELAY
AREA
in mW
in μm²
DCVS
8.6754
49.584 Ns
1540
DOMINO
4.3589
49.860 Ns
1320
BDL
4.013
49.504 Ns
1540
BCDL
1.4473
176.78 Ps
792
The Table .1 summarizes the simulated
performance of various logic gates designed with the
conventional and proposed logic styles. The
simulation was executed at 100-MHz frequency with a
supply of 1.8V. In the domino CMOS and BDL, only
the non-inverting outputs are available. For Full adder
which having the same input counts designed with
differential logic styles, the BCDL gates has larger
energy as compared with domino CMOS and DCVS
gates due to the extra circuit to perform the boosting
operation, it consumes still less energy than BDL
gates. In case of EDP, BCDL gates show the best
performance, improvement over the conventional
logic gates. The fig.4 shows the power, delay and area
analysis in different types of circuits such as DCVS,
DOMINO, BDL, BCDL.
2000
1500
DCVS
1000
DOMINO
500
BDL
0
BCDL
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The above Fig.5 shows the output waveform
obtained for the proposed BCDL logic with carry
chain of Full adder in the Differential logic tree. Then
the comparison of the both BDL and BCDL logic are
performed at different voltages to show that BCDL
has a more amount decreasing delay at low voltages
compared with BDL logic. Thus it is proved that the
proposed BCDL logic has high performance at low
voltages as compared with existing logic.
IV.
EXPERIMENTAL RESULT
To demonstrate practical applicability of the
proposed logic style, a set of ripple carry adders were
designed. The 64-bit adder consisting of eight 8-bit
adder subsections adopts the carry selection scheme
for high-speed carry propagation. In BCDL Adder an
8-bit ripple carry chain was used to allow boosting
operation at each carry chain stage, whereas an 8-bit
Manchester carry chain was used in the DCVS and
BDL adders for high-speed carry propagation. Fig. 6
shows the structure of the 8-bit ripple carry chain used
in the 64-bit BCDL adder.
At 1.8-V supply voltage, the 1-bit ripple
carry chain in the BCDL adder requires 2.14 ns for
propagating a carry value from the lowest to the
highest bit positions, whereas the 1-bit carry chains in
the DCVS and BDL adders require 8.96 and 7.48 ns,
respectively, indicating 76% and 72% improvements.
In 1 bit ripple carry adder chain the average power
consumed is 2.595673milliwatts, power delay product
is 5.521305𝑒 −008 and Energy delay product is
30.49090616𝑒 −016 .The experimental result for ripple
carry adders is performed one by one. First 1 bit
BCDL ripple carry adder is designed and simulated
and obtained corresponding results the continue 2 bit,
4 bit, 8 bit ,16 bit and so on BCDL ripple carry adders.
Fig.4. Power Comparison Chart.
Fig.6. 64 Bit Ripple Carry Adder
Fig.5 Waveform of BCDL with full adder carry chain
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26 | P a g e
5. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
www.ijera.com
Fig.7. Structure of a ripple carry chain in BCDL.
Fig.9. Waveform of BCDL Ripple Carry Adder.
DELAY
Fig.8. 2 bit BCDL ripple carry adder in
schematic window
In Fig.8 the rectangular block is the symbol
created for 1 bit ripple carry adder which is shown in
Fig.7. Hence the both symbols for 1 bit adder forms 2
bit and similarly all the bits upto 64 bit has been
created by calling the symbol with respect to
corresponding bits.The power, EDP, and PDP levels
all are reduced compared to Exciting methods of
DCVL, DOMINO CMOS, BDL. In BCDL, the
outgoing carry from each 8-bit subsection goes into
block-carry generators (BCG). There is a pair of
BCGs in each 8-bit subsection in the upper half of the
adder, and block carries are selected using the carry
bit propagated from the lower half. The measured
propagation delay and Switching energy of the BCDL
adder depending on supply voltage are summarized in
Table 2.
Table.2. Measured Delay at various voltages of
BCDL ripple carry adder
VOLTAGE in 3.3
3.0
2.6
1.8
V
DELAY in Fs 8.4808 7.3387 6.2817 3.6234
10
8
6
4
2
0
DELAY
3.3
3
2.6
1.8
VOLTAGES
Fig.10 Graph to show decrease in delay at low
voltages
Fig.11 Layout of BCDL adder
The schematic is drawn in Mentor Graphics
Pyxis window and is simulated by creating a symbol
to the schematic. As per the simulation using Mentor
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27 | P a g e
6. Meenu Roy et al Int. Journal of Engineering Research and Applications
ISSN : 2248-9622, Vol. 4, Issue 1( Version 2), January 2014, pp.23-28
Graphics EDA tool using the tsmc 180nm technology
it is proved that the proposed has increased speed as
compared to the existing works. And its practical
application shows that in low voltages also the delay is
decreasing which means that at low voltage also the
expected speed can be achieved by the proposed
BCDL.
[7]
[8]
V.
CONCLUSION
CMOS differential logic style with voltage
boosting has been described. The BCDL provides
higher switching speed than the conventional logic
style at low supply voltage. By allowing a single
boosting circuit to be shared by complementary
outputs the BCDL minimizes the area overhead.
Comparison results in a 0.180-μm technology of
Mentor Graphics EDA tool indicated that the energy–
delay product of the proposed logic style was
improved when compared with conventional logic
styles. Here present two high-speed and low-power
full-adder cells designed. Logic styles that lead to
have a reduced power-delay product (PDP). The
experiment result for a adder designed with BCDL
logic style revealed an reduction in the addition time.
The practical application in ripple carry adder proves
that it can operate in low supply voltages with a
decrease in propagation delay. So BCDL is a best
choice for adders especially for ripple carry adders
which is the slowest among all the adders.
[9]
[10]
[11]
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