ADVANCES IN VLSI DESIGN12EC009 CHAPTER-6 SUPERBUFFERS, BI-CMOS AND STEERING LOGIC

1. ADVANCES IN VLSI DESIGN
12EC009
CHAPTER-6
SUPERBUFFERS,
BI-CMOS
AND
STEERING LOGIC
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2. INTRODUCTION
• Used to drive large capacitive loads
• Either a large pad Or long line
• Bonding pads to interface and Probe pads to test,
both present heavy capacitive loads
• Long line – delay proportional to square of its
length
• Types: Inverting or non-inverting, NMOS or CMOS
• Alternatives: Bi-CMOS, NMOS or PMOS pass
transistors
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3. RC DELAY LINES
• Delay depends on
Resistance of the segment driving it
Capacitance of the segment it drives
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4. Superbuffers
A Superbuffer
 A symmetric Inverter or ratioless
Can supply or remove large currents
Switch large capacitive loads faster than a standard
inverter
Consisting of totem-pole or Push-Pull
NMOS SB design:
the gate bias
twice than
standard pull-up
inverter
So Trise = Tfall
CMOS SB design:
Pull-up ratio twice
the pull-down ratio
So Trise = Tfall
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5. Stick diagrams
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6. NMOS Super Superbuffer
Its a combination of Inverting and non inverting superbuffers
Inverting – Q1A through Q4A and Non-Inverting – Q1B through Q4B
Totem pole output stage Q5 and Q6
Q3A, Q3B, Q5
are zero
threshold
devices
This is faster
and
Exhibits low
power
consumption
under No-
Load
condition
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7. NMOS Tristate Superbuffer
Tristate drivers Desirable to :
 Multiplex a bus
 Drive large capacitive loads such as pads
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8. Cont....
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9. CMOS Superbuffers
Its A...
wide channel CMOS inverter or
Pair of Inverters
When EN is True
Q1B,Q3B Are OFF
Q2B,Q2A are ON
VO1 AND VO2 = Vin BAR
When EN is False:
Q2B, Q2A Are OFF
VO1 = HIGH
VO2 = LOW
This forces Pad-driver
totem pole to be OFF
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10. Bi-CMOS
• Combination of Bipolar and MOS technology
• Used for line drivers and sense amplifiers
• CMOS – Low power dissipation
• Bipolar – Low propagation delay and driving
capability
• MOS devices provide high input impedance
and BJT provides current drive and low output
impedance
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11. Cont....
Figure (a)
If input is high, Pull-down FET short
circuits the base of Q2 to collector
and Pull-up FET is Off, Q1 has no base
drive, High resistance at plus rail,
resulting in a low output value,
reverse happens when input is low
Figure (b)- Improved bi-CMOS
inverter
Q4 turns ON when the input signal
goes high, pulling node a down
discharging Q1 quickly. As the
potential at node a drops,Q6 is
turned OFF, allowing Q5 to drive Q2
on hard and pull the output low.
When input goes low,Q3 turns ON
while Q4 turns OFF,Q1 turns ON fast
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12. Bi-CMOS implementation of 2-input
NAND gate and 2-input NOR gate
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13. Dynamic Ratioless Inverters
• Precharging used to
improve the switching
performance
• Output can be precharged
high and selectively
discharged low
• It requires minimum two
clock phases
• The bus can be pulled all
the way up to VDD
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14. Pass Transistor Logic
• NMOS or PMOS, or a CMOS
transmission gate can be used
to steer or transfer charge
from one node of a circuit to
other node, under the control
of FETs gate voltage
• These chins are used in
designing arrays such as
ROMs, PLAs, and multiplexers
• Two major advantages
– Not ratiod devices and
minimum geometry
– Do not dissipate standby power
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15. Design rules
• One pass transistor never
the gate of an other pass
transistor
• If D signal drops from 5 to 0
V ,then input to the inverter
changes from 3.5 V to -1.5
V, so charging and
discharging paths should be
provided
• If any one pass transistor
turns off, a low will be
latched to the inverter
• Charge sharing and sneak
path are other problems
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16. Designing pass transistor logic
Strong one 4.5-5.0 V
Weak one 3.5-4.5 V
Weak zero 0.5-1.5 V
Strong zero 0.0-.5 V
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17. Cont...
CMOS Devices
• CMOS is superior to
NMOS
• They output both strong
one and strong zero
• Two transistors are
connected in parallel, it
has about half the
resistance of a single pass
transistors
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18. Cont...
Pass transistor 2-input NAND
Gate
Pass transistor 2-input NOR
Gate
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19. General functional blocks
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20. NMOS Function Blocks
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21. 2-input functional block
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22. NOR and NAND structures
NMOS ex-OR gates with fixed
inputs
Stick drawings of NMOS pass
transistor two variable function blocks
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23. CMOS Function blocks
• This implements 16
logic functions with two
input variables A and B,
4 control inputs C0 to
C3
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24. THANK YOU
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