The document discusses pass transistor logic (PTL), explaining how NMOS and PMOS transistors operate to transfer charge between input and output nodes and defines strong and weak logic levels. It describes the limitations and advantages of PTL in circuit design, emphasizing applications like universal logic modules and multiplexers. Additionally, it includes exercises for designing specific pass-transistor circuits like a three-input majority gate and a priority encoder, illustrating the practical application of the concepts discussed.

1. L E C T U R E : O C T O B E R 9 T H , 2 0 1 7
Pass Transistor Logic

2.  PTL uses a NMOS or PMOS transistor to transfer charge
from input node to the output node, under the control of
gate voltage. The output remains in High impedance
state when gate voltage is zero.
 Pass Transistor circuits are widely used in design of
ROMs, PLAs, multiplexers etc

3. Defining STRONG and WEAK logic
 Strong ‘1’: An output very close to the positive supply rail (VDD)
 Weak ‘1’: An output voltage that is above VIH but lower than a Strong ‘1’
 Strong ‘0’: An output very close to the negative supply rail (Vss)or Gnd
 Weak ‘0’: An output that is below VIL but higher than a Strong ‘0’
.
Signal Range (in Volts)
Strong ‘1’ 4.5-5
Weal ‘1’ 3.5-4.5
Weak ‘0’ 0.5-1.5
Strong ‘0’ 0.0- 0.5

4. NMOS pass transistor passes Strong ‘0’ but weak ‘1’
 An NMOS pass-transistor can pull down to the negative
rail, but it can pull-up to a threshold voltage below the
positive rail.
 => It can output a strong zero, but a weak one.
Why???

5. NMOS pass transistor passes Strong ‘0’ but weak ‘1’
 For an NMOS to pass Logic ‘1’, the node Vs gets
gradually charged from 0 towards VDD .
 When Vs reaches VDD-Vt,n then
VGS=(VG- VS) = VDD-(VDD-Vt,n) = Vt,n
which is the minimum voltage required for the
NMOS to be ON state for a current to flow.
 So node out reaching to a potential more than VDD-
Vt,n turns off the NMOS.

6. PMOS pass transistor passes Strong ‘1’ but weak ‘0’
 An NMOS pass-transistor can pull down to the
positive supply rail, but it can only pull-down to a
threshold voltage above the negative rail.
 => It can output a strong zero, but a weak one.
Why???

7.  Similarly for a PMOS to pass logic ‘0’, gate should be
logic 0 and the output node should be gradually
discharged from its previous value to zero potential.
 In this process when output node reaches |Vt,p| then
|VSG| reaches (|Vt,p|-0) which is the minimum voltage
required for the PMOS to be ON state for a current to
flow. So node out reaching to a potential less than Vt,p
turns off the PMOS.
 So the maximum voltage level that the output node can
be discharged to is |Vt,p|

8. Strong and Weak Logic Summary
nMOS passes a strong Logic ‘0’ but a degraded Logic ‘1’. The opposite is true for pMOS

9.  The source voltage is always the lower of voltages
VD and VG-VT

10.  Three pass-transistors driving an inverter are shown. Let the threshold
voltage of each transistor be 1.5V. Then the node voltages are as shown.
 With the gate and drain of 1st pass-transistor at VDD, its source rises to
3.5V. And the device is at onset of pinching-off. The 2nd pass-transistor
has gate at 5V and drain at 3.5V, its source rises to drain potential of
3.5V. This is repeated along the chain. This is called charge steering.

11.  Circuit Limitation:
The voltage presented to the inverter input is only 3.5V. This
must be sufficient to drive the inverter output low.

12. General function Block
 One application of pass-transistor logic is the
universal Logic Module, also called General Function
Block.
 Various functions can be obtained from the same
circuit by changing Control and Logic Inputs

13. 2-input NAND gate

14. 2-input NOR gate

16. 2 X 1 Multiplexer

17. Advantages of Pass-Transistor Logic
 They are not ratioed devices and can be minimum
geometry
 They do not have a path from VDD to ground and do
not dissipate stand-by power

18. Limitations
 A sneak path is created when two pass-transistors
are both ON at the same time and one is connected
to VDD and the other is connected to ground.

19.  Design Constraints
 Issue with discharge path
 Charge sharing

20. Exercise 1
 Design a pass-transistor circuit for a three-input
majority gate. The output of a 3-input majority gate
is true if atleast two-inputs are true. The controls are
A and B. Show the Karnaugh map and a circuit
diagram.

21. Exercise 2
 Draw a pass-transistor circuit for the priority encoder whose truth
table is given below. The controls are A and B. Show the Karnaugh
Map and a circuit diagram. Realize Y1 and Y2 simultaneously.
Which form of pass-transistor is better suited for this realization,
and why?
 .
Input Output
A B C Y1 Y0
0 0 0 0 0
0 0 1 0 1
0 1 0 1 0
0 1 1 1 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1