The presentation covers synchronous sequential circuit elements; latch and Flip flops, SR Flip flop, JK Flip flop, T flip flop, D Flip flop, race around condition, Edge triggered flip flop
The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.
The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.
The following presentation is a part of the level 4 module -- Digital Logic and Signal Principles. This resources is a part of the 2009/2010 Engineering (foundation degree, BEng and HN) courses from University of Wales Newport (course codes H101, H691, H620, HH37 and 001H). This resource is a part of the core modules for the full time 1st year undergraduate programme.
The BEng & Foundation Degrees and HNC/D in Engineering are designed to meet the needs of employers by placing the emphasis on the theoretical, practical and vocational aspects of engineering within the workplace and beyond. Engineering is becoming more high profile, and therefore more in demand as a skill set, in today’s high-tech world. This course has been designed to provide you with knowledge, skills and practical experience encountered in everyday engineering environments.
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
synchronous Sequential circuit counters and registersDr Naim R Kidwai
The presentation covers, synchronous sequential circuits; registers and counters. design of registers, shift registers are explained. Design of counter, synchronous and ripple counter is demostrated.
The presentation covers asynchronous sequential circuit analysis; Map, transition table, flow table. It also covers asynchronous circuit design process and race conditions
The document explains about the concepts of sequential circuits in Digital electronics.
This will be helpful for the beginners in VLSI and electronics students.
synchronous Sequential circuit counters and registersDr Naim R Kidwai
The presentation covers, synchronous sequential circuits; registers and counters. design of registers, shift registers are explained. Design of counter, synchronous and ripple counter is demostrated.
The presentation covers asynchronous sequential circuit analysis; Map, transition table, flow table. It also covers asynchronous circuit design process and race conditions
JK flip flop in Digital electronics
You can watch my lectures at:
Digital electronics playlist in my youtube channel:
https://www.youtube.com/channel/UC_fItK7wBO6zdWHVPIYV8dQ?view_as=subscriber
My Website : https://easyninspire.blogspot.com/
The Reason Why we use master slave JK flip flop instead of simple level triggered flip flop is Racing condition which can be successfully avoided using two SR latches fed with inverted clocks.
The presentation covers clocked sequential circuit analysis and design process demonstrated with example. State reduction and state assignment is design is also described.
The presentation covers sampling theorem, ideal sampling, flat top sampling, natural sampling, reconstruction of signals from samples, aliasing effect, zero order hold, upsampling, downsampling, and discrete time processing of continuous time signals.
The presentation covers financial feasibility of projects, payback analysis, NPV analysis or discounted cash flow analysis, IRR analysis, Benefit to cost ratio analysis, B/C pitfalls, ROI
The presentation covers infrastructure project financing, typical configurations, key project parties, project contracts, It explains financing of a power project, security mechanism, SPV payment hierarchy and risk mitigation mechanism
The presentation covers project financing, capital structure, key factors in determining debt equity ratio, menu of financing, sources of capital, internal accruals, equity capital, preference capital, debenture or bonds, methods of offering, term loan, working capital advances, project financing structures,
The presentation covers project constraints: project dependence, capital rationing, project invisibility. It covers comparing project under constraints: methods of ranking, ranking conflicts,
Nec 602 unit ii Random Variables and Random processDr Naim R Kidwai
The presentation explains concept of Probability, random variable, statistical averages, correlation, sum of random Variables, Central Limit Theorem,
random process, classification of random processes, power spectral density, multiple random processes.
The presentation describes Measures of Information, entropy, source coding, source coding theorem, huffman coding, shanon fano coding, channel capacity theorem, capacity of a discrete and continuous memoryless channel, Error Free Communication over a Noisy Channel
Rec101 unit ii (part 2) bjt biasing and re modelDr Naim R Kidwai
The presentation covers BJT Biasing: Operating Point or Q point, Fixed-Bias, Emitter Bias, Voltage-Divider Bias, Collector Feedback bias, Emitter-Follower bias, common base bias, bias Stabilization and re model of CB/ CE/ CC configuration
The presentation covers, Field Effect Transistor: Construction and Characteristic of JFETs, dc biasing of CS, ac analysis of CS amplifier, MOSFET (Depletion and Enhancement)Type, Transfer Characteristic
The presentation covers Bipolar Junction Transistor: Construction, Operation, Transistor configurations and input / output characteristics; Common Base, Common Emitter, and Common Collector
The presentation explains elements of communication system, need of the modulation, types of modulation, basic signals, fundamentals of amplitude modulation/ demodulation, envelope detector, DSB_SC, SSB, VSB and comparison of modulation techniques
The presentation covers digital Voltmeter, RAMP Techniques, digital Multi-meters. It also covers Oscilloscope; Introduction and Basic Principle, CRT, Measurement of voltage, current, phase and frequency using CRO, Introduction of Digital Storage Oscilloscope and its comparison over analogue CRO
The presentation describes diode application; series / parallel diode configuration, half wave and full wave rectifier, clipper, clamper, zener diode as a shunt regulator, voltage multiplier
The presentation explains working of pn junction diode, V-I characteristics, breakdown mechanism, ac and dc resistance, diode capacitance, effect of temperature and equivalent circuit. It also covers special diodes, LED, Varicap diodes, Tunnel diode, and working of LCD
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Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
1. Sequential Circuit
16-03-2019 1
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
A Sequential circuit is a combinational circuit with memory or storage element in feedback
i.e Sequential circuit’ output depends on inputs as well as previous state of storage element.
Synchronous Sequential Circuit: Behaviour of the system depends on inputs (external and
internal state) only at discrete instants of time. Storage elements used are clocked Flip Flops
Asynchronous Sequential Circuit: Behaviour of the system depends on inputs (external and
internal state) at any time. Storage element used are time delay elements and latches
Combinational
Circuit
Memory
Element
Input Output
Sequential Circuit
2. Latch
16-03-2019 2
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
R
S
Q
Q
SR Latch using NOR gate
Full State table of SR FF
S R Qn+1 S R Qn Qn+1
0 0 Qn No Change
0 0 0 0
0 0 1 1
0 1 0 Reset
0 1 0 0
0 1 1 0
1 0 1 Set
1 0 0 1
1 0 1 1
1 1 Invalid
1 1 0 invalid
1 1 1 invalid
•Latch holds 1 bit of information
•Two outputs are complementary
•Inputs are S and R which Sets ( output 1) and Resets (output 0) the latch
• S=R=1 is invalid in which rule of complementary output breaks
3. SR Flip Flop
16-03-2019 3
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
Full State table of SR FF
S R Qn+1 S R Qn Qn+1
0 0 Qn No Change
0 0 0 0
0 0 1 1
0 1 0 Reset
0 1 0 0
0 1 1 0
1 0 1 Set
1 0 0 1
1 0 1 1
1 1 Invalid
1 1 0 invalid
1 1 1 invalid
•In Latch, spurious inputs can cause output change at time.
•A clock pulse (in AND to inputs) ensures that inputs are
applied only when clock pulse is present
R
S
Q
Q
SR FF
CLK
R
S
CLK
Q
Q
SR Flip Flop symbol
1and;
)7,6(5,4,1),,(
1
1
SRQRQSQ
QKJQ
nn
nn
SR Characteristics equation
4. JK Flip Flop
16-03-2019 4
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•JK is modification of SR FF for invalid input combination
•For J=K=1, output Toggles (complements)
K
J
CLK
Q
Q
JK Flip Flop symbol
R
S
CLK
Q
Q
J
K
nQ
nQ
nnn
nn
QKQJQ
QKJQ
1
1 6,5,4,1),,(
JK Characteristics equation
Full State table of JK FF
J K Qn+1 J K Qn Qn+1
0 0 No Change
0 0 0 0
0 0 1 1
0 1 0 Reset
0 1 0 0
0 1 1 0
1 0 1 Set
1 0 0 1
1 0 1 1
1 1 Toggle
1 1 0 1
1 1 1 0
5. Full State table of T FF
T Qn+1 T Qn Qn+1
0 No Change
0 0 0
0 1 1
1 Toggle
1 0 1
1 1 0
T Flip Flop
16-03-2019 5
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•T FF is JK FF with J=K
•For T=1, output Toggles (complements)
T
CLK
Q
Q
T Flip Flop symbol
nQ
nQ
nnnn
nn
QTQTQTQ
QTQ
1
1 2,1),(
T Characteristics equation
K
J
CLK
Q
Q
T
6. Full State table of T FF
D Qn+1 D Qn Qn+1
0 0 Reset
0 0 0
0 1 0
1 1 Set
1 0 1
1 1 1
D Flip Flop
16-03-2019 6
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•D FF is JK FF with J=D and applying NOT gate between J and K
•Output is same as Data input (D)
D
CLK
Q
Q
D Flip Flop symbol
DQ
QDQ
n
nn
1
1 3,2),(
D Characteristics equation
K
J
CLK
Q
Q
T
7. JK Flip Flop: Race around condition
16-03-2019 7
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•when J=K=1, output toggles recursively during active period of clock pulse
•This leads to unpredictable output state after active period of clock pulse
• This condition is know as race around condition
K
J
CLK
Q
Q
JK Flip Flop symbol
CLK
J
K
Q
•Solution to race around condition
• Master slave FF: that gives a single trigger at slave output. How ever race around
condition occurs in Master.
•Edge triggered FF: flip-flop triggers the ‘edge’ of clock pulse
8. Edge Triggered Flip Flop
16-03-2019 8
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•Edge triggered FF considers input values at the edge of the clock
pulse (either positive or negative)
K
J
CLK
Q
Q
Positive Edge triggered JK FF
K
J
CLK
Q
Q
Negative Edge triggered JK FF
CLK
J
K
Q
•Timing diagram of typical positive edge triggered JK FF
9. Edge Trigger Circuit
16-03-2019 9
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
•Edge triggered FF considers input values at the edge of the clock
pulse (either positive or negative)
•Circuit generates a pulse train of pulse duration equal to delay time of invert gate
(comparable to rise time or edge duration of clock pulse)
• Narrow pulse duration allows only one input trigger in clock pulse
CLK
y
z
CLK
y
z
Positive edge pulse train
generation circuit
10. Conversion of Flip-flops
16-03-2019 10
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
T→JK FF conversion
• Requires design of additional combination circuit (as shown in figure)
T
CLK
Q
Q
T FF to JK FF Conversion
Additional
Combinational
circuit
J
K
Step 1: Write the desired state table (JK State table)
Step 2: Determine what should be value at available FF
input for desired state changes (what should be at T to
cause Qn→ Qn+1 using excitation table of T
Step 3: Write output of additional circuit (T) in SOP and
minimize using K map
Step 4: Implement the function
11. Conversion of Flip-flops
16-03-2019 11
Dr Naim R Kidwai, Professor, Integral University, Lucknow
www.nrkidwai.wordpress.com
T→JK FF conversion
J K Qn Qn+1 T
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 1 1
1 1 1 0 1
T FF excitation table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0KQ
QKJT n
nQJT
mapKusingSolving
)7,6,4,3(),,(
T
CLK
Q
Q
T FF to JK FF Conversion
J
K