ANALOG AND DIGITAL ELECTRONICS unit 5

DEPARTMENT OF
ELECTRONICS AND COMMUNICATION
ENGINEERING
Instructor
Mr. D V S RAMANJANEYULU
Assistant Professor
Accredited by NBA & NAAC with “A” Grade
CS301ES : ANALOG & DIGITAL ELECTRONICS

P.KIRAN KUMAR,ECE DEPARTMENT 2
UNIT - V
Sequential Logic Circuits: Sequential Circuits, Storage
Elements: Latches and flip flops, Analysis of Clocked
Sequential Circuits, State Reduction and Assignment,
Shift Registers, Ripple Counters, Synchronous Counters,
Random-Access Memory, Read-Only Memory.

Sequential Circuits
Every digital system is likely to have combinational circuits, most systems encountered in
practice also include storage elements, which require that the system be described in
term of sequential logic.

Difference between combinational and sequential circuits

Synchronous Clocked Sequential Circuit
A sequential circuit may use many flip-flops to store as many bits as necessary. The
outputs can come either from the combinational circuit or from the flip-flops or both.

SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or two
cross-coupled NAND gates. It has two inputs labeled S for set and R
for reset.

SR Latch with NAND Gates

SR Latch with Control Input
The operation of the basic SR latch can be modified by providing an additional
control input that determines when the state of the latch can be changed, it
consists of the basic SR latch and two additional NAND gates.

D Latch
One way to eliminate the undesirable condition of the indeterminate state in SR latch is
to ensure that inputs S and R are never equal to 1 at the same time in Fig 5-5. This is
done in the D latch.

Graphic Symbols for latches
A latch is designated by a rectangular block with inputs on the left and outputs on the
right. One output designates the normal output, and the other designates the
complement output.

Clock Response in Flip-Flop

Notion of Clock
• A clock is a periodic (repetitive) rectangular pulse train that synchronizes the
operation of a synchronous sequential circuit.
• For synchronous operation, the storage elements must be clock triggered.
– Flip-flops (as opposed to latches, which are level triggered).
CLK

Edge-Triggered Flip-Flop
• An edge-triggered flip-flop changes its state in synchronism with a clock pulse.
– Either at the positive-edge or at the negative-edge.
– Useful in the design of synchronous sequential circuits, where all changes in the
circuit outputs occur in synchronism with the clock.
CLK
ON period
OFF period
Time period f = frequency
T = time period
T = 1 / f

S
CK
Q
CK
R. Q’
Positive edge triggered
S. Q
R Q’
Negative edge triggered
CK S R Q Q’
0/1 X X NC NC
 0 0 NC NC
 0 1 0 1
 1 0 1 0
 1 1 ? ?
Edge-Triggered S-R Flip-Flop
Characteristic equation:
R.S = 0
Q(t+1) = R’.Q(t) + S
0 0 X 1
1 0 X 1
00 01 11 10
1
SR
Q(t)
0
Positive edge triggered state table

• Excitation table for S-R flip-flop:
Circuit changes Required value
From To S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0

D Q
CK
Q’
CK
D Q
Q’
CK D Q Q’
0/1 X NC NC
 0 0 1
 1 1 0
Edge-Triggered D Flip-Flop
Q(t+1) = D

• Excitation table for D flip-flop:
Circuit changes Required
value
From To D
0 0 0
0 1 1
1 0 0
1 1 1

Edge-Triggered J-K Flip-Flop
CK J K Q(t+1) Q(t+1)’
0/1 X X Q(t) Q(t)’
 0 0 Q(t) Q(t)’
 0 1 0 1
 1 0 1 0
 1 1 Q(t)’ Q(t)
• The J-K flip-flop is the most versatile flip-flop.
– Like in S-R flip-flop, it has two inputs J and K, but does not have any invalid inputs.
J. Q
CK
J. Q’

0 0 1 1
1 0 0 1
00 01 11 10
1
Q(t+1) = J.Q(t)’ + K’.Q(t)
JK
Q(t)
0
Circuit changes Required value
From To J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Excitation Table

Gate-Level Implementation of J-K Flip-Flop
CK acts like an enable input; edge detection circuit is not shown.

Edge-Triggered T Flip-Flop
T Q
CK
Q’
CK
T Q
Q’
CK T Q(t+1) Q(t+1)’
0/1 X Q(t) Q(t)’
 0 Q(t) Q(t)’
 1 Q(t)’ Q(t)
Q(t+1) = T  Q(t)

Circuit changes Required
value
From To T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
J
K
CK
Q
Q’
T

Master-Slave Flip-Flops
• A master-slave flip-flop has two latch stages, called Master and
Slave.
• Data gets stored in the Master stage one one edge or level of an
control signal (clock), and is transferred to the Slave on the other
edge or level of the control signal.
• Aims to address the problem in latches when the ENABLE signal
may cause multiple changes in the storage cell (for J-K and T
types).
• Suffers from a problem called 0’s catching and 1’s catching
that may be undesirable for many applications.
– Edge-triggered versions are preferred in such cases.

(a) S-R master-slave flip-flop

(b) D master-slave flip-flop

(c) J-K master-slave flip-flop

Converting One Flip-Flop Type to Another
reference class notes

• A register consists of a group of flip-flops with a common clock input, used for storing
binary data.
• Depending on the configuration, there can be several different variations:
a) Parallel-in parallel-out (PIPO)
b) Serial-in serial-out (SISO)
c) Parallel-in serial-out (PISO)
d) Serial-in parallel-out (SIPO)
• If the register supports serial-in and serial-out modes, it is also called a shift register.
Registers

Shift Register
• A shift register is a register in which the binary data can be stored, and the
data can be shifted to the left (or right) when a shift signal is applied.
– New bit gets shifted in; bit shifted out typically get lost.
• Can be constructed simply by connecting D, SR or JK flip-flops in cascade.
• A 4-bit shift register is shown below:
D1 Q1 D2 Q2 D3 Q3 D4 Q4
CLK
Serial In
(SI)
Serial
Out
(SO)

• Some shift registers have a shift enable signal SHIFT, which is used in the same
way as the LOAD signal of a PIPO register.
– Sample timing diagram is shown, assuming that the initial state is Q1Q2Q3Q4 =
0101.
CLK
SI
Q1
Q2
Q3
Q4
1
1
1
1 0
01
0
0
1
1
1
1
1
0
0
0
0 1
1

Universal Shift Register
Universal Shift Register
S1
S0
• A universal shift register is a bidirectional shift register,
whose input can be either in serial form or in parallel
form, and whose output can also be either in serial
form or in parallel form.
• D
• k
k
Q
Shift Right SI
Shift Left SI
CLK
Control
Inputs
Action
0 0 No change
0 1 Shift right
1 0 Shift left
1 1 Parallel load

D1 Q1 D2 Q2 D3 Q3
CLK
MUXMUXMUX
D1
Q2 Q1 Q3
D2 D3
SI
Q3 Q2 (left)
SI
Q1 (right) Q2
S1 S1 S1
S0 S0
S0
A 3-bit universal shift register

Ring Counter
• This is obtained from a SISO shift register by connecting the Q output of the
last flip-flop to the D input of the first flip-flop.
– Typically, a ring counter is initialized with a single 1 and all remaining 0’s.
– This can generate multi-phase clock, or sequence of synchronizing pulses.
• For a k-bit ring counter, the contents of the register gets repeated after k
clocks.
– Modulo-k counter.

D1 Q1 D2 Q2 D3 Q3
A 3-bit ring counter.
Assume the initial state
Q1Q2Q3 = 1 0 0.
CLK
CLK
Q1
Q2
Q3
Q1Q2Q3 generates non-overlapping pulse trains

TWISTED RING COUNTER (JOHNSON COUNTER)

ANALOG AND DIGITAL ELECTRONICS unit 5

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