This document discusses various types of flip-flops including RS, D, JK, T flip-flops. It describes their characteristic tables and excitation tables. It also covers sequential circuits, state tables, state diagrams, state equations, and the design of counters using flip-flops. Key topics include the use of flip-flops as memory elements, master-slave configurations to prevent race-around conditions, and how to analyze and design sequential circuits and counters.

1. Dr. Heman Pathak
Associate Professor
Dept. of Comp. Sc.
Kanya Gurukul Dehradun

2. Flip-flop / Latch
Flip-flop is a basic digital memory circuit, which stores one bit
of information. Flip flops are the fundamental blocks of most
sequential circuits. It is also known as a bistable multivibrator
or a binary or one-bit memory. Flip-flops are used as memory
elements in sequential circuit.

3. Flip-flop / Latch

4. Flip-flop
NOR: If one input is 1 output is 0
Output is 1 only when all inputs 0
Q S R Q(T+1) Q’(T+1)
0 0 0 0 1
0 0 1 0 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
1 1 0 1 0
1 1 1 0 0
S
R

5. Sequential Logic

6. Flip-flop
NAND: If one input is 0 output is 1
Output is 0 only when all inputs 1
S R Q(T) Q(T+1) Q’(T+1)
0 0 0 1 1
0 0 1 1 1
0 1 0 1 0
0 1 1 1 0
1 0 0 0 1
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

7. Flip-flop

8. Clocked R-S Flip-flop

9. Clocked R-S Flip-flop

10. Clocked R-S Flip-flop
S R Q(T+1)
0 0 Q(T)
0 1 0
1 0 1
1 1 Indeterminate

11. D Flip-flop
• The D (data) flip-flop is a slight modification of the SR flip-flop.
• An SR flip-flop is converted to a D flip-flop by inserting an
inverter between S and R and assigning the symbol D to the
single input.
• If D = 1, the output of the flip-flop goes to the 1 state,
but if D = 0, the output of the flip-flop goes to the 0 state .

12. D Flip-flop
S R Q(T+1)
0 0 Q(T)
0 1 0
1 0 1
1 1 Indeterminate
S R=S’ Q(T+1)
0 1 0
1 0 1

13. D Flip-flop

14. JK Flip-flop

15. JK Flip-flop

16. JK Flip-flop
 Because of feedback connection, for a given clock pulse, the
output will oscillate between '0' & '1' when both J & K are high.
 The condition is referred to as “race around”.

17. JK Flip-flop

18. Methods to eliminate race around
condition of JK Flip-flop
• The propagation delay (delta t) should be made greater than the duration of the
clock pulse (T). But it is not a good solution as increasing the delay will decrease
the speed of the system.
Increasing the delay of flip-flop
• If the clock is High for a time interval less than the propagation delay of the flip flop
then racing around condition can be eliminated. This is done by using the edge-
triggered flip flop rather than using the level-triggered flip-flop.
Use of edge-triggered flip-flop
• If the flip flop is made to toggle over one clock period then racing around condition
can be eliminated. This is done by using Master-Slave JK flip-flop.
Use of master-slave JK flip-flop

19.  T (toggle) flip-flop is obtained from a JK type when inputs J and
K are connected to provide a single input designated by T.
T Flip-Flop

20. T Flip-Flop

21.  In this type of flip-flop, output transitions occur at a specific
level of the clock pulse.
 When the pulse input level exceeds this threshold level, the
inputs are locked out so that the flip-flop is unresponsive to
further changes in inputs until the clock pulse returns to 0 and
another pulse occurs.
 Some edge-triggered flip-flops cause a transition on the rising
edge of the clock signal (positive-edge transition), and
 others cause a transition on the falling edge (negative-edge
transition).
Edge Triggered Flip Flops

22. Edge Triggered Flip Flops

23. Edge Triggered Flip Flops

24. This type of circuit consists of two flip-flops.
 The first is the master, which responds to the positive level of
the clock, and
 the second is the slave, which responds to the negative level
of the clock.
 The result is that the output changes during the 1-to-0
transition of the clock signal.
Master-Slave Flip Flop

25. Master-Slave RS-Flip Flop

26. Master-Slave RS-Flip Flop

27. Master-Slave JK-Flip Flop

28. Master-Slave JK-Flip Flop

29. Master-Slave JK-Flip Flop

31.  The characteristic tables of flip-flops specify the next state
when the inputs and the present state are known.
 During the design of sequential circuits we usually know the
required transition from present state to next state and wish
to find the flip-flop input conditions that will cause the required
transition.
 For this reason we need a table that lists the required input
combinations for a given change of state.
 Such a table is called a flip-flop excitation table.
Excitation Tables

32. Excitation Tables
 Excitation table consists of two columns, Q(t) and Q(t + 1), and a
column for each input to show how the required transition is
achieved.
 There are four possible transitions from present state Q(t) to next
state Q(t + 1).
 The required input conditions for each of these transitions are
derived from the information available in the characteristic tables.
 The symbol x in the tables represents a don't-care condition; that is,
it does not matter whether the input to the flip-flop is 0 or 1.

33. Excitation Tables-RS Flip Flop
Characteristic Table
Q S R Q(T+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Excitation Tables
Q(T) Q(T+1)
0 0
0 1
1 0
1 1
S R
0 X
1 0
0 1
X 0

34. Excitation Tables-JK Flip Flop
Characteristic Table
Q J K Q(T+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Excitation Tables
Q(T) Q(T+1)
0 0
0 1
1 0
1 1
J K
0 X
1 X
X 1
X 0

35. Excitation Tables-D Flip Flop
Characteristic Table
Q D Q(T+1)
0 0 0
0 1 1
1 0 0
1 1 1
Excitation Tables
Q(T) Q(T+1)
0 0
0 1
1 0
1 1
D
0
1
0
1

36. Excitation Tables-T Flip Flop
Characteristic Table
Q T Q(T+1)
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Tables
Q(T) Q(T+1)
0 0
0 1
1 0
1 1
T
0
1
1
0

37.  A sequential circuit is an interconnection of flip-flops and
gates.
 The gates by themselves constitute a combinational circuit,
but when included with the flip-flops, the overall circuit is
classified as a sequential circuit.
Sequential Circuit

38. Analysis of Sequential Circuit

39. Analysis of Sequential Circuit
How many Inputs, Outputs & Flip-flops
Input - 1 - x
Output - 1 - y
Flip-flops - 2 - A & B

41. State Table
 The behavior of a sequential circuit is determined from the inputs, the
outputs, and the state of its flip-flops.
 Both the outputs and the next state are a function of the inputs and the
present state.
 A sequential circuit is specified by a state table that relates outputs and
next states as a function of inputs and present states.

43. State Diagram

44. State Diagram
 The information available in a state table can be represented
graphically in a state diagram.
 In this type of diagram, a state is represented by a circle, and the
transition between states is indicated by directed lines connecting
the circles.
 The binary number inside each circle identifies the state of the flip-
flops.
 The directed lines are labelled with two binary numbers separated
by a slash.
 The input value during the present state is labelled first and the
number after the slash gives the output during the present state.

45. State Equation

46. State Equation
A B X A B Y
0 0 0 0 0 0
0 0 1 1 1 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 1 0
1 1 0 0 0 1
1 1 1 1 1 0

47. State Equation

48. Analysis of Sequential Circuit
How many Inputs, Outputs & Flip-flops
Input - 1 - x
Output - 1 - y
Flip-flops - 2 - A & B

49. Analysis of Sequential Circuit

50. Analysis of Sequential Circuit

51. Designing Sequential Circuits

52. Designing Sequential Circuits

53. Designing Sequential Circuits
How many Inputs, Outputs & Flip-flops
Input - 1 - x
Output - 0
No. of States - 4 - 22
Flip-flops - 2 - A & B

54. Designing Sequential Circuits

55. Designing Sequential Circuits

56. Designing Sequential Circuits

57. Designing Sequential Circuits

59. Designing of Counters
 A sequential circuit that goes through a predetermined sequence of
states upon the application of input pulses is called a counter.
 The input pulses may be clock pulses or may originate from an
external source.
 They may occur at uniform intervals of time or at random.
 Of the various sequences a counter may follow, the straight binary
sequence is the simplest and most straightforward.
 A counter that follows the binary number sequence is called a binary
counter.
 An n-bit binary counter contains n flip-flops and associated gates
that follows a sequence of states according to the binary count of n
bits, from 0 to 2n - 1.

60. Designing of Counters
How many Inputs, Outputs & Flip-flops
Input - 0
Output - 0
No. of States - 8 - 23
Flip-flops - 3 - A0, A1 & A2
Type of Flip flop - T

61. Designing of Counters
Present State Next State
A2 A1 A0 A2 A1 A0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

62. Designing of Counters
Present State Next State Flip flop Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

63. Designing of Counters

64. Designing of Counters

65. Designing of Counters
000
001
010
100
101
110

66. Designing of Counters

67. Designing of Counters
JA
ABC 00 01 11 10
0 0 0 X 1
1 X X X X
KA
ABC 00 01 11 10
0 X X X X
1 0 0 X 1
JB
ABC 00 01 11 10
0 0 1 X X
1 0 1 X X
KB
ABC 00 01 11 10
0 X X X 1
1 X X X 1
JC
ABC 00 01 11 10
0 1 X X 0
1 1 X X 0
KC
ABC 00 01 11 10
0 X 1 X X
1 X 1 X X

68. Designing of Counters

69. Designing of Counters

70. Design with State Equation

71. Designing of Counters
Present State Next State Flip flop Inputs
A2 A1 A0 A2 A1 A0 TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

72. Designing of Counters
Present
State
Next
State
A B C A B C
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0
A(T+1)
ABC 00 01 11 10
0 0 0 1 0
1 1 1 0 1
B(T+1)
ABC 00 01 11 10
0 0 1 0 1
1 0 1 0 1
C(T+1)
ABC 00 01 11 10
0 1 0 0 1
1 1 0 0 1
A(T+1) = A’BC + AB’ + ABC’
= A’BC + A(B’+BC’)
= A’BC + A[(B’+B)(B’+C’)]
= A’BC + A(BC)’
TA = BC
C(T+1) = C’
= 1.C’ + 0
= 1.C’ + 0.C
= 1.C’ + 1’.C
TC = 1
B(T+1) = B’C + BC’
TB = C

73. Designing of Counters

74. Design with State Equation
Present
State
Next
State
A B C A B C
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 0 0 0
1 1 1 0 0 0
A(T+1)
ABC 00 01 11 10
0 0 0 1 1
1 1 1 0 0
B(T+1)
ABC 00 01 11 10
0 0 1 0 0
1 0 1 0 0
C(T+1)
ABC 00 01 11 10
0 1 0 X 0
1 1 0 X 0
C(T+1) = B’C’
C(T+1) = C’B’ + 0
= C’B’ + 1’.B
JC = B’ KC =1
Q(T+1) = JQ’ + K’Q
A(T+1) = A’B + AB’
KA = B JA = B
B(T+1) = B’C
B(T+1) = B’C + 0
= B’C + 0.B
= B’C + 1’B
JB = C KB = 1

75. Sequential Circuit with D Flip flop

76. Sequential Circuit with D Flip flop

77. Sequential Circuit with JK Flip flop

78. Sequential Circuit with JK Flip flop

79. Sequential Circuit with JK Flip flop

80. Sequential Circuit with JK Flip flop

81. Sequential Circuit with JK Flip flop