This document discusses sequential logic circuits and memory elements. It describes latches and flip-flops, which are basic memory elements used in sequential circuits. Specifically, it covers the set-reset (SR) latch, D flip-flop, and JK flip-flop. It provides their logic diagrams, truth tables, and examples of how their output changes in response to different input patterns over time. Asynchronous preset and clear inputs are also discussed as additional control inputs for flip-flops.

1. TOPIC 4
Latch & Flip-flop

2. Logic circuits
Combinational
 i.e NAND, NOR, AND, OR, etc
 Depend on present inputs
Combinational
 i.e NAND, NOR, AND, OR, etc
 Depend on present inputs
Sequential
 D FF, JK FF, RS FF, etc
 Depends on present and previous inputs
 Made up of an assembly of logic gates
Sequential
 D FF, JK FF, RS FF, etc
 Depends on present and previous inputs
 Made up of an assembly of logic gates

3. Introduction
 A sequential circuit consists of a
feedback path, and employs some
memory elements.
Combinational
logic
Memory
elements
Combinational
outputs Memory outputs
External inputs
Sequential circuit = Combinational logic + Memory Elements

4.  There are two types of sequential circuits:
synchronous: outputs change only at specific time
asynchronous: outputs change at any time
 Multivibrator: a class of sequential circuits. They can be:
bistable (2 stable states : SET and RESET)
monostable or one-shot (1 stable state)
astable (no stable state)
 Bistable logic devices: latches and flip-flops.
 Latches and flip-flops differ in the method used for
changing their state.

5. Memory Elements
 Memory element: a device which can
remember value indefinitely, or change
value on command from its inputs.
command
Memory
element stored value
Q

6. Memory Elements
 Memory element with clock. Flip-flops
are memory elements that change
state on clock signals.
 Clock is usually a square wave.
command
Memory
element stored value
Q
clock
Positive edges Negative edges
Positive pulses

7. Memory Elements
 Two types of triggering/activation:
pulse-triggered
edge-triggered
 Pulse-triggered
latches
ON = 1, OFF = 0
 Edge-triggered
flip-flops
positive edge-triggered (ON = from 0 to 1; OFF = other
time)
negative edge-triggered (ON = from 1 to 0; OFF =
other time)

8. Set-Reset Latch (S-R)
SR Latch
 Latch is a type of bistable(2 stable state) / multivibrator.
The latch is type of temporary storage device that has two stable state
 Active HIGH i/put S-R formed with 2 cross-couple NOR gates.
 Active LOW i/put S-R formed with 2 cross-couple NAND gates.
 O/put of each gate is connected to an i/put of the opposite gate.
 Produces the regenerative f/back that is characteristic of all latches & FFs.

9. ii. Active LOW i/put S-R Latch
S
R
Q
Q
S
R
S R Q Q Comments
0 0 1 1 INVALID
0 1 1 0 SET
1 0 0 1 RESET
1 1 NC NC No Change (remain
present state)
Symbol & Truth Table
i. Active HIGH i/put S-R Latch
S
R
Q
Q
S R Q Q Comments
0 0 NC NC No Change (remain
present state)
0 1 0 1 RESET
1 0 1 0 SET
1 1 0 0 INVALID

10. Example 1
Determine the w/form that will be observed on the Q o/put. Assume that Q is initially
Low.
S
R
Q
Q
S
R
S
R
Q
1
0
1
0
1
0

11. Exercise 1
Determine the Q o/put of an active HIGH i/put S-R latch if the w/form in example 1
are inverted & applied to the i/puts.
S
R
Q
Q
S
R
Q

12. Exercise 2
S
R
Q
Q
>1
A
B
CA
B
C
The i/puts to an active HIGH S-R latch and the circuit diagram are given below.
Draw the timing diagram o/put Q, Q’ for the latch. Assume Q start with 0.

13. Flip-Flop (FF)
 In digital system, FF is an electronic circuit which has two
stable states and thereby is capable of serving as one bit of
memory, bit 1 or bit 0.
Synchronous means: O/put changes state at specified point
on the triggering i/put (called “CLOCK” - CLK). Clock (C) is
designated as a ctrl input.
Change in the o/put occur in synchronization with the clock.

14. Flip-Flop (FF)
Edge-triggered ff: changes state either at the +ve edge
(rising edge) / at –ve (falling edge) of the clock pulse &
sensitive to its i/put only at this transition of clock.
 3 types of ff: S-R, D & J-K.
whenever we refer to the the state of the flip flop, we refer
to the state of its normal output (Q)
Input 1
Input 2
Q
Q
C
Normal output
Inverted output

15. Symbol of FFs
S
R
Q
Q
C
S
R
Q
Q
C
D Q
Q
C
D Q
Q
C
J
K
Q
Q
C
J
K
Q
Q
C
+ve edge triggered (No bubble ‘C’ i/put)
-ve edge triggered (Bubble ‘C’ i/put)
C
 Dynamic i/put indicator
 Identifying an edge triggered ffs, small triangle inside at
clock (C) i/put

16. S-R FF
 Called synchronous i/put because data on i/put transferred
to the ff o/put only on triggering edge of clock pulse.
Logic Circuit (S-R FF active Low)

17. No Change condition

18. Set

19. Reset

20. Invalid

21. Truth Table (+ve edge-triggered S-R FF Active high)
S R CLK Q Q Comments
0 0 X (don’t
care )
Qo Qo NC
0 1 0 1 RESET
1 0 1 0 SET
1 1 ? ? INVALID S
R
Q
Q
C

22. Example 1
Determine the Q & Q o/put w/form of the ff for the S-R & CLK i/put. Assume that
the +ve edge-triggered ff is initially RESET.
S
R
Q
Q
C
CLK
S
R
Q
Q
1 2 3 4 5 6

23. Example 2
Determine the Q o/put w/form of the ff for the S-R & CLK i/put. Assume that the -ve
edge triggered ff is initially RESET.
S
R
Q
Q
C
CLK
S
R
Q
1 2 3 4 5 6

24. Exercise 1
Figure indicates an Ex-OR logic gate is connected to an S-R ff. Based
on figure given, complete the truth table.
S
R
Q
Q
C
SET
CLR
A B S R Q Q’
0 0 1
0 1 0
1 0 0
1 1 1
R
0
1
1
0
Q
1
0
0
1
Q’
0
1
1
0

25. Truth Table (+ve edge-triggered S-R FF Active Low)
S R CLK Q Q Comments
0 0 X (don’t
care )
Qo Qo INVALID
0 1 1 0 SET
1 0 0 1 RESET
1 1 ? ? NC S
R
Q
Q
C

26. D FF
 Also known as Data FF
Can be constructed from SR FF or JK FF by addition of an
inverter.
Logic circuit for D FF

27. S
R
Q
Q
C
SET
CLR
D
CLK
D Q
Q
C
+ve edge-triggered D FF formed with S-R FF & inverter
Truth Table (+ve edge-triggered D FF)
D CLK Q Q Comments
1 1 0 SET (store 1)
0 0 1 RESET (store 0)
Q follow D at the active or triggering clock edge

28. Example 1
Given the w/form in figure for the D i/put & the clock, determine the Q o/put
w/form if the ff starts out RESET.
D Q
Q
C
1 2 3 4
CLK
D
Q

29. J-K FF

30. J-K FF
Circuit (+ve edge-triggered J-K FF)
Basic internal logic for a +ve edge-triggered J-K ff

31. Truth Table (+ve edge-triggered J-K FF)
J K CLK Q Q Comments
0 0 Qo Qo NC
0 1 0 1 RESET
1 0 1 0 SET
1 1 Qo Qo TOGGLE
J
K
Q
Q
C

32. Example 1
The w/form in figure are applied to the J-K & clock i/put as
indicated. Determine the Q o/put, assuming that the ff in
initially RESET.
1 2 3 4
CLK
J
Q
5
J
K
Q
Q
C
K
Toggle NC Reset Set Set

33. The w/form in figure are applied to the ff as shown. Determine the Q o/put,
starting in initially RESET state.
Example 2
J
K
Q
Q
C
CLK
J
K
Q
1 2 3 4 5 6 7
NC Toggle Reset Set Set Toggle Reset

34. Exercise 1
CLK
J
K
Q
Redraw and complete the output of the timing diagram in figure for J-K ff.
Assume +ve edge ff.

35. Exercise 2
Figure given indicate an EX-OR logic gate connected to a J-K ff. O/put Q of J-K
is connected to i/put R of S-R ff. Based on figure, complete the truth table in table
given.
J
K
Q
Q
C
SET
CLR
S
R
Q
Q
C
SET
CLR
A B J K S R Q of SR ff
0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
J
0
1
1
0
R
0
1
1
0
Q of SR ff
1
0
0
1

36. Asynchronous Preset & Clear I/put
 FF: (SR, D & JK – synchronous i/put)
- because data on these i/put transferred to ff o/put only on
triggering edge of clock pulse.
- that is, data are transferred synchronous with clock.
 Most integrated circuit ff also have asynchronous i/put.
 These are i/put that affect the state of the ff independent of the
clock.

37. Normally labeled as Preset (PRE) & Clear (CLR)/ Direct Set
(SD) & Direct Reset (RD).
 An active level on the Preset i/put will set ff & an active level
on the Clear i/put will reset it.

38.  A logic symbol for J-K ff with Preset & Clear i/put as below:
 These i/put are active LOW, as indicated by the bubbles.
 In normal operation, Preset & Clear would not be LOW at the
same time.
J
K
Q
Q
C
PRE
CLR
J-K ff with active LOW Preset & Clear i/put

39. Logic diagram for a basic JK ff with active LOW Preset & Clear

40. Example 1
If interchange the PRE & CLR w/form in example 1, what will the Q o/put look
like?
J
K
Q
Q
C
PRE
CLR
HIGH
1 2 3 4 5 6 7 8 9
ToggleCLR active LOW
PRE active LOW
CLK
PRE
CLR
Q
Initial LOW